* [U-Boot-Users] [PATCH 1/6] AT572D940HF-EB Support v2 (board folder)
@ 2008-06-12 14:14 Antonio R. Costa
2008-06-12 14:14 ` [U-Boot-Users] [PATCH 1/2] AT572D940HF-EB Support v2 (SDHC support part 1) Antonio R. Costa
0 siblings, 1 reply; 26+ messages in thread
From: Antonio R. Costa @ 2008-06-12 14:14 UTC (permalink / raw)
To: u-boot
Signed-off-by: Antonio R. Costa <antonio.costa@atmel.com>
diff --git a/board/atmel/at572d940hfeb/Makefile b/board/atmel/at572d940hfeb/Makefile
new file mode 100644
index 0000000..c91bea6
--- /dev/null
+++ b/board/atmel/at572d940hfeb/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd <at> denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y += at572d940hfeb.o
+COBJS-y += partition.o
+COBJS-y += flash.o
+COBJS-$(CONFIG_CMD_NAND) += nand.o
+COBJS-$(CONFIG_CMD_MMC) += atmel_mci.o
+COBJS-$(CONFIG_USE_IRQ) += interrupts.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/atmel/at572d940hfeb/at572d940hfeb.c b/board/atmel/at572d940hfeb/at572d940hfeb.c
new file mode 100644
index 0000000..95cedc2
--- /dev/null
+++ b/board/atmel/at572d940hfeb/at572d940hfeb.c
@@ -0,0 +1,251 @@
+/* (C) 2008 Copyright Atmel Corporation
+ *
+ * Antonio R. Costa <antonio.costa <at> atmel.com>
+ * <costa.antonior <at> gmail.com>
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop <at> leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at572d940hf.h>
+#include <asm/arch/at572d940hf_matrix.h>
+#include <asm/arch/at572d940hf_mc.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#include <asm/arch/at91_aic.h>
+#include <asm/arch/interrupts.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ----------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+static void AT572D940HFEB_serial_hw_init(void)
+{
+#ifdef CONFIG_USART0
+ at91_set_A_periph(AT91_PIN_PA8, 1); /* TXD0 */
+ at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
+#endif
+
+#ifdef CONFIG_USART1
+ at91_set_A_periph(AT91_PIN_PC10, 1); /* TXD1 */
+ at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD1 */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
+#endif
+
+#ifdef CONFIG_USART2
+ at91_set_A_periph(AT91_PIN_PC15, 1); /* TXD2 */
+ at91_set_A_periph(AT91_PIN_PC14, 0); /* RXD2 */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
+#endif
+
+#ifdef CONFIG_USART3 /* DBGU */
+ at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
+ at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
+#endif
+}
+
+#ifdef CONFIG_CMD_NAND
+static void AT572D940HFEB_nand_hw_init(void)
+{
+ unsigned long csa;
+
+ /* Enable CS3 */
+ csa = at91_sys_read(AT91_MATRIX_EBICSA);
+ at91_sys_write(AT91_MATRIX_EBICSA,
+ csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ at91_sys_write(AT91_SMC_SETUP(3),
+ AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
+ AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+ at91_sys_write(AT91_SMC_PULSE(3),
+ AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
+ AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
+ at91_sys_write(AT91_SMC_CYCLE(3),
+ AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+ at91_sys_write(AT91_SMC_MODE(3),
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_EXNWMODE_DISABLE |
+ AT91_SMC_DBW_8 | AT91_SMC_TDF_(2));
+
+ at91_sys_write(AT91_PMC_PCER, 1 << AT572D940HF_ID_PIOC);
+
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(AT91_PIN_PC16, 1);
+
+ /* Enable NandFlash */
+ /* By DIP switch on AT572D940HFEB */
+ at91_set_gpio_output(AT91_PIN_PC14, 1);
+}
+#endif
+
+#ifdef CONFIG_HAS_DATAFLASH
+static void AT572D940HFEB_spi_hw_init(void)
+{
+ at91_set_A_periph(AT91_PIN_PA3, 0); /* SPI0_NPCS0 */
+ at91_set_A_periph(AT91_PIN_PA4, 0); /* SPI0_NPCS1 */
+
+ at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
+ at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
+ at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
+
+ /* Enable clock */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT572D940HF_ID_SPI0);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void AT572D940HFEB_macb_hw_init(void)
+{
+ /* Enable clock */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT572D940HF_ID_EMAC);
+
+ at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXCK_EREFCK */
+ at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */
+ at91_set_A_periph(AT91_PIN_PA18, 0); /* ERX0 */
+ at91_set_A_periph(AT91_PIN_PA19, 0); /* ERX1 */
+ at91_set_A_periph(AT91_PIN_PA20, 0); /* ERXER */
+ at91_set_A_periph(AT91_PIN_PA23, 0); /* ETXEN */
+ at91_set_A_periph(AT91_PIN_PA21, 0); /* ETX0 */
+ at91_set_A_periph(AT91_PIN_PA22, 0); /* ETX1 */
+ at91_set_A_periph(AT91_PIN_PA13, 0); /* EMDIO */
+ at91_set_A_periph(AT91_PIN_PA14, 0); /* EMDC */
+ at91_set_A_periph(AT91_PIN_PA15, 0); /* EFCE100 */
+}
+#endif
+
+#ifdef CONFIG_MMC
+static void AT572D940HFEB_mci_hw_init(void)
+{
+ at91_sys_write(AT91_PMC_PCER, (1 << AT572D940HF_ID_MCI));
+
+ at91_set_A_periph(AT91_PIN_PC22,0);
+ at91_set_A_periph(AT91_PIN_PC23,0);
+ at91_set_A_periph(AT91_PIN_PC24,0);
+ at91_set_A_periph(AT91_PIN_PC25,0);
+ at91_set_A_periph(AT91_PIN_PC26,0);
+ at91_set_A_periph(AT91_PIN_PC27,0);
+}
+#endif
+
+#ifdef CONFIG_USBH
+static void AT572D940HFEB_usbh_hw_init(void)
+{
+ at91_sys_write(AT91_PMC_PCER, (1 << AT572D940HF_ID_UHP));
+ at91_sys_write(AT91_PMC_SCER, AT572D940HF_PMC_UHP);
+}
+
+int rstc_init(void)
+{
+ /* Reads the SR to clean from
+ * previous resets
+ */
+ at91_sys_read(AT91_RSTC_SR);
+
+ /* Disble the USR_RST line,
+ * enable USR_RST_INT and
+ * sets the EXT_RST length to 2^14
+ * (500ms needed by the phy)
+ */
+ at91_sys_write(AT91_RSTC_MR,
+ (0xa5<<24) | (13<<8) | AT91_RSTC_URSTIEN);
+ return 0;
+}
+
+int board_init(void)
+{
+
+ /* Init the reset controller */
+ rstc_init();
+
+ /* Init interrupts */
+ interrupts_init();
+
+ /* Enable Ctrlc */
+ console_init_f();
+
+ /* arch number of AT572D940HFEB-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_AT572D940HFEB;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ AT572D940HFEB_serial_hw_init();
+
+#ifdef CONFIG_CMD_NAND
+ AT572D940HFEB_nand_hw_init();
+#endif
+
+#ifdef CONFIG_HAS_DATAFLASH
+ AT572D940HFEB_spi_hw_init();
+#endif
+
+#ifdef CONFIG_MACB
+ AT572D940HFEB_macb_hw_init();
+#endif
+
+#ifdef CONFIG_MMC
+ AT572D940HFEB_mci_hw_init();
+#endif
+
+#ifdef CONFIG_USBH
+ AT572D940HFEB_usbh_hw_init();
+#endif
+
+#endif
+ gd->flags |= GD_FLG_RELOC;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+ return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_MACB
+ /*
+ * Initialize ethernet HW addr prior to starting Linux,
+ * needed for nfsroot
+ */
+ eth_init(gd->bd);
+#endif /* CONFIG_MACB */
+}
+#endif /* CONFIG_RESET_PHY_R */
+
+#endif /* CONFIG_CMD_NET */
diff --git a/board/atmel/at572d940hfeb/config.mk b/board/atmel/at572d940hfeb/config.mk
new file mode 100644
index 0000000..ff2cfd1
--- /dev/null
+++ b/board/atmel/at572d940hfeb/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x23f00000
diff --git a/board/atmel/at572d940hfeb/flash.c b/board/atmel/at572d940hfeb/flash.c
new file mode 100644
index 0000000..652a29b
--- /dev/null
+++ b/board/atmel/at572d940hfeb/flash.c
@@ -0,0 +1,524 @@
+/*
+ * (C) Copyright 2002
+ * Lineo, Inc. <www.lineo.com>
+ * Bernhard Kuhn <bkuhn@lineo.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+ulong myflush(void);
+
+
+/* Flash Organization Structure */
+typedef struct OrgDef
+{
+ unsigned int sector_number;
+ unsigned int sector_size;
+} OrgDef;
+
+
+/* Flash Organizations */
+
+OrgDef OrgAT49BV642D[] =
+{
+ { 8, 4*1024 },
+ { 58, 32*1024 },
+};
+
+OrgDef OrgAT49BV16x4[] =
+{
+ { 8, 8*1024 }, /* 8 * 8 kBytes sectors */
+ { 2, 32*1024 }, /* 2 * 32 kBytes sectors */
+ { 30, 64*1024 }, /* 30 * 64 kBytes sectors */
+};
+
+OrgDef OrgAT49BV16x4A[] =
+{
+ { 8, 8*1024 }, /* 8 * 8 kBytes sectors */
+ { 31, 64*1024 }, /* 31 * 64 kBytes sectors */
+};
+
+OrgDef OrgAT49BV6416[] =
+{
+ { 8, 8*1024 }, /* 8 * 8 kBytes sectors */
+ { 127, 64*1024 }, /* 127 * 64 kBytes sectors */
+};
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+/* AT49BV1614A Codes */
+#define FLASH_CODE1 0xAA
+#define FLASH_CODE2 0x55
+#define ID_IN_CODE 0x90
+#define ID_OUT_CODE 0xF0
+
+
+#define CMD_READ_ARRAY 0x00F0
+#define CMD_UNLOCK1 0x00AA
+#define CMD_UNLOCK2 0x0055
+#define CMD_ERASE_SETUP 0x0080
+#define CMD_ERASE_CONFIRM 0x0030
+#define CMD_PROGRAM 0x00A0
+#define CMD_UNLOCK_BYPASS 0x0020
+#define CMD_SECTOR_UNLOCK 0x0070
+
+#define MEM_FLASH_ADDR1 (*(volatile u16 *) \
+ (CFG_FLASH_BASE + (0x00005555<<1)))
+#define MEM_FLASH_ADDR2 (*(volatile u16 *) \
+ (CFG_FLASH_BASE + (0x00002AAA<<1)))
+
+#define BIT_ERASE_DONE 0x0080
+#define BIT_RDY_MASK 0x0080
+#define BIT_PROGRAM_ERROR 0x0020
+#define BIT_TIMEOUT 0x80000000 /* our flag */
+
+#define READY 1
+#define ERR 2
+#define TMO 4
+
+/*-----------------------------------------------------------------------
+ */
+void flash_identification (flash_info_t * info)
+{
+ volatile u16 manuf_code, device_code, add_device_code;
+
+ MEM_FLASH_ADDR1 = FLASH_CODE1;
+ MEM_FLASH_ADDR2 = FLASH_CODE2;
+ MEM_FLASH_ADDR1 = ID_IN_CODE;
+
+ manuf_code = *(volatile u16 *) CFG_FLASH_BASE;
+ device_code = *(volatile u16 *) (CFG_FLASH_BASE + 2);
+ add_device_code = *(volatile u16 *) (CFG_FLASH_BASE + (3 << 1));
+
+ MEM_FLASH_ADDR1 = FLASH_CODE1;
+ MEM_FLASH_ADDR2 = FLASH_CODE2;
+ MEM_FLASH_ADDR1 = ID_OUT_CODE;
+
+ /* Vendor type */
+ info->flash_id = ATM_MANUFACT & FLASH_VENDMASK;
+ printf ("Atmel: ");
+
+ if ((device_code & FLASH_TYPEMASK) ==
+ (ATM_ID_BV1614 & FLASH_TYPEMASK)) {
+
+ if ((add_device_code & FLASH_TYPEMASK) ==
+ (ATM_ID_BV1614A & FLASH_TYPEMASK)) {
+ info->flash_id |= ATM_ID_BV1614A & FLASH_TYPEMASK;
+ printf ("AT49BV1614A (16Mbit)\n");
+ } else { /* AT49BV1614 Flash */
+ info->flash_id |= ATM_ID_BV1614 & FLASH_TYPEMASK;
+ printf ("AT49BV1614 (16Mbit)\n");
+ }
+
+ } else if ((device_code & FLASH_TYPEMASK) ==
+ (ATM_ID_BV6416 & FLASH_TYPEMASK)) {
+ info->flash_id |= ATM_ID_BV6416 & FLASH_TYPEMASK;
+ printf ("AT49BV6416 (64Mbit)\n");
+ }
+}
+
+ushort flash_number_sector(OrgDef *pOrgDef, unsigned int nb_blocks)
+{
+ int i, nb_sectors = 0;
+
+ for (i=0; i<nb_blocks; i++){
+ nb_sectors += pOrgDef[i].sector_number;
+ }
+
+ return nb_sectors;
+}
+
+void flash_unlock_sector(flash_info_t * info, unsigned int sector)
+{
+ volatile u16 *addr = (volatile u16 *) (info->start[sector]);
+
+ MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+ *addr = CMD_SECTOR_UNLOCK;
+}
+
+
+ulong flash_init (void)
+{
+ int i, j, k;
+ unsigned int flash_nb_blocks, sector;
+ unsigned int start_address;
+ OrgDef *pOrgDef;
+
+ ulong size = 0;
+
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+ ulong flashbase = 0;
+
+ flash_identification (&flash_info[i]);
+
+ if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+ (ATM_ID_BV1614 & FLASH_TYPEMASK)) {
+
+ pOrgDef = OrgAT49BV16x4;
+ flash_nb_blocks = sizeof (OrgAT49BV16x4) /
+ sizeof (OrgDef);
+ } else if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+ (ATM_ID_BV1614A & FLASH_TYPEMASK)){
+ /* AT49BV1614A Flash */
+
+ pOrgDef = OrgAT49BV16x4A;
+ flash_nb_blocks = sizeof (OrgAT49BV16x4A) /
+ sizeof (OrgDef);
+ } else if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+ (ATM_ID_BV6416 & FLASH_TYPEMASK)){
+ /* AT49BV6416 Flash */
+
+ pOrgDef = OrgAT49BV6416;
+ flash_nb_blocks = sizeof (OrgAT49BV6416) /
+ sizeof (OrgDef);
+ } else {
+ flash_nb_blocks = 0;
+ pOrgDef = OrgAT49BV16x4;
+ }
+
+ flash_info[i].sector_count =
+ flash_number_sector(pOrgDef, flash_nb_blocks);
+ memset(flash_info[i].protect, 0, flash_info[i].sector_count);
+
+ if (i == 0)
+ flashbase = PHYS_FLASH_1;
+ else
+ panic ("configured too many flash banks!\n");
+
+ sector = 0;
+ start_address = flashbase;
+ flash_info[i].size = 0;
+
+ for (j = 0; j < flash_nb_blocks; j++) {
+ for (k = 0; k < pOrgDef[j].sector_number; k++) {
+ flash_info[i].start[sector++] =
+ start_address;
+ start_address += pOrgDef[j].sector_size;
+ flash_info[i].size += pOrgDef[j].sector_size;
+ }
+ }
+
+ size += flash_info[i].size;
+
+ if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+ (ATM_ID_BV6416 & FLASH_TYPEMASK)){
+ /* AT49BV6416 Flash */
+
+ /* Unlock all sectors@reset */
+ for (j=0; j<flash_info[i].sector_count; j++) {
+ flash_unlock_sector(&flash_info[i], j);
+ }
+ }
+ }
+
+ /* Protect binary boot image */
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_FLASH_BASE,
+ CFG_FLASH_BASE + CFG_BOOT_SIZE - 1, &flash_info[0]);
+
+ /* Protect environment variables */
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+ /* Protect U-Boot gzipped image */
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_U_BOOT_BASE,
+ CFG_U_BOOT_BASE + CFG_U_BOOT_SIZE - 1,
+ &flash_info[0]);
+
+ return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+ int i;
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case (ATM_MANUFACT & FLASH_VENDMASK):
+ printf ("Atmel: ");
+ break;
+ default:
+ printf ("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case (ATM_ID_BV1614 & FLASH_TYPEMASK):
+ printf ("AT49BV1614 (16Mbit)\n");
+ break;
+ case (ATM_ID_BV1614A & FLASH_TYPEMASK):
+ printf ("AT49BV1614A (16Mbit)\n");
+ break;
+ case (ATM_ID_BV6416 & FLASH_TYPEMASK):
+ printf ("AT49BV6416 (64Mbit)\n");
+ break;
+ default:
+ printf ("Unknown Chip Type\n");
+ return;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; i++) {
+ if ((i % 5) == 0) {
+ printf ("\n ");
+ }
+ printf (" %08lX%s", info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+ }
+ printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+ ulong result;
+ int iflag, cflag, prot, sect;
+ int rc = ERR_OK;
+ int chip1;
+
+ /* first look for protection bits */
+
+ if (info->flash_id == FLASH_UNKNOWN)
+ return ERR_UNKNOWN_FLASH_TYPE;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ return ERR_INVAL;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) !=
+ (ATM_MANUFACT & FLASH_VENDMASK)) {
+ return ERR_UNKNOWN_FLASH_VENDOR;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+ if (prot)
+ return ERR_PROTECTED;
+
+ /*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+ cflag = icache_status ();
+ icache_disable ();
+ iflag = disable_interrupts ();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+ printf ("Erasing sector %2d ... ", sect);
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked ();
+
+ if (info->protect[sect] == 0) { /* not protected */
+ volatile u16 *addr =
+ (volatile u16 *) (info->start[sect]);
+
+ MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+ MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+ MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+ MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+ MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+ *addr = CMD_ERASE_CONFIRM;
+
+ /* wait until flash is ready */
+ chip1 = 0;
+
+ do {
+ result = *addr;
+
+ /* check timeout */
+ if(get_timer_masked()>CFG_FLASH_ERASE_TOUT) {
+ MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+ chip1 = TMO;
+ break;
+ }
+
+ if(!chip1 && (result & 0xFFFF) &
+ BIT_ERASE_DONE)
+ chip1 = READY;
+
+ } while (!chip1);
+
+ MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+ if (chip1 == ERR) {
+ rc = ERR_PROG_ERROR;
+ goto outahere;
+ }
+ if (chip1 == TMO) {
+ rc = ERR_TIMOUT;
+ goto outahere;
+ }
+
+ printf ("ok.\n");
+ } else { /* it was protected */
+ printf ("protected!\n");
+ }
+ }
+
+ if (ctrlc ())
+ printf ("User Interrupt!\n");
+
+outahere:
+ /* allow flash to settle - wait 10 ms */
+ udelay_masked (10000);
+
+ if (iflag)
+ enable_interrupts ();
+
+ if (cflag)
+ icache_enable ();
+
+ return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+ volatile u16 *addr = (volatile u16 *) dest;
+ ulong result;
+ int rc = ERR_OK;
+ int cflag, iflag;
+ int chip1;
+
+ /*
+ * Check if Flash is (sufficiently) erased
+ */
+ result = *addr;
+ if ((result & data) != data)
+ return ERR_NOT_ERASED;
+
+ /*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+ cflag = icache_status ();
+ icache_disable ();
+ iflag = disable_interrupts ();
+
+ MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+ MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+ MEM_FLASH_ADDR1 = CMD_PROGRAM;
+ *addr = data;
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked ();
+
+ /* wait until flash is ready */
+ chip1 = 0;
+ do {
+ result = *addr;
+
+ /* check timeout */
+ if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+ chip1 = ERR | TMO;
+ break;
+ }
+ if (!chip1 && ((result & 0x80) == (data & 0x80)))
+ chip1 = READY;
+
+ } while (!chip1);
+
+ *addr = CMD_READ_ARRAY;
+
+ if (chip1 == ERR || *addr != data)
+ rc = ERR_PROG_ERROR;
+
+ if (iflag)
+ enable_interrupts ();
+
+ if (cflag)
+ icache_enable ();
+
+ return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong wp, data;
+ int rc;
+
+ if (addr & 1) {
+ printf ("unaligned destination not supported\n");
+ return ERR_ALIGN;
+ };
+
+ if ((int) src & 1) {
+ printf ("unaligned source not supported\n");
+ return ERR_ALIGN;
+ };
+
+ wp = addr;
+
+ while (cnt >= 2) {
+ data = *((volatile u16 *) src);
+ if ((rc = write_word (info, wp, data)) != 0) {
+ return (rc);
+ }
+ src += 2;
+ wp += 2;
+ cnt -= 2;
+ }
+
+ if (cnt == 1) {
+ data = (*((volatile u8 *) src)) |
+ (*((volatile u8 *) (wp + 1)) << 8);
+ if ((rc = write_word (info, wp, data)) != 0) {
+ return (rc);
+ }
+ src += 1;
+ wp += 1;
+ cnt -= 1;
+ };
+
+ return ERR_OK;
+}
diff --git a/board/atmel/at572d940hfeb/interrupts.c b/board/atmel/at572d940hfeb/interrupts.c
new file mode 100644
index 0000000..1eafa9a
--- /dev/null
+++ b/board/atmel/at572d940hfeb/interrupts.c
@@ -0,0 +1,84 @@
+/*
+ * board/atmel/at572d940hfeb/interrupts.c
+ * Copyright 2008 (C) ATMEL
+ * Antonio R. Costa <antonio.costa <at> atmel.com>
+ * <costa.antonior <at> gmail.com>
+ *
+ * Advanced Interrupt Controller (AIC).
+ * Based on AT572D940HF datasheet.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <common.h>
+#include <asm/arch/at572d940hf.h>
+#include <asm/arch/io.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_aic.h>
+#include <asm/arch/interrupts.h>
+
+irq_handler_t handler_reset(void)
+{
+ unsigned long rstc_sr=0;
+
+ rstc_sr = at91_sys_read(AT91_RSTC_SR);
+ if(rstc_sr & AT91_RSTC_URSTS) {
+ while(!(at91_sys_read(AT91_RSTC_SR) & (1<<16)));
+ reset_cpu(1);
+ };
+}
+
+irq_handler_t handler_ext1(void)
+{
+ puts("--- EXT1 IRQ ---\n");
+}
+
+
+int reset_irqs(void) {
+ unsigned long ul = 0;
+ volatile unsigned long * psrc = _armboot_start;
+ volatile unsigned long * pdest = 0x0;
+
+ /*
+ * Relocates U-Boot ARM IRQ vectors to 0
+ * This is an ugly way to do it.
+ * More support must be offered by start.S
+ * on symbols and macros performing partial relocation
+ */
+
+ while(ul++ < 16)
+ *pdest++ = *psrc++;
+
+
+ /* Reset IRQ vectors */
+ for(ul=0;ul<32;ul++)
+ RESET_IRQ_HANDLER(ul);
+ return 0;
+}
+
+int interrupts_init(void)
+{
+ reset_irqs();
+ SET_IRQ_HANDLER(1 ,0x27,handler_reset);
+ SET_IRQ_HANDLER(30,0x27,handler_ext1);
+ return 0;
+}
+
+
+void do_irq(struct pt_regs* pregs) {
+
+ unsigned long int ivr = AIC_REG(AIC_IVR);
+ unsigned long int isr = AIC_REG(AIC_ISR);
+ void (*irq_handler)(unsigned long int) =
+ (void(*)(unsigned long int)) ivr;
+
+ irq_handler(isr);
+
+ /* Acknowledges irq */
+ IRQ_ACKNOWLEDGE(ivr);
+
+ return;
+};
diff --git a/board/atmel/at572d940hfeb/nand.c b/board/atmel/at572d940hfeb/nand.c
new file mode 100644
index 0000000..0f8dcb9
--- /dev/null
+++ b/board/atmel/at572d940hfeb/nand.c
@@ -0,0 +1,76 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop <at> leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at572d940hf.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91_pio.h>
+
+#include <nand.h>
+
+/*
+ * hardware specific access to control-lines
+ */
+#define MASK_ALE (1 << 21) /* our ALE is AD21 */
+#define MASK_CLE (1 << 22) /* our CLE is AD22 */
+
+static void at91sam9260ek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+ struct nand_chip *this = mtd->priv;
+ ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+
+ IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
+ switch (cmd) {
+ case NAND_CTL_SETCLE:
+ IO_ADDR_W |= MASK_CLE;
+ break;
+ case NAND_CTL_SETALE:
+ IO_ADDR_W |= MASK_ALE;
+ break;
+ case NAND_CTL_CLRNCE:
+ at91_set_gpio_value(AT91_PIN_PC14, 1);
+ break;
+ case NAND_CTL_SETNCE:
+ at91_set_gpio_value(AT91_PIN_PC14, 0);
+ break;
+ }
+ this->IO_ADDR_W = (void *) IO_ADDR_W;
+}
+
+static int at91sam9260ek_nand_ready(struct mtd_info *mtd)
+{
+ return at91_get_gpio_value(AT91_PIN_PC13);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ nand->eccmode = NAND_ECC_SOFT;
+ nand->hwcontrol = at91sam9260ek_nand_hwcontrol;
+ nand->dev_ready = at91sam9260ek_nand_ready;
+ nand->chip_delay = 20;
+
+ return 0;
+}
diff --git a/board/atmel/at572d940hfeb/partition.c b/board/atmel/at572d940hfeb/partition.c
new file mode 100644
index 0000000..389fb2c
--- /dev/null
+++ b/board/atmel/at572d940hfeb/partition.c
@@ -0,0 +1,38 @@
+/*
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
+ {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
+ {CFG_DATAFLASH_LOGIC_ADDR_CS1, 1}
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+ {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
+ {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+ {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
+ {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
+ {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
+};
diff --git a/board/atmel/at572d940hfeb/u-boot.lds b/board/atmel/at572d940hfeb/u-boot.lds
new file mode 100644
index 0000000..05a6d83
--- /dev/null
+++ b/board/atmel/at572d940hfeb/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj <at> denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm926ejs/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
--
1.5.4.3
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [U-Boot-Users] [PATCH 1/2] AT572D940HF-EB Support v2 (SDHC support part 1)
2008-06-12 14:14 [U-Boot-Users] [PATCH 1/6] AT572D940HF-EB Support v2 (board folder) Antonio R. Costa
@ 2008-06-12 14:14 ` Antonio R. Costa
2008-06-12 14:14 ` [U-Boot-Users] [PATCH 2/2] AT572D940HF-EB Support v2 (SDHC support part 2) Antonio R. Costa
2008-06-12 16:36 ` [U-Boot-Users] [PATCH 1/2] AT572D940HF-EB Support v2 (SDHC support part 1) Haavard Skinnemoen
0 siblings, 2 replies; 26+ messages in thread
From: Antonio R. Costa @ 2008-06-12 14:14 UTC (permalink / raw)
To: u-boot
This patch add support for SD/SDHC cards to AT572D940HF-EB
and more generally is a proposal for all Atmel chips.
Dued to that I placed atmel_mci.c under the board directory.
Plaese give me some feedbacks.
The implementation of the CSD interpretation has been re-worked
completely. Bit fields are not portable so there were replaced by
a vector of 4 32-bit words and some macros.
Probing process follow the schema from SD spec 2.0:
sdhc --> sd --> mmc
Introduced IF_TYPE_SDHC to distinguish between SD and SDHC.
Maybe this is not the best method since struct block_dev_descr.priv
could point to a structure describing card properties but it was
the quickest one and I had no time to spend.
Tested SD:
- Mediacom 512 MB (spec 1.0) bare FAT16 no partition table
- Kingstone 1 GB (spec 1.0) 1 FAT16
- Trascend 2 GB (spec 1.01) 1 FAT16
- TakeMS 4 GB (spec 1.10) 1 FAT16
Tested SDHC:
- Peak 8 GB (spec 2.0) 1 FAT32
Signed-off-by: Antonio R. Costa <antonio.costa@atmel.com>
diff --git a/board/atmel/at572d940hfeb/atmel_mci.c b/board/atmel/at572d940hfeb/atmel_mci.c
new file mode 100644
index 0000000..2aa2588
--- /dev/null
+++ b/board/atmel/at572d940hfeb/atmel_mci.c
@@ -0,0 +1,799 @@
+/*
+ * (C) Copyright 2008 Atmel Corporation
+ *
+ * Antonio R. Costa <antonio.costa <at> atmel.com>
+ * <costa.antonior <at> gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_MMC
+
+#include <part.h>
+#include <mmc.h>
+
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/byteorder.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/memory-map.h>
+#include <asm/arch/timer.h>
+#include <fat.h>
+
+#include <asm/arch/atmel_mci.h>
+
+#ifdef DEBUG
+#define pr_debug(fmt, args...) printf(fmt, ##args)
+#else
+#define pr_debug(...) do { } while(0)
+#endif
+
+#ifndef CFG_MMC_CLK_OD
+#define CFG_MMC_CLK_OD 150000
+#endif
+
+#ifndef CFG_MMC_CLK_PP
+#define CFG_MMC_CLK_PP 5000000
+#endif
+
+#ifndef CFG_MMC_OP_COND
+#define CFG_MMC_OP_COND 0x401f8000
+#endif
+
+#define MMC_DEFAULT_BLKLEN 512
+#define MMC_DEFAULT_RCA 1
+
+static unsigned int mmc_rca;
+static int mmc_card_is_sd;
+static block_dev_desc_t mmc_blkdev;
+
+block_dev_desc_t *mmc_get_dev(int dev)
+{
+ return &mmc_blkdev;
+}
+
+static int mci_reset(void)
+{
+
+ mmci_writel(CR, MMCI_BIT(SWRST));
+ mmci_writel(CR, MMCI_BIT(MCIEN));
+ mmci_writel(CR, MMCI_BIT(PWSDIS));
+
+ mmci_writel(CMDR, (1 << 11) | (1 << 8)); /* Init command */
+ while (!(mmci_readl(SR) & MMCI_BIT(CMDRDY))) ;
+ return 0;
+}
+
+static void mci_set_mode(unsigned long hz, unsigned long blklen)
+{
+ unsigned long bus_hz;
+ unsigned long clkdiv;
+
+ bus_hz = get_mci_clk_rate();
+ clkdiv = (bus_hz / hz) / 2 - 1;
+
+ pr_debug("mmc: setting clock %lu Hz, clkdiv %lu, block size %lu\n",
+ hz, clkdiv, blklen);
+
+ if (clkdiv & ~255UL) {
+ clkdiv = 255;
+ printf("mmc: clock %lu too low; setting CLKDIV to 255\n",
+ hz);
+ }
+
+ blklen &= 0xfffc;
+ mmci_writel(MR, (MMCI_BF(CLKDIV, clkdiv)
+ | MMCI_BF(BLKLEN, blklen)
+ | MMCI_BIT(RDPROOF)
+ | MMCI_BIT(WRPROOF)));
+}
+
+#define RESP_NO_CRC 1
+#define R1 MMCI_BF(RSPTYP, 1) /* 48-bit CRC */
+#define R2 MMCI_BF(RSPTYP, 2) /* 136-bit CRC*/
+#define R3 (R1 | RESP_NO_CRC)
+#define R6 R1
+#define R7 R1
+#define NID MMCI_BF(MAXLAT, 0)
+#define NCR MMCI_BF(MAXLAT, 1)
+#define TRCMD_START MMCI_BF(TRCMD, 1)
+#define TRDIR_READ MMCI_BF(TRDIR, 1)
+#define TRTYP_BLOCK MMCI_BF(TRTYP, 0)
+#define INIT_CMD MMCI_BF(SPCMD, 1)
+#define OPEN_DRAIN MMCI_BF(OPDCMD, 1)
+
+#define ERROR_FLAGS (MMCI_BIT(DTOE) \
+ | MMCI_BIT(RDIRE) \
+ | MMCI_BIT(RENDE) \
+ | MMCI_BIT(RINDE) \
+ | MMCI_BIT(RTOE))
+
+static int
+mmc_cmd(unsigned long cmd, unsigned long arg, void *resp,
+ unsigned long flags)
+{
+ unsigned long *response = resp;
+ int i, response_words = 0;
+ unsigned long error_flags;
+ u32 status;
+
+ pr_debug("mmc: CMD%lu 0x%lx (flags 0x%lx)\n", cmd, arg, flags);
+
+ error_flags = ERROR_FLAGS;
+ if (!(flags & RESP_NO_CRC))
+ error_flags |= MMCI_BIT(RCRCE);
+
+ flags &= ~MMCI_BF(CMDNB, ~0UL);
+
+ if (MMCI_BFEXT(RSPTYP, flags) == MMCI_RSPTYP_48_BIT_RESP)
+ response_words = 1;
+ else if (MMCI_BFEXT(RSPTYP, flags) == MMCI_RSPTYP_136_BIT_RESP)
+ response_words = 4;
+
+ mmci_writel(ARGR, arg);
+ mmci_writel(CMDR, cmd | flags);
+ do {
+ udelay(40);
+ status = mmci_readl(SR);
+ } while (!(status & MMCI_BIT(CMDRDY)));
+
+ pr_debug("mmc: status 0x%08lx\n", status);
+
+ if (status & ERROR_FLAGS) {
+ printf("mmc: command %lu failed (status: 0x%08lx)\n",
+ cmd, status);
+ return -EIO;
+ }
+
+ if (response_words)
+ pr_debug("mmc: response:");
+
+ for (i = 0; i < response_words; i++) {
+ response[i] = mmci_readl(RSPR);
+ pr_debug(" %08lx", response[i]);
+ }
+ pr_debug("\n");
+
+ return 0;
+}
+
+static int mmc_acmd(unsigned long cmd, unsigned long arg, void *resp,
+ unsigned long flags) __attribute ((noinline));
+
+static int mmc_acmd(unsigned long cmd, unsigned long arg,
+ void *resp, unsigned long flags)
+{
+ unsigned long aresp[4];
+ int ret;
+
+ /*
+ * Seems like the APP_CMD part of an ACMD has 64 cycles max
+ * latency even though the ACMD part doesn't. This isn't
+ * entirely clear in the SD Card spec, but some cards refuse
+ * to work if we attempt to use 5 cycles max latency here...
+ */
+
+ pr_debug("acmd: flags 0x%lx \n", flags);
+ ret = mmc_cmd(MMC_CMD_APP_CMD, 0, aresp,
+ R1 | NCR | (flags & OPEN_DRAIN));
+ if (ret)
+ return ret;
+ if ((aresp[0] & (R1_ILLEGAL_COMMAND | R1_APP_CMD)) != R1_APP_CMD)
+ return -EIO;
+
+ ret = mmc_cmd(cmd, arg, resp, flags);
+
+ return ret;
+}
+
+static unsigned long
+mmc_bread(int dev, unsigned long start, lbaint_t blkcnt,
+ unsigned long *buffer)
+{
+ int ret, start_inc = 0, i = 0;
+ unsigned long resp[4];
+ unsigned long card_status;
+ unsigned long wordcount;
+ u32 status;
+
+ if (blkcnt == 0)
+ return 0;
+
+ /*
+ * ARC:
+ * For SDHC cards start is the number of the first block to read;
+ * for regular SD cards start is the address of the first byte to
+ * read
+ */
+ start = (mmc_blkdev.if_type == IF_TYPE_SDHC) ? start : start * 512;
+ start_inc = (mmc_blkdev.if_type == IF_TYPE_SDHC) ? 1 : 512;
+
+ pr_debug("mmc_bread: dev %d, type %u, start %lx," \
+ " blkcnt %lx buffer: 0x%p\n",dev,
+ mmc_blkdev.if_type, start, blkcnt, buffer);
+
+ /* Put the device into Transfer state */
+ ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, R1 | NCR);
+
+ if (ret)
+ goto out;
+
+ /*
+ * ARC: set the bus width to 4-bits
+ * 0x1 1-bit, 0x2 4-bits
+ */
+ if ((mmc_blkdev.if_type == IF_TYPE_SD)
+ || (mmc_blkdev.if_type == IF_TYPE_SDHC)) {
+ unsigned long resp[4];
+ ret = mmc_cmd(MMC_CMD_APP_CMD, mmc_rca << 16,
+ resp, R1 | NCR);
+ if (ret)
+ return ret;
+ if ((resp[0] & (R1_ILLEGAL_COMMAND | R1_APP_CMD)) !=
+ R1_APP_CMD)
+ return -ENODEV;
+
+ ret = mmc_cmd(MMC_ACMD_BUS_WIDTH, 0x2, resp, R1 | NCR);
+ }
+
+ /* Set block length */
+ /*
+ * ARC: useless but not dungerous for SDHC
+ */
+ ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp,
+ R1 | NCR);
+ if (ret)
+ goto out;
+
+ /*
+ * ARC: wait for card in ready state
+ */
+ do {
+ ret = mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, resp,
+ R1 | NCR);
+ } while ((ret != 0) && (resp[0] & (1 << 8)));
+
+ for (i = 0; i < blkcnt; i++, start += start_inc) {
+ /*
+ * ARC: enables and configure PDC
+ */
+ pr_debug("bread: buffer address: 0x%p\n", buffer);
+ ret = mmci_readl(MR);
+ mmci_writel(MR, (ret | MMCI_BIT(PDCMODE)));
+ mmci_writel(PTCR, (MMCI_PTCR_TXTDIS | MMCI_PTCR_RXTDIS));
+ mmci_writel(RPR, (u32) buffer);
+ mmci_writel(RCR, mmc_blkdev.blksz / 4);
+ mmci_writel(PTCR, MMCI_PTCR_RXTEN);
+
+ ret = mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK,
+ start, resp,
+ (R1 | NCR | TRCMD_START | TRDIR_READ |
+ TRTYP_BLOCK));
+ if (ret)
+ goto read_error;
+
+ do {
+ status = mmci_readl(SR);
+ } while (!(status & MMCI_BIT(RXBUFF))
+ && !(status & ERROR_FLAGS));
+ /*
+ * ARC: disable PDC
+ */
+
+ ret = mmci_readl(MR);
+ mmci_writel(MR, (ret & ~MMCI_BIT(PDCMODE)));
+
+ if (status & ERROR_FLAGS) {
+ ret = mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16,
+ resp, R1 | NCR);
+ printf("Error reading from card: 0x%08x," \
+ " status: 0x%08x\n", mmc_rca, resp[0]);
+ goto read_error;
+ }
+
+ wordcount = (mmc_blkdev.blksz / 4) - mmci_readl(RCR);
+ buffer += wordcount;
+ mmci_writel(PTCR, (MMCI_PTCR_TXTDIS | MMCI_PTCR_RXTDIS));
+
+ pr_debug("mmc: read %u words, waiting for BLKE\n",
+ wordcount);
+
+ while (!(status & MMCI_BIT(BLKE)))
+ status = mmci_readl(SR);
+ }
+
+ out:
+ /* Put the device back into Standby state */
+ mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, NCR);
+ return i;
+
+ read_error:
+ mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR);
+ printf("mmc: bread failed, rca = 0x%08x, status = 0x%08x," \
+ " card status = 0x%08x\n", mmc_rca, status, card_status);
+ goto out;
+}
+
+static void mmc_parse_cid(struct mmc_cid *cid, unsigned long *resp)
+{
+ cid->mid = resp[0] >> 24;
+ cid->oid = (resp[0] >> 8) & 0xffff;
+ cid->pnm[0] = resp[0];
+ cid->pnm[1] = resp[1] >> 24;
+ cid->pnm[2] = resp[1] >> 16;
+ cid->pnm[3] = resp[1] >> 8;
+ cid->pnm[4] = resp[1];
+ cid->pnm[5] = resp[2] >> 24;
+ cid->pnm[6] = 0;
+ cid->prv = resp[2] >> 16;
+ cid->psn = (resp[2] << 16) | (resp[3] >> 16);
+ cid->mdt = resp[3] >> 8;
+}
+
+static void sd_parse_cid(struct mmc_cid *cid, unsigned long *resp)
+{
+ cid->mid = resp[0] >> 24;
+ cid->oid = (resp[0] >> 8) & 0xffff;
+ cid->pnm[0] = resp[0];
+ cid->pnm[1] = resp[1] >> 24;
+ cid->pnm[2] = resp[1] >> 16;
+ cid->pnm[3] = resp[1] >> 8;
+ cid->pnm[4] = resp[1];
+ cid->pnm[5] = 0;
+ cid->pnm[6] = 0;
+ cid->prv = resp[2] >> 24;
+ cid->psn = (resp[2] << 8) | (resp[3] >> 24);
+ cid->mdt = (resp[3] >> 8) & 0x0fff;
+}
+
+static void mmc_dump_cid(const struct mmc_cid *cid)
+{
+ puts("----- CID -----\n");
+ printf("Manufacturer ID: %02lX\n", cid->mid);
+ printf("OEM/Application ID: %04lX\n", cid->oid);
+ printf("Product name: %s\n", cid->pnm);
+ printf("Product Revision: %lu.%lu\n",
+ cid->prv >> 4, cid->prv & 0x0f);
+ printf("Product Serial Number: %lu\n", cid->psn);
+ printf("Manufacturing Date: %02lu/%02lu\n",
+ cid->mdt >> 4, cid->mdt & 0x0f);
+ puts("----- CID -----\n");
+}
+
+static void mmc_dump_csd(const mmc_csd_t pcsd)
+{
+ printf("CSD data: %08lx %08lx %08lx %08lx\n",
+ pcsd[0], pcsd[1], pcsd[2], pcsd[3]);
+ printf("CSD structure version: %u\n",
+ 1 + SD_CSD_FIELD(VER, pcsd));
+ printf("TAAC: %u\n", SD_CSD_FIELD(TAAC, pcsd));
+ printf("NSAC: %u\n", SD_CSD_FIELD(NSAC, pcsd));
+ printf("Card command classes: %03x\n",
+ SD_CSD_FIELD(CCC, pcsd));
+ printf("Read block length: %u\n",
+ 1 << SD_CSD_FIELD(RBLEN, pcsd));
+ if (SD_CSD_FIELD(RBP, pcsd))
+ puts("Supports partial reads\n");
+ else
+ puts("Does not support partial reads\n");
+ printf("Write block length: %u\n",
+ 1 << SD_CSD_FIELD(WBL, pcsd));
+ if (SD_CSD_FIELD(WBP, pcsd))
+ puts("Supports partial writes\n");
+ else
+ puts("Does not support partial writes\n");
+ if (SD_CSD_FIELD(WPGE, pcsd))
+ printf("Supports group WP: %u\n",
+ SD_CSD_FIELD(WPGS, pcsd) + 1);
+ else
+ puts("Does not support group WP\n");
+
+ /*
+ * ARC: capacity is computed dependig on CSD version:
+ * SD cards capacity depends on read_block_len parameter
+ * and a multiplier, SDHC cadrs capacity depend on the #
+ * of blocks insted, block length is fixed to 512K
+ */
+ printf("Card capacity: %llu MB\n",
+ (unsigned long long)
+ ((SD_CSD_VER(pcsd) == 0) ?
+ (SD_CSD_1x_CSIZE(pcsd) + 1) *
+ ((1 << (SD_CSD_1x_FIELD(CSMUL, pcsd) + 2)) *
+ (1 << SD_CSD_1x_FIELD(RBLEN, pcsd))) :
+ ((unsigned long long)
+ (SD_CSD_2x_CSIZE(pcsd) + 1ULL) * 512ULL * 1024ULL))
+ / 1048576);
+
+ printf("File format: %u/%u\n",
+ SD_CSD_FIELD(FFG, pcsd), SD_CSD_FIELD(FF, pcsd));
+ puts("Write protection: ");
+ if (SD_CSD_FIELD(PWP, pcsd))
+ puts(" permanent");
+ if (SD_CSD_FIELD(TWP, pcsd))
+ puts(" temporary");
+ putc('\n');
+}
+
+static int mmc_idle_cards(void)
+{
+ int ret;
+
+ /* Reset and initialize all cards */
+ /* Send CMD0 */
+ ret = mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, NULL, 0);
+ if (ret)
+ return ret;
+
+ /* Keep the bus idle for 74 clock cycles */
+ return mmc_cmd(0, 0, NULL, INIT_CMD);
+}
+
+static int sd_init_card(struct mmc_cid *cid, block_dev_desc_t * mmc_blkdev_p,
+ int verbose) __attribute__((noinline));
+
+static int sd_init_card(struct mmc_cid *cid, block_dev_desc_t * mmc_blkdev_p,
+ int verbose)
+{
+ unsigned long resp[4];
+ int i, ret = 0;
+ u32 status;
+
+ mci_reset();
+ mmc_idle_cards();
+ if(verbose)
+ puts("mmc: Probing for SDHC ...\n");
+ /* Send supported voltage range */
+ /* SD cards 1.x do not answer to CMD8 */
+ ret = mmc_cmd(MMC_CMD_IF_COND, ((1 << 8) | 0xAA), resp, R7 | NCR);
+ if (ret == -EIO) {
+ /*
+ * ARC: No answer let's try SD 1.x
+ */
+ if(verbose)
+ puts("mmc: No answer to CMD8 trying SD\n");
+ mmc_blkdev_p->if_type = IF_TYPE_SD;
+ } else if (ret) {
+ /* Other errors or most probably 2.0 voltage mismatch */
+ puts("mmc: Unknown error on CMD8\n");
+ mmc_blkdev_p->if_type = IF_TYPE_UNKNOWN;
+ return -ENODEV;
+ } else {
+ /*
+ * ARC: probably an SDHC card
+ */
+ mmc_blkdev_p->if_type = IF_TYPE_SDHC;
+ if(verbose)
+ puts("mmc: SD 2.0 or later card found\n");
+
+ /* Check if the card supports this voltage */
+ if (resp[0] != ((1 << 8) | 0xAA)) {
+ pr_debug("mmc: Invalid voltage range\n");
+ return -ENODEV;
+ }
+ }
+
+ /*
+ * ARC: HC (30) bit set according to response to
+ * CMD8 command
+ */
+
+ pr_debug("mmc: Sending ACMD41 %s HC set\n",
+ ((mmc_blkdev_p->if_type ==
+ IF_TYPE_SDHC) ? "with" : "without"));
+
+ for (i = 1; i <= SD_MAX_RETRIES; i++) {
+ pr_debug("ACMD41 arg: 0x%08x \n",
+ CFG_MMC_OP_COND &
+ ((mmc_blkdev_p->if_type ==
+ IF_TYPE_SDHC) ? 0xffffffff : 0xbfffffff));
+ {
+ /*
+ * ARC: Some cards need this delay
+ * during voltage negotiation otherwise
+ * they report an error between two ACMD41 probes
+ * More investigation needed.
+ */
+ int volatile i =100000;
+ while(i-->0);
+ }
+
+ ret =
+ mmc_acmd(MMC_ACMD_SD_SEND_OP_COND,
+ CFG_MMC_OP_COND &
+ ((mmc_blkdev_p->if_type ==
+ IF_TYPE_SDHC) ? 0xffffffff : 0xbfffffff), resp,
+ R3 | NCR);
+ /*
+ * ARC: if no answer try again
+ */
+ if (ret == -EIO) {
+ if(verbose)
+ printf("Retrying (%d/%d) ... \n",
+ i, SD_MAX_RETRIES);
+ continue;
+ }
+ if (ret || (resp[0] & 0x80000000))
+ break;
+ ret = -ETIMEDOUT;
+ }
+
+ /*
+ * ARC: Card did not answer to ACMD41
+ * so it's a MMC card
+ */
+ if (ret) {
+ mmc_blkdev.if_type = IF_TYPE_MMC;
+ puts("No answer to ACMD41 trying mmc card\n");
+ return ret;
+ }
+
+ /*
+ * ARC: check for HC bit, if its not set
+ * sd card is SD
+ */
+ if ((resp[0] & 0xc0000000) == 0x80000000) {
+ mmc_blkdev.if_type = IF_TYPE_SD;
+ }
+
+ ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, R2 | NID);
+ if (ret)
+ return ret;
+ sd_parse_cid(cid, resp);
+ if (verbose)
+ mmc_dump_cid(cid);
+
+ /* Get RCA of the card that responded */
+ ret = mmc_cmd(MMC_CMD_SD_SEND_RELATIVE_ADDR, 0, resp, R6 | NCR);
+ if (ret)
+ return ret;
+
+ mmc_rca = resp[0] >> 16;
+ if (verbose)
+ printf("SD Card detected RCA: 0x%x type: %s\n",
+ mmc_rca,
+ ((mmc_blkdev.if_type ==
+ IF_TYPE_SDHC) ? "SDHC" : ((mmc_blkdev.if_type ==
+ IF_TYPE_SD) ? "SD" :
+ "MMC")));
+
+ mmc_card_is_sd = 1;
+ return 0;
+}
+
+static int mmc_init_card(struct mmc_cid *cid, int verbose)
+{
+ unsigned long resp[4];
+ int i, ret = 0;
+
+ mmc_idle_cards();
+ for (i = 0; i < 1000; i++) {
+ ret = mmc_cmd(MMC_CMD_SEND_OP_COND, CFG_MMC_OP_COND, resp,
+ R3 | NID | OPEN_DRAIN);
+ if (ret || (resp[0] & 0x80000000))
+ break;
+ ret = -ETIMEDOUT;
+ }
+
+ if (ret)
+ return ret;
+
+ /* Get CID of all cards. FIXME: Support more than one card */
+ ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, R2 | NID | OPEN_DRAIN);
+ if (ret)
+ return ret;
+ mmc_parse_cid(cid, resp);
+ if (verbose)
+ mmc_dump_cid(cid);
+
+ /* Set Relative Address of the card that responded */
+ ret = mmc_cmd(MMC_CMD_SET_RELATIVE_ADDR, mmc_rca << 16, resp,
+ R1 | NCR | OPEN_DRAIN);
+ return ret;
+}
+
+static void mci_set_data_timeout(mmc_csd_t * pu_csd)
+{
+ static const unsigned int dtomul_to_shift[] = {
+ 0, 4, 7, 8, 10, 12, 16, 20,
+ };
+ static const unsigned int taac_exp[] = {
+ 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000,
+ };
+ static const unsigned int taac_mant[] = {
+ 0, 10, 12, 13, 15, 60, 25, 30,
+ 35, 40, 45, 50, 55, 60, 70, 80,
+ };
+ unsigned int timeout_ns, timeout_clks;
+ unsigned int e, m;
+ unsigned int dtocyc, dtomul;
+ unsigned int shift;
+ u32 dtor;
+
+ unsigned long sys_freq = 0;
+
+ sys_get_freq(AT91_MASTER_FREQ, &sys_freq);
+ pr_debug("mmc: sys_frequency: %lu\n", sys_freq);
+
+ if ((mmc_blkdev.if_type == IF_TYPE_SD) ||
+ (mmc_blkdev.if_type == IF_TYPE_SDHC)) {
+ /* SDHC cards maximum timeout is 100ms
+ * 100ms = dtocyc * mci_cycle_period s =>
+ * 0.1s = dtocyc * (sys_freq/(2*(clkdiv+1)))^-1 s =>
+ * dtocyc = 0.1*(sys_freq/(2*(clkdiv+1))) =>
+ * dtocyc = sys_freq/(20*(clkdiv+1))
+ */
+ unsigned long clkdiv = mmci_readl(MR);
+
+ clkdiv = MMCI_BF(CLKDIV, clkdiv);
+ timeout_clks = sys_freq / (20 * (clkdiv + 1));
+ pr_debug("mmc: timeout cycles %lu\n", timeout_clks);
+ } else {
+ e = MMC_CSD_FIELD(TAAC, pu_csd) & 0x07;
+ m = (MMC_CSD_FIELD(TAAC, pu_csd) >> 3) & 0x0f;
+
+ timeout_ns = (taac_exp[e] * taac_mant[m] + 9) / 10;
+ timeout_clks = MMC_CSD_FIELD(NSAC, pu_csd) * 100;
+
+ timeout_clks += (((timeout_ns + 9) / 10)
+ * ((CFG_MMC_CLK_PP + 99999) / 100000) +
+ 9999) / 10000;
+ if (!mmc_card_is_sd)
+ timeout_clks *= 10;
+ else
+ timeout_clks *= 100;
+ }
+
+ dtocyc = timeout_clks;
+
+ dtomul = 0;
+ while (dtocyc > 15 && dtomul < 8) {
+ dtomul++;
+ shift = dtomul_to_shift[dtomul];
+ dtocyc = (timeout_clks + (1 << shift) - 1) >> shift;
+ }
+
+ if (dtomul >= 8) {
+ dtomul = 7;
+ dtocyc = 15;
+ puts("Warning: Using maximum data timeout\n");
+ }
+
+ dtor = (MMCI_BF(DTOMUL, dtomul)
+ | MMCI_BF(DTOCYC, dtocyc + 1));
+ mmci_writel(DTOR, dtor);
+
+ pr_debug("mmc: Using %u cycles data timeout (DTOR=0x%x)\n",
+ dtocyc << shift, dtor);
+}
+
+int mmc_init(int verbose)
+{
+ struct mmc_cid cid;
+ mmc_csd_t u_csd;
+ unsigned int max_blksz;
+ int ret;
+
+ /* Initialize controller */
+ mmci_writel(CR, MMCI_BIT(SWRST));
+ mmci_writel(CR, MMCI_BIT(MCIEN));
+ mmci_writel(DTOR, 0x5f);
+ mmci_writel(IDR, ~0UL);
+ mci_set_mode(CFG_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
+
+ mmc_card_is_sd = 0;
+ mmc_blkdev.if_type = IF_TYPE_UNKNOWN;
+
+ ret = sd_init_card(&cid, &mmc_blkdev, verbose);
+
+ /* No SD card so try MMC */
+ if (ret) {
+ mmc_rca = MMC_DEFAULT_RCA;
+ ret = mmc_init_card(&cid, verbose);
+ }
+ /* No MMC card so abort */
+ if (ret)
+ return ret;
+
+ /* Get CSD from the card */
+ ret = mmc_cmd(MMC_CMD_SEND_CSD, mmc_rca << 16, &u_csd, R2 | NCR);
+ if (ret)
+ return ret;
+ if (verbose)
+ mmc_dump_csd((void *)&u_csd);
+
+ /*
+ * ARC: If the card type is not MMC then
+ * check for SD CSD version:
+ * 0 => SD
+ * !0 => SDHC
+ */
+ /*
+ if(mmc_blkdev.if_type != IF_TYPE_MMC)
+ if(SD_CSD_FIELD(VER,&u_csd) == 0)
+ mmc_blkdev.if_type = IF_TYPE_SD;
+ else
+ mmc_blkdev.if_type = IF_TYPE_SDHC;
+ */
+
+ mci_set_data_timeout(&u_csd);
+
+ /* Initialize the blockdev structure */
+ if (mmc_blkdev.if_type == IF_TYPE_UNKNOWN)
+ mmc_blkdev.if_type = IF_TYPE_MMC;
+
+ mmc_blkdev.part_type = PART_TYPE_DOS;
+ mmc_blkdev.block_read = mmc_bread;
+ sprintf((char *)mmc_blkdev.vendor,
+ "Man %02x%04x Snr %08x", cid.mid, cid.oid, cid.psn);
+ strncpy((char *)mmc_blkdev.product, cid.pnm,
+ sizeof(mmc_blkdev.product));
+ sprintf((char *)mmc_blkdev.revision, "%x %x",
+ cid.prv >> 4, cid.prv & 0x0f);
+
+ /*
+ * If we can't use 512 byte blocks, refuse to deal with the
+ * card. Tons of code elsewhere seems to depend on this.
+ */
+ max_blksz = 1 << MMC_CSD_FIELD(RBLEN, &u_csd);
+ if ((mmc_blkdev.if_type == IF_TYPE_MMC) &
+ ((max_blksz < 512)
+ || ((max_blksz > 512) && !MMC_CSD_FIELD(RBP, &u_csd)))
+ ) {
+ printf("Card does not support 512 byte reads, aborting.\n");
+ return -ENODEV;
+ }
+ mmc_blkdev.blksz = 512;
+ if (MMC_CSD_VER(&u_csd) == 0)
+ /* CSD ver 1.x */
+ mmc_blkdev.lba =
+ (MMC_CSD_FIELD(CSIZE, &u_csd) +
+ 1) * (1 << (MMC_CSD_FIELD(CSMUL, &u_csd) + 2));
+ else
+ /* CSD ver 2.0 */
+ mmc_blkdev.lba =
+ (SD_CSD_FIELD(CSIZE, &u_csd) + 1) * (512 * 1024);
+
+ mci_set_mode(CFG_MMC_CLK_PP, mmc_blkdev.blksz);
+
+ init_part(&mmc_blkdev);
+ if (fat_register_device(&mmc_blkdev, 1))
+ printf("Could not register MMC fat device\n");
+ if(verbose)
+ print_part_dos(&mmc_blkdev);
+ return 0;
+}
+
+int mmc_read(ulong src, uchar * dst, int size)
+{
+ return -ENOSYS;
+}
+
+int mmc_write(uchar * src, ulong dst, int size)
+{
+ return -ENOSYS;
+}
+
+int mmc2info(ulong addr)
+{
+ return 0;
+}
+
+#endif /* CONFIG_MMC */
diff --git a/include/asm-arm/arch-at572d940hf/atmel_mci.h b/include/asm-arm/arch-at572d940hf/atmel_mci.h
new file mode 100644
index 0000000..ddf611c
--- /dev/null
+++ b/include/asm-arm/arch-at572d940hf/atmel_mci.h
@@ -0,0 +1,227 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * Antonio R. Costa <antonio.costa <at> atmel.com>
+ * <costa.antonior <at> gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef __CPU_AT32AP_ATMEL_MCI_H__
+#define __CPU_AT32AP_ATMEL_MCI_H__
+
+/* Atmel MultiMedia Card Interface (MCI) registers */
+#define MMCI_CR 0x0000
+#define MMCI_MR 0x0004
+#define MMCI_DTOR 0x0008
+#define MMCI_SDCR 0x000c
+#define MMCI_ARGR 0x0010
+#define MMCI_CMDR 0x0014
+#define MMCI_RSPR 0x0020
+#define MMCI_RSPR1 0x0024
+#define MMCI_RSPR2 0x0028
+#define MMCI_RSPR3 0x002c
+#define MMCI_RDR 0x0030
+#define MMCI_TDR 0x0034
+#define MMCI_SR 0x0040
+#define MMCI_IER 0x0044
+#define MMCI_IDR 0x0048
+#define MMCI_IMR 0x004c
+
+#define MMCI_RPR 0x100
+#define MMCI_RCR 0x104
+#define MMCI_TPR 0x108
+#define MMCI_TCR 0x10C
+#define MMCI_RNPR 0x110
+#define MMCI_RNCR 0x114
+#define MMCI_TNPR 0x118
+#define MMCI_TNCR 0x11C
+#define MMCI_PTCR 0x120
+#define MMCI_PTSR 0x124
+
+#define MMCI_PTCR_RXTEN 0x1
+#define MMCI_PTCR_RXTDIS 0x2
+#define MMCI_PTCR_TXTEN 0x100
+#define MMCI_PTCR_TXTDIS 0x200
+
+
+
+
+/* Bitfields in CR */
+#define MMCI_MCIEN_OFFSET 0
+#define MMCI_MCIEN_SIZE 1
+#define MMCI_MCIDIS_OFFSET 1
+#define MMCI_MCIDIS_SIZE 1
+#define MMCI_PWSEN_OFFSET 2
+#define MMCI_PWSEN_SIZE 1
+#define MMCI_PWSDIS_OFFSET 3
+#define MMCI_PWSDIS_SIZE 1
+#define MMCI_SWRST_OFFSET 7
+#define MMCI_SWRST_SIZE 1
+
+/* Bitfields in MR */
+#define MMCI_CLKDIV_OFFSET 0
+#define MMCI_CLKDIV_SIZE 8
+#define MMCI_PWSDIV_OFFSET 8
+#define MMCI_PWSDIV_SIZE 3
+#define MMCI_RDPROOF_OFFSET 11
+#define MMCI_RDPROOF_SIZE 1
+#define MMCI_WRPROOF_OFFSET 12
+#define MMCI_WRPROOF_SIZE 1
+#define MMCI_PDCPADV_OFFSET 14
+#define MMCI_PDCPADV_SIZE 1
+#define MMCI_PDCMODE_OFFSET 15
+#define MMCI_PDCMODE_SIZE 1
+#define MMCI_BLKLEN_OFFSET 16
+#define MMCI_BLKLEN_SIZE 16
+
+/* Bitfields in DTOR */
+#define MMCI_DTOCYC_OFFSET 0
+#define MMCI_DTOCYC_SIZE 4
+#define MMCI_DTOMUL_OFFSET 4
+#define MMCI_DTOMUL_SIZE 3
+
+/* Bitfields in SDCR */
+#define MMCI_SCDSEL_OFFSET 0
+#define MMCI_SCDSEL_SIZE 4
+#define MMCI_SCDBUS_OFFSET 7
+#define MMCI_SCDBUS_SIZE 1
+
+/* Bitfields in ARGR */
+#define MMCI_ARG_OFFSET 0
+#define MMCI_ARG_SIZE 32
+
+/* Bitfields in CMDR */
+#define MMCI_CMDNB_OFFSET 0
+#define MMCI_CMDNB_SIZE 6
+#define MMCI_RSPTYP_OFFSET 6
+#define MMCI_RSPTYP_SIZE 2
+#define MMCI_SPCMD_OFFSET 8
+#define MMCI_SPCMD_SIZE 3
+#define MMCI_OPDCMD_OFFSET 11
+#define MMCI_OPDCMD_SIZE 1
+#define MMCI_MAXLAT_OFFSET 12
+#define MMCI_MAXLAT_SIZE 1
+#define MMCI_TRCMD_OFFSET 16
+#define MMCI_TRCMD_SIZE 2
+#define MMCI_TRDIR_OFFSET 18
+#define MMCI_TRDIR_SIZE 1
+#define MMCI_TRTYP_OFFSET 19
+#define MMCI_TRTYP_SIZE 2
+
+/* Bitfields in RSPRx */
+#define MMCI_RSP_OFFSET 0
+#define MMCI_RSP_SIZE 32
+
+/* Bitfields in SR/IER/IDR/IMR */
+#define MMCI_CMDRDY_OFFSET 0
+#define MMCI_CMDRDY_SIZE 1
+#define MMCI_RXRDY_OFFSET 1
+#define MMCI_RXRDY_SIZE 1
+#define MMCI_TXRDY_OFFSET 2
+#define MMCI_TXRDY_SIZE 1
+#define MMCI_BLKE_OFFSET 3
+#define MMCI_BLKE_SIZE 1
+#define MMCI_DTIP_OFFSET 4
+#define MMCI_DTIP_SIZE 1
+#define MMCI_NOTBUSY_OFFSET 5
+#define MMCI_NOTBUSY_SIZE 1
+#define MMCI_ENDRX_OFFSET 6
+#define MMCI_ENDRX_SIZE 1
+#define MMCI_ENDTX_OFFSET 7
+#define MMCI_ENDTX_SIZE 1
+#define MMCI_RXBUFF_OFFSET 14
+#define MMCI_RXBUFF_SIZE 1
+#define MMCI_TXBUFE_OFFSET 15
+#define MMCI_TXBUFE_SIZE 1
+#define MMCI_RINDE_OFFSET 16
+#define MMCI_RINDE_SIZE 1
+#define MMCI_RDIRE_OFFSET 17
+#define MMCI_RDIRE_SIZE 1
+#define MMCI_RCRCE_OFFSET 18
+#define MMCI_RCRCE_SIZE 1
+#define MMCI_RENDE_OFFSET 19
+#define MMCI_RENDE_SIZE 1
+#define MMCI_RTOE_OFFSET 20
+#define MMCI_RTOE_SIZE 1
+#define MMCI_DCRCE_OFFSET 21
+#define MMCI_DCRCE_SIZE 1
+#define MMCI_DTOE_OFFSET 22
+#define MMCI_DTOE_SIZE 1
+#define MMCI_OVRE_OFFSET 30
+#define MMCI_OVRE_SIZE 1
+#define MMCI_UNRE_OFFSET 31
+#define MMCI_UNRE_SIZE 1
+
+/* Constants for DTOMUL */
+#define MMCI_DTOMUL_1_CYCLE 0
+#define MMCI_DTOMUL_16_CYCLES 1
+#define MMCI_DTOMUL_128_CYCLES 2
+#define MMCI_DTOMUL_256_CYCLES 3
+#define MMCI_DTOMUL_1024_CYCLES 4
+#define MMCI_DTOMUL_4096_CYCLES 5
+#define MMCI_DTOMUL_65536_CYCLES 6
+#define MMCI_DTOMUL_1048576_CYCLES 7
+
+/* Constants for RSPTYP */
+#define MMCI_RSPTYP_NO_RESP 0
+#define MMCI_RSPTYP_48_BIT_RESP 1
+#define MMCI_RSPTYP_136_BIT_RESP 2
+
+/* Constants for SPCMD */
+#define MMCI_SPCMD_NO_SPEC_CMD 0
+#define MMCI_SPCMD_INIT_CMD 1
+#define MMCI_SPCMD_SYNC_CMD 2
+#define MMCI_SPCMD_INT_CMD 4
+#define MMCI_SPCMD_INT_RESP 5
+
+/* Constants for TRCMD */
+#define MMCI_TRCMD_NO_TRANS 0
+#define MMCI_TRCMD_START_TRANS 1
+#define MMCI_TRCMD_STOP_TRANS 2
+
+/* Constants for TRTYP */
+#define MMCI_TRTYP_BLOCK 0
+#define MMCI_TRTYP_MULTI_BLOCK 1
+#define MMCI_TRTYP_STREAM 2
+
+/* Bit manipulation macros */
+#define MMCI_BIT(name) \
+ (1 << MMCI_##name##_OFFSET)
+#define MMCI_BF(name,value) \
+ (((value) & ((1 << MMCI_##name##_SIZE) - 1)) \
+ << MMCI_##name##_OFFSET)
+#define MMCI_BFEXT(name,value) \
+ (((value) >> MMCI_##name##_OFFSET)\
+ & ((1 << MMCI_##name##_SIZE) - 1))
+#define MMCI_BFINS(name,value,old) \
+ (((old) & ~(((1 << MMCI_##name##_SIZE) - 1) \
+ << MMCI_##name##_OFFSET)) \
+ | MMCI_BF(name,value))
+
+/* Register access macros */
+#define mmci_readl(reg) \
+ readl((volatile void *)MMCI_BASE + MMCI_##reg)
+#define mmci_writel(reg,value) \
+ writel((value), (volatile void *)MMCI_BASE + MMCI_##reg)
+
+#define SD_MAX_RETRIES 50
+
+#endif /* __CPU_AT32AP_ATMEL_MCI_H__ */
diff --git a/include/asm-arm/arch-at572d940hf/mmc.h b/include/asm-arm/arch-at572d940hf/mmc.h
new file mode 100644
index 0000000..46e0028
--- /dev/null
+++ b/include/asm-arm/arch-at572d940hf/mmc.h
@@ -0,0 +1,354 @@
+/*
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * Antonio R. Costa <antonio.costa <at> atmel.com>
+ * <costa.antonior <at> gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_AT572D940_MMC_H
+#define __ASM_AT572D940_MMC_H
+
+struct mmc_cid {
+ unsigned long psn;
+ unsigned short oid;
+ unsigned char mid;
+ unsigned char prv;
+ unsigned char mdt;
+ char pnm[7];
+};
+
+/*
+ * Bitfileds are ugly and not portable,
+ * So lets redefine the CSD
+ */
+
+typedef unsigned long mmc_csd_t[4];
+typedef unsigned long sd_csd_t[4];
+
+/*
+ * CSD ver: 2.0 manipulation macros
+ */
+
+/*
+ * Masks
+ */
+
+#define CSD_2x_VER_MASK 0x3
+#define CSD_2x_RSVD1_MASK 0x3f
+#define CSD_2x_TAAC_MASK 0xff
+#define CSD_2x_NSAC_MASK 0xff
+#define CSD_2x_TRANSPEED_MASK 0xff
+
+#define CSD_2x_CCC_MASK 0xfff
+#define CSD_2x_RBLEN_MASK 0xff
+#define CSD_2x_RBP_MASK 0x1
+#define CSD_2x_WBM_MASK 0x1
+#define CSD_2x_RBM_MASK 0x1
+#define CSD_2x_DSRIMP_MASK 0x1
+#define CSD_2x_RSVD2_MASK 0x3f
+#define CSD_2x_CSIZE_H_MASK 0x3f
+
+#define CSD_2x_CSIZE_MASK 0xffff
+#define CSD_2x_RSVD3_MASK 0x1
+#define CSD_2x_ERBL_MASK 0x1
+#define CSD_2x_SECSIZE_MASK 0x7f
+#define CSD_2x_WPGS_MASK 0x7f
+
+#define CSD_2x_WPGE_MASK 0x1
+#define CSD_2x_RSVD4_MASK 0x3
+#define CSD_2x_R2WF_MASK 0x7
+#define CSD_2x_WBL_MASK 0xf
+#define CSD_2x_WBP_MASK 0x1
+#define CSD_2x_RSVD5_MASK 0x1f
+#define CSD_2x_FFG_MASK 0x1
+#define CSD_2x_COPY_MASK 0x1
+#define CSD_2x_PWP_MASK 0x1
+#define CSD_2x_TWP_MASK 0x1
+#define CSD_2x_FF_MASK 0x3
+#define CSD_2x_RSVD6_MASK 0x3
+#define CSD_2x_CRC_MASK 0x7f
+#define CSD_2x_ONE_MASK 0x1
+
+/*
+ * Offsets inside the single word
+ */
+
+#define CSD_2x_VER_OFF 30
+#define CSD_2x_RSVD1_OFF 24
+#define CSD_2x_TAAC_OFF 16
+#define CSD_2x_NSAC_OFF 8
+#define CSD_2x_TRANSPEED_OFF 0
+
+#define CSD_2x_CCC_OFF 20
+#define CSD_2x_RBLEN_OFF 16
+#define CSD_2x_RBP_OFF 15
+#define CSD_2x_WBM_OFF 14
+#define CSD_2x_RBM_OFF 13
+#define CSD_2x_DSRIMP_OFF 12
+#define CSD_2x_RSVD2_OFF 6
+#define CSD_2x_CSIZE_H_OFF 0
+
+#define CSD_2x_CSIZE_OFF 16
+#define CSD_2x_RSVD3_OFF 15
+#define CSD_2x_ERBL_OFF 14
+#define CSD_2x_SECSIZE_OFF 7
+#define CSD_2x_WPGS_OFF 0
+
+#define CSD_2x_WPGE_OFF 31
+#define CSD_2x_RSVD4_OFF 29
+#define CSD_2x_R2WF_OFF 26
+#define CSD_2x_WBL_OFF 22
+#define CSD_2x_WBP_OFF 21
+#define CSD_2x_RSVD5_OFF 16
+#define CSD_2x_FFG_OFF 15
+#define CSD_2x_COPY_OFF 14
+#define CSD_2x_PWP_OFF 13
+#define CSD_2x_TWP_OFF 12
+#define CSD_2x_FF_OFF 10
+#define CSD_2x_RSVD6_OFF 8
+#define CSD_2x_CRC_OFF 1
+#define CSD_2x_ONE_OFF 0
+
+/*
+ * Word in which the field is placed
+ */
+
+#define CSD_2x_VER_W 0
+#define CSD_2x_RSVD1_W 0
+#define CSD_2x_TAAC_W 0
+#define CSD_2x_NSAC_W 0
+#define CSD_2x_TRANSPEED_W 0
+
+#define CSD_2x_CCC_W 1
+#define CSD_2x_RBLEN_W 1
+#define CSD_2x_RBP_W 1
+#define CSD_2x_WBM_W 1
+#define CSD_2x_RBM_W 1
+#define CSD_2x_DSRIMP_W 1
+#define CSD_2x_RSVD2_W 1
+#define CSD_2x_CSIZE_H_W 1
+
+#define CSD_2x_CSIZE_W 2
+#define CSD_2x_RSVD3_W 2
+#define CSD_2x_ERBL_W 2
+#define CSD_2x_SECSIZE_W 2
+#define CSD_2x_WPGS_W 2
+
+#define CSD_2x_WPGE_W 3
+#define CSD_2x_RSVD4_W 3
+#define CSD_2x_R2WF_W 3
+#define CSD_2x_WBL_W 3
+#define CSD_2x_WBP_W 3
+#define CSD_2x_RSVD5_W 3
+#define CSD_2x_FFG_W 3
+#define CSD_2x_COPY_W 3
+#define CSD_2x_PWP_W 3
+#define CSD_2x_TWP_W 3
+#define CSD_2x_FF_W 3
+#define CSD_2x_RSVD6_W 3
+#define CSD_2x_CRC_W 3
+#define CSD_2x_ONE_W 3
+
+/*
+ * ARC:
+ * Please note that CSIZE field crosses the word boundary,
+ * anyway since SD spec 2.0 states that the highest 6 bits
+ * shall be set to 0s the following macro still works
+ */
+
+#define SD_CSD_2x_CSIZE(pcsd) \
+ (((unsigned long long) SD_CSD_2x_FIELD(CSIZE,pcsd)) | \
+ (((unsigned long long) SD_CSD_2x_FIELD(CSIZE_H,pcsd)) << 16))
+
+#define SD_CSD_2x_FIELD(name,pcsd) \
+ ((((unsigned long *)pcsd)[CSD_2x_## name ##_W] >> \
+ CSD_2x_## name ##_OFF) & CSD_2x_## name ##_MASK)
+
+#define CSD_1x_VER_MASK 0x3
+#define CSD_1x_RSVD1_MASK 0x3f
+#define CSD_1x_TAAC_MASK 0xff
+#define CSD_1x_NSAC_MASK 0xff
+#define CSD_1x_TRANSPEED_MASK 0xff
+
+#define CSD_1x_CCC_MASK 0xfff
+#define CSD_1x_RBLEN_MASK 0xf
+#define CSD_1x_RBP_MASK 0x1
+#define CSD_1x_WBM_MASK 0x1
+#define CSD_1x_RBM_MASK 0x1
+#define CSD_1x_DSRIMP_MASK 0x1
+#define CSD_1x_RSVD2_MASK 0x3
+#define CSD_1x_CSIZE_H_MASK 0x3ff
+
+#define CSD_1x_CSIZE_MASK 0x3
+#define CSD_1x_RCMIN_MASK 0x7
+#define CSD_1x_RCMAX_MASK 0x7
+#define CSD_1x_WCMIN_MASK 0x7
+#define CSD_1x_WCMAX_MASK 0x7
+#define CSD_1x_CSMUL_MASK 0x7
+#define CSD_1x_ESBE_MASK 0x1
+#define CSD_1x_SEC_SIZE_MASK 0x7ff
+
+#define CSD_1x_WPGS_MASK 0x7ff
+#define CSD_1x_WPGE_MASK 0x1
+#define CSD_1x_RSVD4_MASK 0x3
+#define CSD_1x_R2WF_MASK 0x7
+#define CSD_1x_WBL_MASK 0xf
+#define CSD_1x_WBP_MASK 0x1
+#define CSD_1x_RSVD5_MASK 0x1f
+#define CSD_1x_FFG_MASK 0x1
+#define CSD_1x_COPY_MASK 0x1
+#define CSD_1x_PWP_MASK 0x1
+#define CSD_1x_TWP_MASK 0x1
+#define CSD_1x_FF_MASK 0x3
+#define CSD_1x_RSVD6_MASK 0x3
+#define CSD_1x_CRC_MASK 0x7f
+#define CSD_1x_ONE_MASK 0x1
+
+/*
+ * Offsets inside the single word
+ */
+
+#define CSD_1x_VER_OFF 30
+#define CSD_1x_RSVD1_OFF 24
+#define CSD_1x_TAAC_OFF 16
+#define CSD_1x_NSAC_OFF 8
+#define CSD_1x_TRANSPEED_OFF 0
+
+#define CSD_1x_CCC_OFF 20
+#define CSD_1x_RBLEN_OFF 16
+#define CSD_1x_RBP_OFF 15
+#define CSD_1x_WBM_OFF 14
+#define CSD_1x_RBM_OFF 13
+#define CSD_1x_DSRIMP_OFF 12
+#define CSD_1x_RSVD2_OFF 10
+#define CSD_1x_CSIZE_H_OFF 0
+
+#define CSD_1x_CSIZE_OFF 30
+#define CSD_1x_RCMIN_OFF 27
+#define CSD_1x_RCMAX_OFF 24
+#define CSD_1x_WCMIN_OFF 21
+#define CSD_1x_WCMAX_OFF 18
+#define CSD_1x_CSMUL_OFF 15
+#define CSD_1x_ERBL_OFF 14
+#define CSD_1x_SECSIZE_OFF 7
+#define CSD_1x_WPGS_OFF 0
+
+#define CSD_1x_WPGE_OFF 31
+#define CSD_1x_RSVD4_OFF 29
+#define CSD_1x_R2WF_OFF 26
+#define CSD_1x_WBL_OFF 22
+#define CSD_1x_WBP_OFF 21
+#define CSD_1x_RSVD5_OFF 16
+#define CSD_1x_FFG_OFF 15
+#define CSD_1x_COPY_OFF 14
+#define CSD_1x_PWP_OFF 13
+#define CSD_1x_TWP_OFF 12
+#define CSD_1x_FF_OFF 10
+#define CSD_1x_RSVD6_OFF 8
+#define CSD_1x_CRC_OFF 1
+#define CSD_1x_ONE_OFF 0
+
+/*
+ * Word in which the field is placed
+ */
+
+#define CSD_1x_VER_W 0
+#define CSD_1x_RSVD1_W 0
+#define CSD_1x_TAAC_W 0
+#define CSD_1x_NSAC_W 0
+#define CSD_1x_TRANSPEED_W 0
+
+#define CSD_1x_CCC_W 1
+#define CSD_1x_RBLEN_W 1
+#define CSD_1x_RBP_W 1
+#define CSD_1x_WBM_W 1
+#define CSD_1x_RBM_W 1
+#define CSD_1x_DSRIMP_W 1
+#define CSD_1x_RSVD2_W 1
+#define CSD_1x_CSIZE_H_W 1
+
+#define CSD_1x_CSIZE_W 2
+#define CSD_1x_RCMIN_W 2
+#define CSD_1x_RCMAX_W 2
+#define CSD_1x_WCMIN_W 2
+#define CSD_1x_WCMAX_W 2
+#define CSD_1x_CSMUL_W 2
+#define CSD_1x_ERBL_W 2
+#define CSD_1x_SECSIZE_W 2
+#define CSD_1x_WPGS_W 2
+
+#define CSD_1x_WPGE_W 3
+#define CSD_1x_RSVD4_W 3
+#define CSD_1x_R2WF_W 3
+#define CSD_1x_WBL_W 3
+#define CSD_1x_WBP_W 3
+#define CSD_1x_RSVD5_W 3
+#define CSD_1x_FFG_W 3
+#define CSD_1x_COPY_W 3
+#define CSD_1x_PWP_W 3
+#define CSD_1x_TWP_W 3
+#define CSD_1x_FF_W 3
+#define CSD_1x_RSVD6_W 3
+#define CSD_1x_CRC_W 3
+#define CSD_1x_ONE_W 3
+
+#define SD_CSD_1x_FIELD(name,pcsd) \
+ ((((unsigned long *)pcsd)[CSD_1x_## name ##_W] >> \
+ CSD_1x_## name ##_OFF) & CSD_1x_## name ##_MASK)
+
+#define SD_CSD_FIELD(name,pcsd) \
+ ((SD_CSD_1x_FIELD(VER,pcsd) == 0x0) ? \
+ SD_CSD_1x_FIELD(name,pcsd) : SD_CSD_2x_FIELD(name,pcsd))
+
+#define SD_CSD_1x_CSIZE(pcsd) \
+ (SD_CSD_1x_FIELD(CSIZE,pcsd)+(SD_CSD_1x_FIELD(CSIZE_H,pcsd) << 2))
+
+#define SD_CSD_VER(pcsd) \
+ (SD_CSD_1x_FIELD(VER,pcsd))
+
+#define MMC_CSD_VER(pcsd) SD_CSD_VER(pcsd)
+#define MMC_CSD_FIELD(name,pcsd) SD_CSD_1x_FIELD(name,pcsd)
+
+/* MMC Command numbers */
+#define MMC_CMD_GO_IDLE_STATE 0
+#define MMC_CMD_SEND_OP_COND 1
+#define MMC_CMD_ALL_SEND_CID 2
+#define MMC_CMD_SET_RELATIVE_ADDR 3
+#define MMC_CMD_SD_SEND_RELATIVE_ADDR 3
+#define MMC_CMD_SET_DSR 4
+#define MMC_CMD_SELECT_CARD 7
+#define MMC_CMD_IF_COND 8
+#define MMC_CMD_SEND_CSD 9
+#define MMC_CMD_SEND_CID 10
+#define MMC_CMD_SEND_STATUS 13
+#define MMC_CMD_SET_BLOCKLEN 16
+#define MMC_CMD_READ_SINGLE_BLOCK 17
+#define MMC_CMD_READ_MULTIPLE_BLOCK 18
+#define MMC_CMD_WRITE_BLOCK 24
+#define MMC_CMD_APP_CMD 55
+
+#define MMC_ACMD_BUS_WIDTH 6
+#define MMC_ACMD_SD_SEND_OP_COND 41
+
+#define R1_ILLEGAL_COMMAND (1 << 22)
+#define R1_APP_CMD (1 << 5)
+
+#endif /* __ASM_AT572D940_MMC_H */
--
1.5.4.3
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [U-Boot-Users] [PATCH 2/2] AT572D940HF-EB Support v2 (SDHC support part 2)
2008-06-12 14:14 ` [U-Boot-Users] [PATCH 1/2] AT572D940HF-EB Support v2 (SDHC support part 1) Antonio R. Costa
@ 2008-06-12 14:14 ` Antonio R. Costa
2008-06-12 14:14 ` [U-Boot-Users] [PATCH 3/6] AT572D940HF-EB Support v2 (include files part 1) Antonio R. Costa
2008-06-12 16:36 ` [U-Boot-Users] [PATCH 1/2] AT572D940HF-EB Support v2 (SDHC support part 1) Haavard Skinnemoen
1 sibling, 1 reply; 26+ messages in thread
From: Antonio R. Costa @ 2008-06-12 14:14 UTC (permalink / raw)
To: u-boot
Introduced IF_TYPE_SDHC to distinguish between SD and SDHC.
Maybe this is not the best method since struct block_dev_descr.priv
could point to a structure describing card properties but it was
the quickest one and I had no time to spend.
Signed-off-by: Antonio R. Costa <antonio.costa@atmel.com>
diff --git a/include/part.h b/include/part.h
index b22a637..1bf4a24 100644
--- a/include/part.h
+++ b/include/part.h
@@ -62,6 +62,7 @@ typedef struct block_dev_desc {
#define IF_TYPE_MMC 6
#define IF_TYPE_SD 7
#define IF_TYPE_SATA 8
+#define IF_TYPE_SDHC 9
/* Part types */
#define PART_TYPE_UNKNOWN 0x00
--
1.5.4.3
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [U-Boot-Users] [PATCH 3/6] AT572D940HF-EB Support v2 (include files part 1)
2008-06-12 14:14 ` [U-Boot-Users] [PATCH 2/2] AT572D940HF-EB Support v2 (SDHC support part 2) Antonio R. Costa
@ 2008-06-12 14:14 ` Antonio R. Costa
2008-06-12 14:14 ` [U-Boot-Users] [PATCH 4/6] AT572D940HF-EB Support v2 (include files part 2) Antonio R. Costa
0 siblings, 1 reply; 26+ messages in thread
From: Antonio R. Costa @ 2008-06-12 14:14 UTC (permalink / raw)
To: u-boot
Signed-off-by: Antonio R. Costa <antonio.costa@atmel.com>
diff --git a/include/asm-arm/arch-at572d940hf/at91_aic.h b/include/asm-arm/arch-at572d940hf/at91_aic.h
new file mode 100644
index 0000000..ba0da8c
--- /dev/null
+++ b/include/asm-arm/arch-at572d940hf/at91_aic.h
@@ -0,0 +1,44 @@
+/*
+ * include/asm-arm/arch-at572d940/at91_aic.h
+ *
+ * Copyright (C) 2008 Antonio R. Costa
+ * Copyright (C) ATMEL
+ *
+ * Advanced Interrupt Controller (AIC).
+ * Based on AT572D940 datasheet.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#define AIC_BASE 0xfffff000
+
+#define AIC_SMR0 0x0
+#define AIC_SVR0 0x80
+#define AIC_IVR 0x100
+#define AIC_FIQ 0x104
+#define AIC_ISR 0x108
+#define AIC_IPR 0x10c
+#define AIC_IMR 0x110
+#define AIC_ICR 0x114
+#define AIC_IECR 0x120
+#define AIC_IDCR 0x124
+#define AIC_ICCR 0x128
+#define AIC_ISCR 0x12c
+#define AIC_EOICR 0x130
+#define AIC_SPU 0x134
+
+#define AIC_SMR(n) \
+ ((unsigned long) (((unsigned long*) AIC_SMR0) + (n)))
+#define AIC_SVR(n) \
+ ((unsigned long) (((unsigned long*) AIC_SVR0) + (n)))
+
+#define AIC_WRITE(reg,value) \
+ (*((volatile unsigned long*) (AIC_BASE + (reg))) = value)
+#define AIC_READ(reg,value) \
+ (value = *((volatile unsigned long*) (AIC_BASE + (reg))))
+
+#define AIC_REG(reg) \
+ (*((volatile unsigned long*) (AIC_BASE + (reg))))
diff --git a/include/asm-arm/arch-at572d940hf/at91_pio.h b/include/asm-arm/arch-at572d940hf/at91_pio.h
new file mode 100644
index 0000000..8b85d66
--- /dev/null
+++ b/include/asm-arm/arch-at572d940hf/at91_pio.h
@@ -0,0 +1,51 @@
+/*
+ * include/asm-arm/arch-at91/at91_pio.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Parallel I/O Controller (PIO) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_PIO_H
+#define AT91_PIO_H
+
+#include <asm/arch/at572d940hf.h>
+
+#define PIO_PER 0x00 /* Enable Register */
+#define PIO_PDR 0x04 /* Disable Register */
+#define PIO_PSR 0x08 /* Status Register */
+#define PIO_OER 0x10 /* Output Enable Register */
+#define PIO_ODR 0x14 /* Output Disable Register */
+#define PIO_OSR 0x18 /* Output Status Register */
+#define PIO_IFER 0x20 /* Glitch Input Filter Enable */
+#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
+#define PIO_IFSR 0x28 /* Glitch Input Filter Status */
+#define PIO_SODR 0x30 /* Set Output Data Register */
+#define PIO_CODR 0x34 /* Clear Output Data Register */
+#define PIO_ODSR 0x38 /* Output Data Status Register */
+#define PIO_PDSR 0x3c /* Pin Data Status Register */
+#define PIO_IER 0x40 /* Interrupt Enable Register */
+#define PIO_IDR 0x44 /* Interrupt Disable Register */
+#define PIO_IMR 0x48 /* Interrupt Mask Register */
+#define PIO_ISR 0x4c /* Interrupt Status Register */
+#define PIO_MDER 0x50 /* Multi-driver Enable Register */
+#define PIO_MDDR 0x54 /* Multi-driver Disable Register */
+#define PIO_MDSR 0x58 /* Multi-driver Status Register */
+#define PIO_PUDR 0x60 /* Pull-up Disable Register */
+#define PIO_PUER 0x64 /* Pull-up Enable Register */
+#define PIO_PUSR 0x68 /* Pull-up Status Register */
+#define PIO_ASR 0x70 /* Peripheral A Select Register */
+#define PIO_BSR 0x74 /* Peripheral B Select Register */
+#define PIO_ABSR 0x78 /* AB Status Register */
+#define PIO_OWER 0xa0 /* Output Write Enable Register */
+#define PIO_OWDR 0xa4 /* Output Write Disable Register */
+#define PIO_OWSR 0xa8 /* Output Write Status Register */
+
+#endif
diff --git a/include/asm-arm/arch-at572d940hf/at91_pit.h b/include/asm-arm/arch-at572d940hf/at91_pit.h
new file mode 100644
index 0000000..b854ff9
--- /dev/null
+++ b/include/asm-arm/arch-at572d940hf/at91_pit.h
@@ -0,0 +1,29 @@
+/*
+ * include/asm-arm/arch-at91/at91_pit.h
+ *
+ * Periodic Interval Timer (PIT) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_PIT_H
+#define AT91_PIT_H
+
+#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */
+#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */
+#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */
+#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */
+
+#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */
+#define AT91_PIT_PITS (1 << 0) /* Timer Status */
+
+#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */
+#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */
+#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */
+#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */
+
+#endif
diff --git a/include/asm-arm/arch-at572d940hf/at91_pmc.h b/include/asm-arm/arch-at572d940hf/at91_pmc.h
new file mode 100644
index 0000000..aef0926
--- /dev/null
+++ b/include/asm-arm/arch-at572d940hf/at91_pmc.h
@@ -0,0 +1,101 @@
+/*
+ * include/asm-arm/arch-at91/at91_pmc.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Power Management Controller (PMC) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_PMC_H
+#define AT91_PMC_H
+
+#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
+#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
+
+#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
+#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
+#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
+#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
+#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
+#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
+#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */
+#define AT572D940HF_PMC_UHP (1 << 6) /* USB Host Port Clock [AT572D940HF] */
+#define AT572D940HF_PMC_UDP (1 << 7) /* USB Device Port Clock [AT572D940HF] */
+#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Decice Port Clock [AT91SAM926x only] */
+#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
+#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
+#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
+#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
+#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
+#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
+
+#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
+#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
+#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
+
+#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */
+
+#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
+#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
+#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */
+#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
+
+#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
+#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
+#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
+
+#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
+#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
+#define AT91_PMC_DIV (0xff << 0) /* Divider */
+#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
+#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
+#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
+#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
+#define AT91_PMC_USBDIV_1 (0 << 28)
+#define AT91_PMC_USBDIV_2 (1 << 28)
+#define AT91_PMC_USBDIV_4 (2 << 28)
+#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
+
+#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
+#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
+#define AT91_PMC_CSS_SLOW (0 << 0)
+#define AT91_PMC_CSS_MAIN (1 << 0)
+#define AT91_PMC_CSS_PLLA (2 << 0)
+#define AT91_PMC_CSS_PLLB (3 << 0)
+#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
+#define AT91_PMC_PRES_1 (0 << 2)
+#define AT91_PMC_PRES_2 (1 << 2)
+#define AT91_PMC_PRES_4 (2 << 2)
+#define AT91_PMC_PRES_8 (3 << 2)
+#define AT91_PMC_PRES_16 (4 << 2)
+#define AT91_PMC_PRES_32 (5 << 2)
+#define AT91_PMC_PRES_64 (6 << 2)
+#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
+#define AT91_PMC_MDIV_1 (0 << 8)
+#define AT91_PMC_MDIV_2 (1 << 8)
+#define AT91_PMC_MDIV_3 (2 << 8)
+#define AT91_PMC_MDIV_4 (3 << 8)
+
+#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
+
+#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
+#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
+#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
+#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
+#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
+#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
+#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
+#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
+#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
+#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
+#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
+#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
+
+#endif
diff --git a/include/asm-arm/arch-at572d940hf/at91_rstc.h b/include/asm-arm/arch-at572d940hf/at91_rstc.h
new file mode 100644
index 0000000..aae10c0
--- /dev/null
+++ b/include/asm-arm/arch-at572d940hf/at91_rstc.h
@@ -0,0 +1,38 @@
+/*
+ * include/asm-arm/arch-at91/at91_rstc.h
+ *
+ * Reset Controller (RSTC) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_RSTC_H
+#define AT91_RSTC_H
+
+#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */
+#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
+#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */
+#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */
+#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */
+
+#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */
+#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */
+#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */
+#define AT91_RSTC_RSTTYP_GENERAL (0 << 8)
+#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8)
+#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8)
+#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8)
+#define AT91_RSTC_RSTTYP_USER (4 << 8)
+#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */
+#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */
+
+#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */
+#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */
+#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */
+#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */
+
+#endif
diff --git a/include/asm-arm/arch-at572d940hf/at91_spi.h b/include/asm-arm/arch-at572d940hf/at91_spi.h
new file mode 100644
index 0000000..b753b90
--- /dev/null
+++ b/include/asm-arm/arch-at572d940hf/at91_spi.h
@@ -0,0 +1,105 @@
+/*
+ * include/asm-arm/arch-at91/at91_spi.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Serial Peripheral Interface (SPI) registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_SPI_H
+#define AT91_SPI_H
+
+#define AT91_SPI_CR 0x00 /* Control Register */
+#define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */
+#define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */
+#define AT91_SPI_SWRST (1 << 7) /* SPI Software Reset */
+#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
+
+#define AT91_SPI_MR 0x04 /* Mode Register */
+#define AT91_SPI_MSTR (1 << 0) /* Master/Slave Mode */
+#define AT91_SPI_PS (1 << 1) /* Peripheral Select */
+#define AT91_SPI_PS_FIXED (0 << 1)
+#define AT91_SPI_PS_VARIABLE (1 << 1)
+#define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */
+#define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */
+#define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */
+#define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */
+#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
+#define AT91_SPI_DLYBCS (0xff << 24) /* Delay Between Chip Selects */
+
+#define AT91_SPI_RDR 0x08 /* Receive Data Register */
+#define AT91_SPI_RD (0xffff << 0) /* Receive Data */
+#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
+
+#define AT91_SPI_TDR 0x0c /* Transmit Data Register */
+#define AT91_SPI_TD (0xffff << 0) /* Transmit Data */
+#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
+#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
+
+#define AT91_SPI_SR 0x10 /* Status Register */
+#define AT91_SPI_RDRF (1 << 0) /* Receive Data Register Full */
+#define AT91_SPI_TDRE (1 << 1) /* Transmit Data Register Full */
+#define AT91_SPI_MODF (1 << 2) /* Mode Fault Error */
+#define AT91_SPI_OVRES (1 << 3) /* Overrun Error Status */
+#define AT91_SPI_ENDRX (1 << 4) /* End of RX buffer */
+#define AT91_SPI_ENDTX (1 << 5) /* End of TX buffer */
+#define AT91_SPI_RXBUFF (1 << 6) /* RX Buffer Full */
+#define AT91_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */
+#define AT91_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */
+#define AT91_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */
+#define AT91_SPI_SPIENS (1 << 16) /* SPI Enable Status */
+
+#define AT91_SPI_IER 0x14 /* Interrupt Enable Register */
+#define AT91_SPI_IDR 0x18 /* Interrupt Disable Register */
+#define AT91_SPI_IMR 0x1c /* Interrupt Mask Register */
+
+#define AT91_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */
+#define AT91_SPI_CPOL (1 << 0) /* Clock Polarity */
+#define AT91_SPI_NCPHA (1 << 1) /* Clock Phase */
+#define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */
+#define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */
+#define AT91_SPI_BITS_8 (0 << 4)
+#define AT91_SPI_BITS_9 (1 << 4)
+#define AT91_SPI_BITS_10 (2 << 4)
+#define AT91_SPI_BITS_11 (3 << 4)
+#define AT91_SPI_BITS_12 (4 << 4)
+#define AT91_SPI_BITS_13 (5 << 4)
+#define AT91_SPI_BITS_14 (6 << 4)
+#define AT91_SPI_BITS_15 (7 << 4)
+#define AT91_SPI_BITS_16 (8 << 4)
+#define AT91_SPI_SCBR (0xff << 8) /* Serial Clock Baud Rate */
+#define AT91_SPI_DLYBS (0xff << 16) /* Delay before SPCK */
+#define AT91_SPI_DLYBCT (0xff << 24) /* Delay between Consecutive Transfers */
+
+#define AT91_SPI_RPR 0x0100 /* Receive Pointer Register */
+
+#define AT91_SPI_RCR 0x0104 /* Receive Counter Register */
+
+#define AT91_SPI_TPR 0x0108 /* Transmit Pointer Register */
+
+#define AT91_SPI_TCR 0x010c /* Transmit Counter Register */
+
+#define AT91_SPI_RNPR 0x0110 /* Receive Next Pointer Register */
+
+#define AT91_SPI_RNCR 0x0114 /* Receive Next Counter Register */
+
+#define AT91_SPI_TNPR 0x0118 /* Transmit Next Pointer Register */
+
+#define AT91_SPI_TNCR 0x011c /* Transmit Next Counter Register */
+
+#define AT91_SPI_PTCR 0x0120 /* PDC Transfer Control Register */
+#define AT91_SPI_RXTEN (0x1 << 0) /* Receiver Transfer Enable */
+#define AT91_SPI_RXTDIS (0x1 << 1) /* Receiver Transfer Disable */
+#define AT91_SPI_TXTEN (0x1 << 8) /* Transmitter Transfer Enable */
+#define AT91_SPI_TXTDIS (0x1 << 9) /* Transmitter Transfer Disable */
+
+#define AT91_SPI_PTSR 0x0124 /* PDC Transfer Status Register */
+
+#endif
diff --git a/include/asm-arm/arch-at572d940hf/clk.h b/include/asm-arm/arch-at572d940hf/clk.h
new file mode 100644
index 0000000..06e6b2b
--- /dev/null
+++ b/include/asm-arm/arch-at572d940hf/clk.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2007
+ * Stelian Pop <stelian.pop <at> leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_ARM_ARCH_CLK_H__
+#define __ASM_ARM_ARCH_CLK_H__
+
+#include <asm/arch/hardware.h>
+
+static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
+{
+ return AT91_MASTER_CLOCK;
+}
+
+static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
+{
+ return AT91_MASTER_CLOCK;
+}
+
+static inline unsigned long get_mci_clk_rate(void)
+{
+ return AT91_MASTER_CLOCK;
+}
+
+#endif /* __ASM_ARM_ARCH_CLK_H__ */
diff --git a/include/asm-arm/arch-at572d940hf/gpio.h b/include/asm-arm/arch-at572d940hf/gpio.h
new file mode 100644
index 0000000..cc6b182
--- /dev/null
+++ b/include/asm-arm/arch-at572d940hf/gpio.h
@@ -0,0 +1,366 @@
+/*
+ * include/asm-arm/arch-at91/gpio.h
+ *
+ * Copyright (C) 2005 HP Labs
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_AT91_GPIO_H
+#define __ASM_ARCH_AT91_GPIO_H
+
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/at91_pio.h>
+
+#define PIN_BASE 32
+
+#define MAX_GPIO_BANKS 5
+
+/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
+
+#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0)
+#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1)
+#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2)
+#define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3)
+#define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4)
+#define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5)
+#define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6)
+#define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7)
+#define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8)
+#define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9)
+#define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10)
+#define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11)
+#define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12)
+#define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13)
+#define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14)
+#define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15)
+#define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16)
+#define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17)
+#define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18)
+#define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19)
+#define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20)
+#define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21)
+#define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22)
+#define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23)
+#define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24)
+#define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25)
+#define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26)
+#define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27)
+#define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28)
+#define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29)
+#define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30)
+#define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31)
+
+#define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0)
+#define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1)
+#define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2)
+#define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3)
+#define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4)
+#define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5)
+#define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6)
+#define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7)
+#define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8)
+#define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9)
+#define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10)
+#define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11)
+#define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12)
+#define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13)
+#define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14)
+#define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15)
+#define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16)
+#define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17)
+#define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18)
+#define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19)
+#define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20)
+#define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21)
+#define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22)
+#define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23)
+#define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24)
+#define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25)
+#define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26)
+#define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27)
+#define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28)
+#define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29)
+#define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30)
+#define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31)
+
+#define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0)
+#define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1)
+#define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2)
+#define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3)
+#define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4)
+#define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5)
+#define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6)
+#define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7)
+#define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8)
+#define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9)
+#define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10)
+#define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11)
+#define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12)
+#define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13)
+#define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14)
+#define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15)
+#define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16)
+#define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17)
+#define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18)
+#define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19)
+#define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20)
+#define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21)
+#define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22)
+#define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23)
+#define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24)
+#define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25)
+#define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26)
+#define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27)
+#define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28)
+#define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29)
+#define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30)
+#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31)
+
+#define AT91_PIN_PD0 (PIN_BASE + 0x60 + 0)
+#define AT91_PIN_PD1 (PIN_BASE + 0x60 + 1)
+#define AT91_PIN_PD2 (PIN_BASE + 0x60 + 2)
+#define AT91_PIN_PD3 (PIN_BASE + 0x60 + 3)
+#define AT91_PIN_PD4 (PIN_BASE + 0x60 + 4)
+#define AT91_PIN_PD5 (PIN_BASE + 0x60 + 5)
+#define AT91_PIN_PD6 (PIN_BASE + 0x60 + 6)
+#define AT91_PIN_PD7 (PIN_BASE + 0x60 + 7)
+#define AT91_PIN_PD8 (PIN_BASE + 0x60 + 8)
+#define AT91_PIN_PD9 (PIN_BASE + 0x60 + 9)
+#define AT91_PIN_PD10 (PIN_BASE + 0x60 + 10)
+#define AT91_PIN_PD11 (PIN_BASE + 0x60 + 11)
+#define AT91_PIN_PD12 (PIN_BASE + 0x60 + 12)
+#define AT91_PIN_PD13 (PIN_BASE + 0x60 + 13)
+#define AT91_PIN_PD14 (PIN_BASE + 0x60 + 14)
+#define AT91_PIN_PD15 (PIN_BASE + 0x60 + 15)
+#define AT91_PIN_PD16 (PIN_BASE + 0x60 + 16)
+#define AT91_PIN_PD17 (PIN_BASE + 0x60 + 17)
+#define AT91_PIN_PD18 (PIN_BASE + 0x60 + 18)
+#define AT91_PIN_PD19 (PIN_BASE + 0x60 + 19)
+#define AT91_PIN_PD20 (PIN_BASE + 0x60 + 20)
+#define AT91_PIN_PD21 (PIN_BASE + 0x60 + 21)
+#define AT91_PIN_PD22 (PIN_BASE + 0x60 + 22)
+#define AT91_PIN_PD23 (PIN_BASE + 0x60 + 23)
+#define AT91_PIN_PD24 (PIN_BASE + 0x60 + 24)
+#define AT91_PIN_PD25 (PIN_BASE + 0x60 + 25)
+#define AT91_PIN_PD26 (PIN_BASE + 0x60 + 26)
+#define AT91_PIN_PD27 (PIN_BASE + 0x60 + 27)
+#define AT91_PIN_PD28 (PIN_BASE + 0x60 + 28)
+#define AT91_PIN_PD29 (PIN_BASE + 0x60 + 29)
+#define AT91_PIN_PD30 (PIN_BASE + 0x60 + 30)
+#define AT91_PIN_PD31 (PIN_BASE + 0x60 + 31)
+
+#define AT91_PIN_PE0 (PIN_BASE + 0x80 + 0)
+#define AT91_PIN_PE1 (PIN_BASE + 0x80 + 1)
+#define AT91_PIN_PE2 (PIN_BASE + 0x80 + 2)
+#define AT91_PIN_PE3 (PIN_BASE + 0x80 + 3)
+#define AT91_PIN_PE4 (PIN_BASE + 0x80 + 4)
+#define AT91_PIN_PE5 (PIN_BASE + 0x80 + 5)
+#define AT91_PIN_PE6 (PIN_BASE + 0x80 + 6)
+#define AT91_PIN_PE7 (PIN_BASE + 0x80 + 7)
+#define AT91_PIN_PE8 (PIN_BASE + 0x80 + 8)
+#define AT91_PIN_PE9 (PIN_BASE + 0x80 + 9)
+#define AT91_PIN_PE10 (PIN_BASE + 0x80 + 10)
+#define AT91_PIN_PE11 (PIN_BASE + 0x80 + 11)
+#define AT91_PIN_PE12 (PIN_BASE + 0x80 + 12)
+#define AT91_PIN_PE13 (PIN_BASE + 0x80 + 13)
+#define AT91_PIN_PE14 (PIN_BASE + 0x80 + 14)
+#define AT91_PIN_PE15 (PIN_BASE + 0x80 + 15)
+#define AT91_PIN_PE16 (PIN_BASE + 0x80 + 16)
+#define AT91_PIN_PE17 (PIN_BASE + 0x80 + 17)
+#define AT91_PIN_PE18 (PIN_BASE + 0x80 + 18)
+#define AT91_PIN_PE19 (PIN_BASE + 0x80 + 19)
+#define AT91_PIN_PE20 (PIN_BASE + 0x80 + 20)
+#define AT91_PIN_PE21 (PIN_BASE + 0x80 + 21)
+#define AT91_PIN_PE22 (PIN_BASE + 0x80 + 22)
+#define AT91_PIN_PE23 (PIN_BASE + 0x80 + 23)
+#define AT91_PIN_PE24 (PIN_BASE + 0x80 + 24)
+#define AT91_PIN_PE25 (PIN_BASE + 0x80 + 25)
+#define AT91_PIN_PE26 (PIN_BASE + 0x80 + 26)
+#define AT91_PIN_PE27 (PIN_BASE + 0x80 + 27)
+#define AT91_PIN_PE28 (PIN_BASE + 0x80 + 28)
+#define AT91_PIN_PE29 (PIN_BASE + 0x80 + 29)
+#define AT91_PIN_PE30 (PIN_BASE + 0x80 + 30)
+#define AT91_PIN_PE31 (PIN_BASE + 0x80 + 31)
+
+static unsigned long at91_pios[] = {
+ AT91_PIOA,
+ AT91_PIOB,
+ AT91_PIOC,
+#ifdef AT91_PIOD
+ AT91_PIOD,
+#ifdef AT91_PIOE
+ AT91_PIOE
+#endif
+#endif
+};
+
+static inline void *pin_to_controller(unsigned pin)
+{
+ pin -= PIN_BASE;
+ pin /= 32;
+ return (void *)(AT91_BASE_SYS + at91_pios[pin]);
+}
+
+static inline unsigned pin_to_mask(unsigned pin)
+{
+ pin -= PIN_BASE;
+ return 1 << (pin % 32);
+}
+
+/*
+ * mux the pin to the "GPIO" peripheral role.
+ */
+static inline int at91_set_GPIO_periph(unsigned pin, int use_pullup)
+{
+ void *pio = pin_to_controller(pin);
+ unsigned mask = pin_to_mask(pin);
+
+ __raw_writel(mask, pio + PIO_IDR);
+ __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
+ __raw_writel(mask, pio + PIO_PER);
+ return 0;
+}
+
+/*
+ * mux the pin to the "A" internal peripheral role.
+ */
+static inline int at91_set_A_periph(unsigned pin, int use_pullup)
+{
+ void *pio = pin_to_controller(pin);
+ unsigned mask = pin_to_mask(pin);
+
+ __raw_writel(mask, pio + PIO_IDR);
+ __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
+ __raw_writel(mask, pio + PIO_ASR);
+ __raw_writel(mask, pio + PIO_PDR);
+ return 0;
+}
+
+/*
+ * mux the pin to the "B" internal peripheral role.
+ */
+static inline int at91_set_B_periph(unsigned pin, int use_pullup)
+{
+ void *pio = pin_to_controller(pin);
+ unsigned mask = pin_to_mask(pin);
+
+ __raw_writel(mask, pio + PIO_IDR);
+ __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
+ __raw_writel(mask, pio + PIO_BSR);
+ __raw_writel(mask, pio + PIO_PDR);
+ return 0;
+}
+
+/*
+ * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
+ * configure it for an input.
+ */
+static inline int at91_set_gpio_input(unsigned pin, int use_pullup)
+{
+ void *pio = pin_to_controller(pin);
+ unsigned mask = pin_to_mask(pin);
+
+ __raw_writel(mask, pio + PIO_IDR);
+ __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
+ __raw_writel(mask, pio + PIO_ODR);
+ __raw_writel(mask, pio + PIO_PER);
+ return 0;
+}
+
+/*
+ * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
+ * and configure it for an output.
+ */
+static inline int at91_set_gpio_output(unsigned pin, int value)
+{
+ void *pio = pin_to_controller(pin);
+ unsigned mask = pin_to_mask(pin);
+
+ __raw_writel(mask, pio + PIO_IDR);
+ __raw_writel(mask, pio + PIO_PUDR);
+ __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
+ __raw_writel(mask, pio + PIO_OER);
+ __raw_writel(mask, pio + PIO_PER);
+ return 0;
+}
+
+/*
+ * enable/disable the glitch filter; mostly used with IRQ handling.
+ */
+static inline int at91_set_deglitch(unsigned pin, int is_on)
+{
+ void *pio = pin_to_controller(pin);
+ unsigned mask = pin_to_mask(pin);
+
+ __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
+ return 0;
+}
+
+/*
+ * enable/disable the multi-driver; This is only valid for output and
+ * allows the output pin to run as an open collector output.
+ */
+static inline int at91_set_multi_drive(unsigned pin, int is_on)
+{
+ void *pio = pin_to_controller(pin);
+ unsigned mask = pin_to_mask(pin);
+
+ __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
+ return 0;
+}
+
+static inline int gpio_direction_input(unsigned pin)
+{
+ void *pio = pin_to_controller(pin);
+ unsigned mask = pin_to_mask(pin);
+
+ if (!(__raw_readl(pio + PIO_PSR) & mask))
+ return -EINVAL;
+ __raw_writel(mask, pio + PIO_ODR);
+ return 0;
+}
+
+static inline int gpio_direction_output(unsigned pin, int value)
+{
+ void *pio = pin_to_controller(pin);
+ unsigned mask = pin_to_mask(pin);
+
+ if (!(__raw_readl(pio + PIO_PSR) & mask))
+ return -EINVAL;
+ __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
+ __raw_writel(mask, pio + PIO_OER);
+ return 0;
+}
+
+/*
+ * assuming the pin is muxed as a gpio output, set its value.
+ */
+static inline int at91_set_gpio_value(unsigned pin, int value)
+{
+ void *pio = pin_to_controller(pin);
+ unsigned mask = pin_to_mask(pin);
+
+ __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
+ return 0;
+}
+
+/*
+ * read the pin's value (works even if it's not muxed as a gpio).
+ */
+static inline int at91_get_gpio_value(unsigned pin)
+{
+ void *pio = pin_to_controller(pin);
+ unsigned mask = pin_to_mask(pin);
+ u32 pdsr;
+
+ pdsr = __raw_readl(pio + PIO_PDSR);
+ return (pdsr & mask) != 0;
+}
+
+#endif
diff --git a/include/asm-arm/arch-at572d940hf/hardware.h b/include/asm-arm/arch-at572d940hf/hardware.h
new file mode 100644
index 0000000..f649b41
--- /dev/null
+++ b/include/asm-arm/arch-at572d940hf/hardware.h
@@ -0,0 +1,36 @@
+/*
+ * include/asm-arm/arch-at91/hardware.h
+ *
+ * Copyright (C) 2003 SAN People
+ * Copyright (C) 2003 ATMEL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+
+#if defined(CONFIG_AT572D940HF)
+#include <asm/arch/at572d940hf.h>
+#else
+#error "Unsupported AT572D940HF processor"
+#endif
+
+/*
+ * container_of - cast a member of a structure out to the containing structure
+ *
+ * @ptr: the pointer to the member.
+ * @type: the type of the container struct this is embedded in.
+ * @member: the name of the member within the struct.
+ */
+#define container_of(ptr, type, member) ({ \
+ const typeof(((type *)0)->member) *__mptr = (ptr); \
+ (type *)((char *)__mptr - offsetof(type, member)); })
+
+#endif
diff --git a/include/asm-arm/arch-at572d940hf/io.h b/include/asm-arm/arch-at572d940hf/io.h
new file mode 100644
index 0000000..be9e9ab
--- /dev/null
+++ b/include/asm-arm/arch-at572d940hf/io.h
@@ -0,0 +1,40 @@
+/*
+ * include/asm-arm/arch-at91/io.h
+ *
+ * Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#include <asm/io.h>
+
+static inline unsigned int at91_sys_read(unsigned int reg_offset)
+{
+ void *addr = (void *)AT91_BASE_SYS;
+
+ return __raw_readl(addr + reg_offset);
+}
+
+static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
+{
+ void *addr = (void *)AT91_BASE_SYS;
+
+ __raw_writel(value, addr + reg_offset);
+}
+
+#endif
diff --git a/include/asm-arm/arch-at572d940hf/memory-map.h b/include/asm-arm/arch-at572d940hf/memory-map.h
new file mode 100644
index 0000000..a590d59
--- /dev/null
+++ b/include/asm-arm/arch-at572d940hf/memory-map.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop <at> leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_ARM_ARCH_MEMORYMAP_H__
+#define __ASM_ARM_ARCH_MEMORYMAP_H__
+
+#include <asm/arch/hardware.h>
+
+#define USART0_BASE AT91_USART0
+#define USART1_BASE AT91_USART1
+#define USART2_BASE AT91_USART2
+#define USART3_BASE (AT91_BASE_SYS + AT91_DBGU)
+
+#define AT572D940_SDRAM_BASE 0x20000000
+
+#endif /* __ASM_ARM_ARCH_MEMORYMAP_H__ */
--
1.5.4.3
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [U-Boot-Users] [PATCH 4/6] AT572D940HF-EB Support v2 (include files part 2)
2008-06-12 14:14 ` [U-Boot-Users] [PATCH 3/6] AT572D940HF-EB Support v2 (include files part 1) Antonio R. Costa
@ 2008-06-12 14:14 ` Antonio R. Costa
2008-06-12 14:15 ` [U-Boot-Users] [PATCH 5/6] AT572D940HF-EB Support v2 (ethernet files) Antonio R. Costa
2008-07-05 20:38 ` [U-Boot-Users] [PATCH 4/6] AT572D940HF-EB Support v2 (include files part 2) Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 2 replies; 26+ messages in thread
From: Antonio R. Costa @ 2008-06-12 14:14 UTC (permalink / raw)
To: u-boot
Signed-off-by: Antonio R. Costa <antonio.costa@atmel.com>
diff --git a/include/asm-arm/arch-at572d940hf/at572d940hf.h b/include/asm-arm/arch-at572d940hf/at572d940hf.h
new file mode 100644
index 0000000..53f049b
--- /dev/null
+++ b/include/asm-arm/arch-at572d940hf/at572d940hf.h
@@ -0,0 +1,147 @@
+/*
+ * include/asm-arm/arch-at91/AT572D940HFhf.h
+ *
+ * (C) 2008 Antonio R. Costa
+ *
+ * Common definitions.
+ * Based on AT572D940HFHF datasheet rev A.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT572D940HFHF_H
+#define AT572D940HFHF_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS 1 /* System Peripherals */
+#define AT572D940HF_ID_PIOA 2 /* Parallel IO Controller A */
+#define AT572D940HF_ID_PIOB 3 /* Parallel IO Controller B */
+#define AT572D940HF_ID_PIOC 4 /* Parallel IO Controller C */
+#define AT572D940HF_ID_EMAC 5 /* Ethernet */
+#define AT572D940HF_ID_US0 6 /* USART 0 */
+#define AT572D940HF_ID_US1 7 /* USART 1 */
+#define AT572D940HF_ID_US2 8 /* USART 2 */
+#define AT572D940HF_ID_MCI 9 /* Multimedia Card Interface */
+#define AT572D940HF_ID_UDP 10 /* USB Device Port */
+#define AT572D940HF_ID_TWI 11 /* Two-Wire Interface */
+#define AT572D940HF_ID_TWI0 11 /* Two-Wire Interface */
+#define AT572D940HF_ID_SPI0 12 /* Serial Peripheral Interface 0 */
+#define AT572D940HF_ID_SPI1 13 /* Serial Peripheral Interface 1 */
+#define AT572D940HF_ID_SSC 14 /* Serial Synchronous Controller */
+#define AT572D940HF_ID_SSC0 14 /* Serial Synchronous Controller */
+#define AT572D940HF_ID_SSC1 15 /* Serial Synchronous Controller */
+#define AT572D940HF_ID_SSC2 16 /* Serial Synchronous Controller */
+#define AT572D940HF_ID_TC0 17 /* Timer Counter 0 */
+#define AT572D940HF_ID_TC1 18 /* Timer Counter 1 */
+#define AT572D940HF_ID_TC2 19 /* Timer Counter 2 */
+#define AT572D940HF_ID_UHP 20 /* USB Host port */
+#define AT572D940HF_ID_SSC3 21 /* Serial Synchronous Controller */
+#define AT572D940HF_ID_TWI1 22 /* Two-Wire Interface */
+#define AT572D940HF_ID_CAN0 23 /* CAN Controller */
+#define AT572D940HF_ID_CAN1 24 /* CAN Controller */
+#define AT572D940HF_ID_mHALT 25 /* mAgicV DSP halt int */
+#define AT572D940HF_ID_mSIRQ1 26 /* mAgicV DSP SIRQ1 int */
+#define AT572D940HF_ID_mEXC 27 /* mAgicV DSP Exception int */
+#define AT572D940HF_ID_mEDMA 28 /* mAgicV DSP end of DMA transfer int */
+#define AT572D940HF_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
+#define AT572D940HF_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
+#define AT572D940HF_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
+
+#define AT91_ID_US0 AT572D940HF_ID_US0
+#define AT91_ID_US1 AT572D940HF_ID_US1
+#define AT91_ID_US2 AT572D940HF_ID_US2
+#define AT91_ID_US3 AT572D940HF_ID_US3
+
+#define AT91_ID_UHP AT572D940HF_ID_UHP
+#define AT91_PMC_UHP AT572D940HF_ID_UHP
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT572D940HF_BASE_TCB0 0xfffa0000
+#define AT572D940HF_BASE_TC0 0xfffa0000
+#define AT572D940HF_BASE_TC1 0xfffa0040
+#define AT572D940HF_BASE_TC2 0xfffa0080
+#define AT572D940HF_BASE_UDP 0xfffa4000
+#define AT572D940HF_BASE_MCI 0xfffa8000
+#define AT572D940HF_BASE_TWI 0xfffac000
+#define AT572D940HF_BASE_US0 0xfffb0000
+#define AT572D940HF_BASE_US1 0xfffb4000
+#define AT572D940HF_BASE_US2 0xfffb8000
+#define AT572D940HF_BASE_SSC 0xfffbc000
+#define AT572D940HF_BASE_ISI 0xfffc0000
+#define AT572D940HF_BASE_EMAC 0xfffd8000
+#define AT572D940HF_BASE_SPI0 0xfffc8000
+#define AT572D940HF_BASE_SPI1 0xfffcc000
+#define AT572D940HF_BASE_US3 0xfffd0000
+#define AT572D940HF_BASE_US4 0xfffd4000
+#define AT572D940HF_BASE_US5 0xfffd8000
+#define AT572D940HF_BASE_TCB1 0xfffdc000
+#define AT572D940HF_BASE_TC3 0xfffdc000
+#define AT572D940HF_BASE_TC4 0xfffdc040
+#define AT572D940HF_BASE_TC5 0xfffdc080
+#define AT572D940HF_BASE_ADC 0xfffe0000
+#define AT572D940HF_BASE_RSTC 0xfffffd00
+#define AT91_BASE_SYS 0xffffea00
+
+#define AT91_BASE_EMAC AT572D940HF_BASE_EMAC
+#define AT91_BASE_SPI AT572D940HF_BASE_SPI0
+#define MMCI_BASE AT572D940HF_BASE_MCI
+
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
+#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
+#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
+#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
+#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
+#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
+#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
+#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
+#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
+
+#define AT91_USART0 AT572D940HF_BASE_US0
+#define AT91_USART1 AT572D940HF_BASE_US1
+#define AT91_USART2 AT572D940HF_BASE_US2
+#define AT91_USART3 AT572D940HF_BASE_US3
+#define AT91_USART4 AT572D940HF_BASE_US4
+#define AT91_USART5 AT572D940HF_BASE_US5
+
+/*
+ * Internal Memory.
+ */
+#define AT572D940HF_ROM_BASE 0x00400000 /* Internal ROM base address */
+#define AT572D940HF_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
+
+#define AT572D940HF_SRAM0_BASE 0x00100000 /* Internal SRAM 0 base address */
+#define AT572D940HF_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (4Kb) */
+#define AT572D940HF_SRAM1_BASE 0x00200000 /* Internal SRAM 0 base address */
+#define AT572D940HF_SRAM1_SIZE SZ_16K /* Internal SRAM 0 size (4Kb) */
+#define AT572D940HF_SRAM2_BASE 0x00300000 /* Internal SRAM 1 base address */
+#define AT572D940HF_SRAM2_SIZE SZ_16K /* Internal SRAM 1 size (4Kb) */
+
+//SDRAM
+#define AT572D940HF_SDRAM_BASE 0x20000000
+
+// USB Host
+#define AT572D940HF_UHP_BASE 0x00500000 /* USB Host controller */
+
+#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */
+#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */
+
+#endif
diff --git a/include/asm-arm/arch-at572d940hf/at572d940hf_matrix.h b/include/asm-arm/arch-at572d940hf/at572d940hf_matrix.h
new file mode 100644
index 0000000..a8e9fec
--- /dev/null
+++ b/include/asm-arm/arch-at572d940hf/at572d940hf_matrix.h
@@ -0,0 +1,78 @@
+/*
+ * include/asm-arm/arch-at91/at91sam9260_matrix.h
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9260 datasheet revision B.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9260_MATRIX_H
+#define AT91SAM9260_MATRIX_H
+
+#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
+#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
+#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
+#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
+#define AT91_MATRIX_ULBT_FOUR (2 << 0)
+#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
+#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
+
+#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
+#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
+#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
+#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
+#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+
+#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
+#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
+#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
+#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
+#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
+#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
+#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
+
+#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
+#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+
+#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */
+#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
+#define AT91_MATRIX_CS1A_SMC (0 << 1)
+#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
+#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
+#define AT91_MATRIX_CS3A_SMC (0 << 3)
+#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
+#define AT91_MATRIX_CS4A_SMC (0 << 4)
+#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
+#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
+#define AT91_MATRIX_CS5A_SMC (0 << 5)
+#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
+#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
+#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
+#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
+#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
+
+#endif
diff --git a/include/asm-arm/arch-at572d940hf/at572d940hf_mc.h b/include/asm-arm/arch-at572d940hf/at572d940hf_mc.h
new file mode 100644
index 0000000..161d504
--- /dev/null
+++ b/include/asm-arm/arch-at572d940hf/at572d940hf_mc.h
@@ -0,0 +1,140 @@
+/*
+ * include/asm-arm/arch-at91/at91sam926x_mc.h
+ *
+ * Memory Controllers (SMC, SDRAMC) - System peripherals registers.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM926x_MC_H
+#define AT91SAM926x_MC_H
+
+/* SDRAM Controller (SDRAMC) registers */
+#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */
+#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
+#define AT91_SDRAMC_MODE_NORMAL 0
+#define AT91_SDRAMC_MODE_NOP 1
+#define AT91_SDRAMC_MODE_PRECHARGE 2
+#define AT91_SDRAMC_MODE_LMR 3
+#define AT91_SDRAMC_MODE_REFRESH 4
+#define AT91_SDRAMC_MODE_EXT_LMR 5
+#define AT91_SDRAMC_MODE_DEEP 6
+
+#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */
+#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
+
+#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */
+#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
+#define AT91_SDRAMC_NC_8 (0 << 0)
+#define AT91_SDRAMC_NC_9 (1 << 0)
+#define AT91_SDRAMC_NC_10 (2 << 0)
+#define AT91_SDRAMC_NC_11 (3 << 0)
+#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
+#define AT91_SDRAMC_NR_11 (0 << 2)
+#define AT91_SDRAMC_NR_12 (1 << 2)
+#define AT91_SDRAMC_NR_13 (2 << 2)
+#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
+#define AT91_SDRAMC_NB_2 (0 << 4)
+#define AT91_SDRAMC_NB_4 (1 << 4)
+#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
+#define AT91_SDRAMC_CAS_1 (1 << 5)
+#define AT91_SDRAMC_CAS_2 (2 << 5)
+#define AT91_SDRAMC_CAS_3 (3 << 5)
+#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */
+#define AT91_SDRAMC_DBW_32 (0 << 7)
+#define AT91_SDRAMC_DBW_16 (1 << 7)
+#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */
+#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */
+#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */
+#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */
+#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
+#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
+
+#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */
+#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
+#define AT91_SDRAMC_LPCB_DISABLE 0
+#define AT91_SDRAMC_LPCB_SELF_REFRESH 1
+#define AT91_SDRAMC_LPCB_POWER_DOWN 2
+#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
+#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
+#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
+#define AT91_SDRAMC_DS (3 << 10) /* Drive Strenght */
+#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
+#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12)
+#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
+#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
+
+#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */
+#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */
+#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */
+#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */
+#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
+
+#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */
+#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
+#define AT91_SDRAMC_MD_SDRAM 0
+#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
+
+/* Static Memory Controller (SMC) registers */
+#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
+#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
+#define AT91_SMC_NWESETUP_(x) ((x) << 0)
+#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
+#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
+#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */
+#define AT91_SMC_NRDSETUP_(x) ((x) << 16)
+#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
+#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
+
+#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
+#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
+#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
+#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
+#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
+#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */
+#define AT91_SMC_NRDPULSE_(x) ((x) << 16)
+#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
+#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
+
+#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
+#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
+#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
+#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
+#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
+
+#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
+#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
+#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
+#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
+#define AT91_SMC_EXNWMODE_DISABLE (0 << 4)
+#define AT91_SMC_EXNWMODE_FROZEN (2 << 4)
+#define AT91_SMC_EXNWMODE_READY (3 << 4)
+#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */
+#define AT91_SMC_BAT_SELECT (0 << 8)
+#define AT91_SMC_BAT_WRITE (1 << 8)
+#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */
+#define AT91_SMC_DBW_8 (0 << 12)
+#define AT91_SMC_DBW_16 (1 << 12)
+#define AT91_SMC_DBW_32 (2 << 12)
+#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */
+#define AT91_SMC_TDF_(x) ((x) << 16)
+#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */
+#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */
+#define AT91_SMC_PS (3 << 28) /* Page Size */
+#define AT91_SMC_PS_4 (0 << 28)
+#define AT91_SMC_PS_8 (1 << 28)
+#define AT91_SMC_PS_16 (2 << 28)
+#define AT91_SMC_PS_32 (3 << 28)
+
+#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */
+#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
+#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
+#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
+#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-at572d940hf/interrupts.h b/include/asm-arm/arch-at572d940hf/interrupts.h
new file mode 100644
index 0000000..71d3f5d
--- /dev/null
+++ b/include/asm-arm/arch-at572d940hf/interrupts.h
@@ -0,0 +1,41 @@
+/*
+ * include/asm-arm/arch-at572d940/at91_aic.h
+ *
+ * Copyright (C) 2008 Antonio R. Costa
+ * Copyright (C) ATMEL
+ *
+ * Advanced Interrupt Controller (AIC).
+ * Based on AT572D940 datasheet.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __AT572D940_INTERRUPTS_H__
+#define __AT572D940_INTERRUPTS_H__
+
+#include <asm/arch/at91_aic.h>
+
+typedef void (*irq_handler_t) (unsigned long int);
+
+#define SET_IRQ_HANDLER(s,m,h) \
+do { \
+ AIC_WRITE(AIC_SMR(s),m); \
+ AIC_WRITE(AIC_SVR(s),h); \
+ AIC_WRITE(AIC_IECR,(1<<s)); \
+} while(0)
+
+#define RESET_IRQ_HANDLER(s) \
+do { \
+ AIC_WRITE(AIC_SMR(s),0); \
+ AIC_WRITE(AIC_SVR(s),0); \
+ AIC_WRITE(AIC_IDCR,(1<<s)); \
+} while(0)
+
+#define IRQ_ACKNOWLEDGE(n) AIC_WRITE(AIC_EOICR,(n))
+
+extern reset_irqs(void);
+
+#endif /* __AT572D940_INTERRUPTS_H__ */
diff --git a/include/asm-arm/arch-at572d940hf/timer.h b/include/asm-arm/arch-at572d940hf/timer.h
new file mode 100644
index 0000000..8878d06
--- /dev/null
+++ b/include/asm-arm/arch-at572d940hf/timer.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Author: Antonio R. Costa
+ */
+
+#ifndef _AT91_TIMER_H_
+#define _AT91_TIMER_H_
+
+#define AT91_SLOW_FREQ 0
+#define AT91_MAIN_FREQ 1
+#define AT91_PLLA_FREQ 2
+#define AT91_PLLB_FREQ 3
+#define AT91_MASTER_FREQ 4
+#define AT91_SYS_FREQ 4
+#define AT91_PROC_FREQ 5
+
+extern int sys_get_freq(unsigned long mode, unsigned long *pfreq);
+
+#endif /* _AT91_TIMER_H_ */
--
1.5.4.3
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [U-Boot-Users] [PATCH 5/6] AT572D940HF-EB Support v2 (ethernet files)
2008-06-12 14:14 ` [U-Boot-Users] [PATCH 4/6] AT572D940HF-EB Support v2 (include files part 2) Antonio R. Costa
@ 2008-06-12 14:15 ` Antonio R. Costa
2008-07-05 20:38 ` [U-Boot-Users] [PATCH 4/6] AT572D940HF-EB Support v2 (include files part 2) Jean-Christophe PLAGNIOL-VILLARD
1 sibling, 0 replies; 26+ messages in thread
From: Antonio R. Costa @ 2008-06-12 14:15 UTC (permalink / raw)
To: u-boot
Signed-off-by: Antonio R. Costa <antonio.costa@atmel.com>
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index e5733f6..eb446d1 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -417,15 +417,15 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
/* choose RMII or MII mode. This depends on the board */
#ifdef CONFIG_RMII
-#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
- defined(CONFIG_AT91SAM9263)
+#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
+ defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT572D940HFEB)
macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
#else
macb_writel(macb, USRIO, 0);
#endif
#else
-#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
- defined(CONFIG_AT91SAM9263)
+#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
+ defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT572D940HFEB)
macb_writel(macb, USRIO, MACB_BIT(CLKEN));
#else
macb_writel(macb, USRIO, MACB_BIT(MII));
diff --git a/net/eth.c b/net/eth.c
index 21d1496..e782731 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -65,6 +65,7 @@ extern int atngw100_eth_initialize(bd_t *);
extern int mcffec_initialize(bd_t*);
extern int mcdmafec_initialize(bd_t*);
extern int at91sam9_eth_initialize(bd_t *);
+extern int at572d940hf_eth_initialize(bd_t *);
#ifdef CONFIG_API
extern void (*push_packet)(volatile void *, int);
@@ -292,6 +293,9 @@ int eth_initialize(bd_t *bis)
defined(CONFIG_AT91SAM9263)
at91sam9_eth_initialize(bis);
#endif
+#if defined(CONFIG_AT572D940HF)
+ at572d940hf_eth_initialize(bis);
+#endif
if (!eth_devices) {
puts ("No ethernet found.\n");
--
1.5.4.3
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [U-Boot-Users] [PATCH 1/2] AT572D940HF-EB Support v2 (SDHC support part 1)
2008-06-12 14:14 ` [U-Boot-Users] [PATCH 1/2] AT572D940HF-EB Support v2 (SDHC support part 1) Antonio R. Costa
2008-06-12 14:14 ` [U-Boot-Users] [PATCH 2/2] AT572D940HF-EB Support v2 (SDHC support part 2) Antonio R. Costa
@ 2008-06-12 16:36 ` Haavard Skinnemoen
2008-06-12 17:19 ` Ulf Samuelsson
2008-06-12 17:27 ` [U-Boot-Users] [PATCH 0/3] Move atmel_mci driver into drivers/mmc Haavard Skinnemoen
1 sibling, 2 replies; 26+ messages in thread
From: Haavard Skinnemoen @ 2008-06-12 16:36 UTC (permalink / raw)
To: u-boot
On Thu, 12 Jun 2008 16:14:56 +0200
"Antonio R. Costa" <costa.antonior@gmail.com> wrote:
> This patch add support for SD/SDHC cards to AT572D940HF-EB
> and more generally is a proposal for all Atmel chips.
> Dued to that I placed atmel_mci.c under the board directory.
It's a bit hard to see what your proposal is all about when you create
a new file instead of modifying the exising one...
> The implementation of the CSD interpretation has been re-worked
> completely. Bit fields are not portable so there were replaced by
> a vector of 4 32-bit words and some macros.
>
> Probing process follow the schema from SD spec 2.0:
> sdhc --> sd --> mmc
>
> Introduced IF_TYPE_SDHC to distinguish between SD and SDHC.
> Maybe this is not the best method since struct block_dev_descr.priv
> could point to a structure describing card properties but it was
> the quickest one and I had no time to spend.
>
> Tested SD:
> - Mediacom 512 MB (spec 1.0) bare FAT16 no partition table
> - Kingstone 1 GB (spec 1.0) 1 FAT16
> - Trascend 2 GB (spec 1.01) 1 FAT16
> - TakeMS 4 GB (spec 1.10) 1 FAT16
>
> Tested SDHC:
> - Peak 8 GB (spec 2.0) 1 FAT32
Ideally, this sort of thing should go into a common MMC layer for
u-boot. But at the very least, we should use the same driver on all
chips that feature the same hardware (other AT91 chips and AVR32).
So how about we start by introducing a new drivers/mmc directory and
move the existing AVR32 driver there? After that, you can apply your
changes to it and send a patch which clearly shows the differences from
the old code. Don't worry about breaking AVR32 -- I'll help you test it
before it gets merged upstream.
Then, after that, if someone feels up to the task, he can gather all
the different pieces together from the existing drivers and create a
common MMC layer.
Does that sound like a good plan to you?
Haavard
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot-Users] [PATCH 1/2] AT572D940HF-EB Support v2 (SDHC support part 1)
2008-06-12 16:36 ` [U-Boot-Users] [PATCH 1/2] AT572D940HF-EB Support v2 (SDHC support part 1) Haavard Skinnemoen
@ 2008-06-12 17:19 ` Ulf Samuelsson
2008-06-12 17:31 ` Haavard Skinnemoen
2008-06-13 6:38 ` Wolfgang Denk
2008-06-12 17:27 ` [U-Boot-Users] [PATCH 0/3] Move atmel_mci driver into drivers/mmc Haavard Skinnemoen
1 sibling, 2 replies; 26+ messages in thread
From: Ulf Samuelsson @ 2008-06-12 17:19 UTC (permalink / raw)
To: u-boot
Haavard Skinnemoen wrote:
> On Thu, 12 Jun 2008 16:14:56 +0200
> "Antonio R. Costa" <costa.antonior@gmail.com> wrote:
>
>> This patch add support for SD/SDHC cards to AT572D940HF-EB
>> and more generally is a proposal for all Atmel chips.
>> Dued to that I placed atmel_mci.c under the board directory.
>
> It's a bit hard to see what your proposal is all about when you create
> a new file instead of modifying the exising one...
>
If you want to see changes right now,
then just replace the existing file with the Diopsis file and do a diff.
>> The implementation of the CSD interpretation has been re-worked
>> completely. Bit fields are not portable so there were replaced by
>> a vector of 4 32-bit words and some macros.
>>
>> Probing process follow the schema from SD spec 2.0:
>> sdhc --> sd --> mmc
>>
>> Introduced IF_TYPE_SDHC to distinguish between SD and SDHC.
>> Maybe this is not the best method since struct block_dev_descr.priv
>> could point to a structure describing card properties but it was
>> the quickest one and I had no time to spend.
>>
>> Tested SD:
>> - Mediacom 512 MB (spec 1.0) bare FAT16 no partition table
>> - Kingstone 1 GB (spec 1.0) 1 FAT16
>> - Trascend 2 GB (spec 1.01) 1 FAT16
>> - TakeMS 4 GB (spec 1.10) 1 FAT16
>>
>> Tested SDHC:
>> - Peak 8 GB (spec 2.0) 1 FAT32
>
> Ideally, this sort of thing should go into a common MMC layer for
> u-boot. But at the very least, we should use the same driver on all
> chips that feature the same hardware (other AT91 chips and AVR32).
> So how about we start by introducing a new drivers/mmc directory and
> move the existing AVR32 driver there? After that, you can apply your
> changes to it and send a patch which clearly shows the differences
> from the old code. Don't worry about breaking AVR32 -- I'll help you
> test it before it gets merged upstream.
>
Why not get the Diopsis support in first, and then do the merge afterwards.
I do agree that they should be merged, but that does not mean
that delaying the availability of Diopsis support in U-Boot is a good idea.
> Then, after that, if someone feels up to the task, he can gather all
> the different pieces together from the existing drivers and create a
> common MMC layer.
>
> Does that sound like a good plan to you?
>
> Haavard
>
> -------------------------------------------------------------------------
> Check out the new SourceForge.net Marketplace.
> It's the best place to buy or sell services for
> just about anything Open Source.
> http://sourceforge.net/services/buy/index.php
> _______________________________________________
> U-Boot-Users mailing list
> U-Boot-Users at lists.sourceforge.net
> https://lists.sourceforge.net/lists/listinfo/u-boot-users
Best Regards
Ulf Samuelsson
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot-Users] [PATCH 0/3] Move atmel_mci driver into drivers/mmc
2008-06-12 16:36 ` [U-Boot-Users] [PATCH 1/2] AT572D940HF-EB Support v2 (SDHC support part 1) Haavard Skinnemoen
2008-06-12 17:19 ` Ulf Samuelsson
@ 2008-06-12 17:27 ` Haavard Skinnemoen
2008-06-12 17:27 ` [U-Boot-Users] [PATCH 1/3] Create drivers/mmc subdirectory Haavard Skinnemoen
` (2 more replies)
1 sibling, 3 replies; 26+ messages in thread
From: Haavard Skinnemoen @ 2008-06-12 17:27 UTC (permalink / raw)
To: u-boot
> So how about we start by introducing a new drivers/mmc directory and
> move the existing AVR32 driver there?
In fact, this is so incredibly easy to do with git that I decided to
just do it. The three patches posted as a follow-up to this e-mail is
the result. I've verified that it compiles and that the driver gets
included in the final image, but I haven't actually run it.
Now, if you move your modified driver into drivers/mmc and generate a
patch against this series, it will be much easier to review your
changes. And any bug fixes done on one platform will benefit all.
To use the driver, simply add "#define CONFIG_ATMEL_MCI" to your board
config file.
Shortlog and diffstat for the whole series follows.
Haavard Skinnemoen (3):
Create drivers/mmc subdirectory
avr32: Use CONFIG_ATMEL_MCI to select the atmel_mci driver
mmc: Move atmel_mci driver into drivers/mmc
Makefile | 2 +
cpu/at32ap/Makefile | 1 -
drivers/mmc/Makefile | 46 +++++++++++++++++++++++++++++++
{cpu/at32ap => drivers/mmc}/atmel_mci.c | 0
{cpu/at32ap => drivers/mmc}/atmel_mci.h | 0
include/configs/atngw100.h | 1 +
include/configs/atstk1002.h | 1 +
include/configs/atstk1003.h | 1 +
include/configs/atstk1004.h | 1 +
include/configs/atstk1006.h | 1 +
10 files changed, 53 insertions(+), 1 deletions(-)
create mode 100644 drivers/mmc/Makefile
rename {cpu/at32ap => drivers/mmc}/atmel_mci.c (100%)
rename {cpu/at32ap => drivers/mmc}/atmel_mci.h (100%)
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot-Users] [PATCH 1/3] Create drivers/mmc subdirectory
2008-06-12 17:27 ` [U-Boot-Users] [PATCH 0/3] Move atmel_mci driver into drivers/mmc Haavard Skinnemoen
@ 2008-06-12 17:27 ` Haavard Skinnemoen
2008-06-12 17:27 ` [U-Boot-Users] [PATCH 2/3] avr32: Use CONFIG_ATMEL_MCI to select the atmel_mci driver Haavard Skinnemoen
2008-07-09 22:02 ` [U-Boot-Users] [PATCH 1/3] Create drivers/mmc subdirectory Wolfgang Denk
2008-07-05 17:01 ` [U-Boot-Users] [PATCH 0/3] Move atmel_mci driver into drivers/mmc Jean-Christophe PLAGNIOL-VILLARD
2008-07-05 22:32 ` Wolfgang Denk
2 siblings, 2 replies; 26+ messages in thread
From: Haavard Skinnemoen @ 2008-06-12 17:27 UTC (permalink / raw)
To: u-boot
In order to consolidate more of the various MMC drivers around the
tree, we must first have a common place to put them.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
---
Makefile | 2 ++
drivers/mmc/Makefile | 44 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 46 insertions(+), 0 deletions(-)
create mode 100644 drivers/mmc/Makefile
diff --git a/Makefile b/Makefile
index 8bfc891..33e45b8 100644
--- a/Makefile
+++ b/Makefile
@@ -220,6 +220,7 @@ LIBS += drivers/hwmon/libhwmon.a
LIBS += drivers/i2c/libi2c.a
LIBS += drivers/input/libinput.a
LIBS += drivers/misc/libmisc.a
+LIBS += drivers/mmc/libmmc.a
LIBS += drivers/mtd/libmtd.a
LIBS += drivers/mtd/nand/libnand.a
LIBS += drivers/mtd/nand_legacy/libnand_legacy.a
@@ -387,6 +388,7 @@ TAG_SUBDIRS += drivers/hwmon
TAG_SUBDIRS += drivers/i2c
TAG_SUBDIRS += drivers/input
TAG_SUBDIRS += drivers/misc
+TAG_SUBDIRS += drivers/mmc
TAG_SUBDIRS += drivers/mtd
TAG_SUBDIRS += drivers/mtd/nand
TAG_SUBDIRS += drivers/mtd/nand_legacy
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
new file mode 100644
index 0000000..db92424
--- /dev/null
+++ b/drivers/mmc/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB := $(obj)libmmc.a
+
+COBJS := $(COBJS-y)
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+all: $(LIB)
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--
1.5.4.3
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [U-Boot-Users] [PATCH 2/3] avr32: Use CONFIG_ATMEL_MCI to select the atmel_mci driver
2008-06-12 17:27 ` [U-Boot-Users] [PATCH 1/3] Create drivers/mmc subdirectory Haavard Skinnemoen
@ 2008-06-12 17:27 ` Haavard Skinnemoen
2008-06-12 17:27 ` [U-Boot-Users] [PATCH 3/3] mmc: Move atmel_mci driver into drivers/mmc Haavard Skinnemoen
2008-07-09 22:05 ` [U-Boot-Users] [PATCH 2/3] avr32: Use CONFIG_ATMEL_MCI to select the atmel_mci driver Wolfgang Denk
2008-07-09 22:02 ` [U-Boot-Users] [PATCH 1/3] Create drivers/mmc subdirectory Wolfgang Denk
1 sibling, 2 replies; 26+ messages in thread
From: Haavard Skinnemoen @ 2008-06-12 17:27 UTC (permalink / raw)
To: u-boot
After we move the atmel_mci driver into drivers/mmc, we can't select
it with CONFIG_MMC anymore. Introduce a new symbol specifically for
this driver so that there's no ambiguity.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
---
cpu/at32ap/Makefile | 2 +-
include/configs/atngw100.h | 1 +
include/configs/atstk1002.h | 1 +
include/configs/atstk1003.h | 1 +
include/configs/atstk1004.h | 1 +
include/configs/atstk1006.h | 1 +
6 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/cpu/at32ap/Makefile b/cpu/at32ap/Makefile
index d16c58b..f182330 100644
--- a/cpu/at32ap/Makefile
+++ b/cpu/at32ap/Makefile
@@ -35,7 +35,7 @@ COBJS-y += exception.o
COBJS-y += cache.o
COBJS-y += interrupts.o
COBJS-y += pio.o
-COBJS-$(CONFIG_MMC) += atmel_mci.o
+COBJS-$(CONFIG_ATMEL_MCI) += atmel_mci.o
SRCS := $(START-y:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h
index 3fc9975..4c995ea 100644
--- a/include/configs/atngw100.h
+++ b/include/configs/atngw100.h
@@ -126,6 +126,7 @@
#define CFG_NR_PIOS 5
#define CFG_HSDRAMC 1
#define CONFIG_MMC 1
+#define CONFIG_ATMEL_MCI 1
#define CFG_DCACHE_LINESZ 32
#define CFG_ICACHE_LINESZ 32
diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h
index ba18eb6..90910bb 100644
--- a/include/configs/atstk1002.h
+++ b/include/configs/atstk1002.h
@@ -153,6 +153,7 @@
#define CFG_NR_PIOS 5
#define CFG_HSDRAMC 1
#define CONFIG_MMC 1
+#define CONFIG_ATMEL_MCI 1
#define CFG_DCACHE_LINESZ 32
#define CFG_ICACHE_LINESZ 32
diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h
index a528ddf..03472a8 100644
--- a/include/configs/atstk1003.h
+++ b/include/configs/atstk1003.h
@@ -136,6 +136,7 @@
#define CONFIG_PIO2 1
#define CFG_HSDRAMC 1
#define CONFIG_MMC 1
+#define CONFIG_ATMEL_MCI 1
#define CFG_DCACHE_LINESZ 32
#define CFG_ICACHE_LINESZ 32
diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h
index fc9585e..07add82 100644
--- a/include/configs/atstk1004.h
+++ b/include/configs/atstk1004.h
@@ -136,6 +136,7 @@
#define CONFIG_PIO2 1
#define CFG_HSDRAMC 1
#define CONFIG_MMC 1
+#define CONFIG_ATMEL_MCI 1
#define CFG_DCACHE_LINESZ 32
#define CFG_ICACHE_LINESZ 32
diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h
index 9fd49a5..f9af675 100644
--- a/include/configs/atstk1006.h
+++ b/include/configs/atstk1006.h
@@ -153,6 +153,7 @@
#define CFG_NR_PIOS 5
#define CFG_HSDRAMC 1
#define CONFIG_MMC 1
+#define CONFIG_ATMEL_MCI 1
#define CFG_DCACHE_LINESZ 32
#define CFG_ICACHE_LINESZ 32
--
1.5.4.3
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [U-Boot-Users] [PATCH 3/3] mmc: Move atmel_mci driver into drivers/mmc
2008-06-12 17:27 ` [U-Boot-Users] [PATCH 2/3] avr32: Use CONFIG_ATMEL_MCI to select the atmel_mci driver Haavard Skinnemoen
@ 2008-06-12 17:27 ` Haavard Skinnemoen
2008-07-09 22:06 ` Wolfgang Denk
2008-07-09 22:05 ` [U-Boot-Users] [PATCH 2/3] avr32: Use CONFIG_ATMEL_MCI to select the atmel_mci driver Wolfgang Denk
1 sibling, 1 reply; 26+ messages in thread
From: Haavard Skinnemoen @ 2008-06-12 17:27 UTC (permalink / raw)
To: u-boot
This makes it easier to use the driver on other platforms.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
---
cpu/at32ap/Makefile | 1 -
drivers/mmc/Makefile | 2 ++
{cpu/at32ap => drivers/mmc}/atmel_mci.c | 0
{cpu/at32ap => drivers/mmc}/atmel_mci.h | 0
4 files changed, 2 insertions(+), 1 deletions(-)
rename {cpu/at32ap => drivers/mmc}/atmel_mci.c (100%)
rename {cpu/at32ap => drivers/mmc}/atmel_mci.h (100%)
diff --git a/cpu/at32ap/Makefile b/cpu/at32ap/Makefile
index f182330..33dc427 100644
--- a/cpu/at32ap/Makefile
+++ b/cpu/at32ap/Makefile
@@ -35,7 +35,6 @@ COBJS-y += exception.o
COBJS-y += cache.o
COBJS-y += interrupts.o
COBJS-y += pio.o
-COBJS-$(CONFIG_ATMEL_MCI) += atmel_mci.o
SRCS := $(START-y:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index db92424..3dc031b 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -25,6 +25,8 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libmmc.a
+COBJS-$(CONFIG_ATMEL_MCI) += atmel_mci.o
+
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/cpu/at32ap/atmel_mci.c b/drivers/mmc/atmel_mci.c
similarity index 100%
rename from cpu/at32ap/atmel_mci.c
rename to drivers/mmc/atmel_mci.c
diff --git a/cpu/at32ap/atmel_mci.h b/drivers/mmc/atmel_mci.h
similarity index 100%
rename from cpu/at32ap/atmel_mci.h
rename to drivers/mmc/atmel_mci.h
--
1.5.4.3
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [U-Boot-Users] [PATCH 1/2] AT572D940HF-EB Support v2 (SDHC support part 1)
2008-06-12 17:19 ` Ulf Samuelsson
@ 2008-06-12 17:31 ` Haavard Skinnemoen
2008-06-12 19:49 ` Ulf Samuelsson
2008-06-13 6:38 ` Wolfgang Denk
1 sibling, 1 reply; 26+ messages in thread
From: Haavard Skinnemoen @ 2008-06-12 17:31 UTC (permalink / raw)
To: u-boot
On Thu, 12 Jun 2008 19:19:47 +0200
"Ulf Samuelsson" <ulf.samuelsson@atmel.com> wrote:
> Haavard Skinnemoen wrote:
> > It's a bit hard to see what your proposal is all about when you create
> > a new file instead of modifying the exising one...
> >
>
> If you want to see changes right now,
> then just replace the existing file with the Diopsis file and do a diff.
The whole idea about e-mail review is that someone posts a patch and
someone else reviews it.
> > So how about we start by introducing a new drivers/mmc directory and
> > move the existing AVR32 driver there? After that, you can apply your
> > changes to it and send a patch which clearly shows the differences
> > from the old code. Don't worry about breaking AVR32 -- I'll help you
> > test it before it gets merged upstream.
> >
>
> Why not get the Diopsis support in first, and then do the merge afterwards.
> I do agree that they should be merged, but that does not mean
> that delaying the availability of Diopsis support in U-Boot is a good idea.
I disagree. Why do a half-assed job when you can do it properly?
Besides, the merge window is closed now, isn't it? So we have lots of
time to review and test things before the next merge window.
Haavard
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot-Users] [PATCH 1/2] AT572D940HF-EB Support v2 (SDHC support part 1)
2008-06-12 17:31 ` Haavard Skinnemoen
@ 2008-06-12 19:49 ` Ulf Samuelsson
0 siblings, 0 replies; 26+ messages in thread
From: Ulf Samuelsson @ 2008-06-12 19:49 UTC (permalink / raw)
To: u-boot
Haavard Skinnemoen wrote:
> On Thu, 12 Jun 2008 19:19:47 +0200
> "Ulf Samuelsson" <ulf.samuelsson@atmel.com> wrote:
>
>> Haavard Skinnemoen wrote:
>>> It's a bit hard to see what your proposal is all about when you
>>> create a new file instead of modifying the exising one...
>>>
>>
>> If you want to see changes right now,
>> then just replace the existing file with the Diopsis file and do a
>> diff.
>
> The whole idea about e-mail review is that someone posts a patch and
> someone else reviews it.
>>> So how about we start by introducing a new drivers/mmc directory and
>>> move the existing AVR32 driver there? After that, you can apply your
>>> changes to it and send a patch which clearly shows the differences
>>> from the old code. Don't worry about breaking AVR32 -- I'll help you
>>> test it before it gets merged upstream.
>>>
>>
>> Why not get the Diopsis support in first, and then do the merge
>> afterwards. I do agree that they should be merged, but that does not
>> mean
>> that delaying the availability of Diopsis support in U-Boot is a
>> good idea.
>
> I disagree. Why do a half-assed job when you can do it properly?
Some times half-assed jobs, are good enough, and if you concentrate
all your efforts on one parts, then everything else suffers.
Currently the Diopsis configuration does not support environment variables,
and I much rather have Antonio spend time on fixing that problem,
than merging the MCI support.
Either by using the onboard parallel flash (which is complicated
since it is 2 x 16 bit AT45BV64x chips in a by 32 configuration).
I am really unsure U-boot supports this...
Or figures out a way to read/write the environment from/to the SD-Card.
While the duplication is unfortunate, the end user will not suffer too much
compared to not having environment variables.
> Besides, the merge window is closed now, isn't it? So we have lots of
> time to review and test things before the next merge window.
>
> Haavard
Best Regards
Ulf Samuelsson
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot-Users] [PATCH 1/2] AT572D940HF-EB Support v2 (SDHC support part 1)
2008-06-12 17:19 ` Ulf Samuelsson
2008-06-12 17:31 ` Haavard Skinnemoen
@ 2008-06-13 6:38 ` Wolfgang Denk
2008-06-13 7:18 ` Ulf Samuelsson
2008-07-05 16:58 ` Jean-Christophe PLAGNIOL-VILLARD
1 sibling, 2 replies; 26+ messages in thread
From: Wolfgang Denk @ 2008-06-13 6:38 UTC (permalink / raw)
To: u-boot
In message <005801c8ccb1$1cd66730$0c0514ac@atmel.com> you wrote:
>
> If you want to see changes right now,
> then just replace the existing file with the Diopsis file and do a diff.
No, this is not the way we work. We submit patches that can be
reviewed, not chunks of code that the reviewer has to anayze with
additional, unnecessary efforts.
> Why not get the Diopsis support in first, and then do the merge afterwards.
Because this is NOT the way it works.
Please stick to the established rules.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Whom the gods would destroy, they first teach BASIC.
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot-Users] [PATCH 1/2] AT572D940HF-EB Support v2 (SDHC support part 1)
2008-06-13 6:38 ` Wolfgang Denk
@ 2008-06-13 7:18 ` Ulf Samuelsson
2008-06-13 7:53 ` Haavard Skinnemoen
2008-07-05 16:58 ` Jean-Christophe PLAGNIOL-VILLARD
1 sibling, 1 reply; 26+ messages in thread
From: Ulf Samuelsson @ 2008-06-13 7:18 UTC (permalink / raw)
To: u-boot
Wolfgang Denk wrote:
> In message <005801c8ccb1$1cd66730$0c0514ac@atmel.com> you wrote:
>>
>> If you want to see changes right now,
>> then just replace the existing file with the Diopsis file and do a
>> diff.
>
> No, this is not the way we work. We submit patches that can be
> reviewed, not chunks of code that the reviewer has to anayze with
> additional, unnecessary efforts.
Antonio submits a working patchset which is structured in the
same manner as existing boards.
Haavard has a different goal which is important, but less urgent than other things.
>> Why not get the Diopsis support in first, and then do the merge
>> afterwards.
>
> Because this is NOT the way it works.
> Please stick to the established rules.
Which rule is you referring to?
Since Haavard wants this merge, then I suggest that Haavard takes
the existing patches from Antonio and reworks them ASAP,
testing them out on AVR32, AT91 and Diopsis, and resubmits
the patchset so that we have a working common driver
and working AT572D940DF board support.
Haavard, There is an AT572D940HF-EB in Atmel Norway,
I gave it to OJ and he should forward it to Haakan.
Do you have any AT91 boards?
>
> Best regards,
>
> Wolfgang Denk
Best Regards
Ulf Samuelsson ulf at atmel.com
Atmel Nordic AB
Mail: Box 2033, 174 02 Sundbyberg, Sweden
Visit: Kavalleriv?gen 24, 174 58 Sundbyberg, Sweden
Phone +46 (8) 441 54 22 Fax +46 (8) 441 54 29
GSM +46 (706) 22 44 57
Technical support when I am not available:
AT90 AVR Applications Group: mailto:avr at atmel.com
AT91 ARM Applications Group: mailto:at91support at atmel.com
AVR32 Applications Group mailto:avr32 at atmel.com
http://www.avrfreaks.net/; http://avr32linux.org/
http://www.at91.com/ ; http://www.linux4sam.org/
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot-Users] [PATCH 1/2] AT572D940HF-EB Support v2 (SDHC support part 1)
2008-06-13 7:18 ` Ulf Samuelsson
@ 2008-06-13 7:53 ` Haavard Skinnemoen
0 siblings, 0 replies; 26+ messages in thread
From: Haavard Skinnemoen @ 2008-06-13 7:53 UTC (permalink / raw)
To: u-boot
"Ulf Samuelsson" <ulf.samuelsson@atmel.com> wrote:
> > No, this is not the way we work. We submit patches that can be
> > reviewed, not chunks of code that the reviewer has to anayze with
> > additional, unnecessary efforts.
>
> Antonio submits a working patchset which is structured in the
> same manner as existing boards.
> Haavard has a different goal which is important, but less urgent than other things.
What the hell makes you think that your goals are so much more
important than mine (and everyone else's for that matter)?
It's much easier to get the drivers merged now rather than later. I did
actually do a quick diff and I saw at least three minor fixes reverted,
so the drivers have _already_ started diverging. Do you think they will
somehow be _more_ similar if we just keep them in the same tree for a
while?
Besides, there's a very real possibility that the drivers will never be
merged since we're all busy with other stuff.
Btw, apart from a couple of relatively minor things, I think the diff
as a whole looked very good, so that's not at all what I'm complaining
about.
> >> Why not get the Diopsis support in first, and then do the merge
> >> afterwards.
> >
> > Because this is NOT the way it works.
> > Please stick to the established rules.
>
> Which rule is you referring to?
>
> Since Haavard wants this merge, then I suggest that Haavard takes
> the existing patches from Antonio and reworks them ASAP,
> testing them out on AVR32, AT91 and Diopsis, and resubmits
> the patchset so that we have a working common driver
> and working AT572D940DF board support.
Ulf, if you keep insisting on that attitude, you'll never get anything
merged. This is _so_ not how it works.
I can certainly help Antonio get the patch into an acceptable state for
merging as well as test it on AVR32, but demanding that I set up
toolchains and test every single Atmel board out there is just totally
unreasonable.
Besides, the driver was originally written by me. Isn't it fair that
Diopsis gave something back by making it usable on more than just their
board?
Haavard
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot-Users] [PATCH 1/2] AT572D940HF-EB Support v2 (SDHC support part 1)
2008-06-13 6:38 ` Wolfgang Denk
2008-06-13 7:18 ` Ulf Samuelsson
@ 2008-07-05 16:58 ` Jean-Christophe PLAGNIOL-VILLARD
1 sibling, 0 replies; 26+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2008-07-05 16:58 UTC (permalink / raw)
To: u-boot
On 08:38 Fri 13 Jun , Wolfgang Denk wrote:
> In message <005801c8ccb1$1cd66730$0c0514ac@atmel.com> you wrote:
> >
> > If you want to see changes right now,
> > then just replace the existing file with the Diopsis file and do a diff.
>
> No, this is not the way we work. We submit patches that can be
> reviewed, not chunks of code that the reviewer has to anayze with
> additional, unnecessary efforts.
>
> > Why not get the Diopsis support in first, and then do the merge afterwards.
IMO: I could apply this patch in a testing branch but I've the same
opinion as Wolfgang and Haavard.
>
> Because this is NOT the way it works.
>
> Please stick to the established rules.
>
Best Regards,
J.
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot-Users] [PATCH 0/3] Move atmel_mci driver into drivers/mmc
2008-06-12 17:27 ` [U-Boot-Users] [PATCH 0/3] Move atmel_mci driver into drivers/mmc Haavard Skinnemoen
2008-06-12 17:27 ` [U-Boot-Users] [PATCH 1/3] Create drivers/mmc subdirectory Haavard Skinnemoen
@ 2008-07-05 17:01 ` Jean-Christophe PLAGNIOL-VILLARD
2008-07-05 22:32 ` Wolfgang Denk
2 siblings, 0 replies; 26+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2008-07-05 17:01 UTC (permalink / raw)
To: u-boot
On 19:27 Thu 12 Jun , Haavard Skinnemoen wrote:
> > So how about we start by introducing a new drivers/mmc directory and
> > move the existing AVR32 driver there?
>
> In fact, this is so incredibly easy to do with git that I decided to
> just do it. The three patches posted as a follow-up to this e-mail is
> the result. I've verified that it compiles and that the driver gets
> included in the final image, but I haven't actually run it.
>
> Now, if you move your modified driver into drivers/mmc and generate a
> patch against this series, it will be much easier to review your
> changes. And any bug fixes done on one platform will benefit all.
>
> To use the driver, simply add "#define CONFIG_ATMEL_MCI" to your board
> config file.
>
> Shortlog and diffstat for the whole series follows.
>
> Haavard Skinnemoen (3):
> Create drivers/mmc subdirectory
> avr32: Use CONFIG_ATMEL_MCI to select the atmel_mci driver
> mmc: Move atmel_mci driver into drivers/mmc
>
> Makefile | 2 +
> cpu/at32ap/Makefile | 1 -
> drivers/mmc/Makefile | 46 +++++++++++++++++++++++++++++++
> {cpu/at32ap => drivers/mmc}/atmel_mci.c | 0
> {cpu/at32ap => drivers/mmc}/atmel_mci.h | 0
> include/configs/atngw100.h | 1 +
> include/configs/atstk1002.h | 1 +
> include/configs/atstk1003.h | 1 +
> include/configs/atstk1004.h | 1 +
> include/configs/atstk1006.h | 1 +
> 10 files changed, 53 insertions(+), 1 deletions(-)
> create mode 100644 drivers/mmc/Makefile
> rename {cpu/at32ap => drivers/mmc}/atmel_mci.c (100%)
> rename {cpu/at32ap => drivers/mmc}/atmel_mci.h (100%)
Ack-by : Jean-Chritophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Best Regards,
J.
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot-Users] [PATCH 4/6] AT572D940HF-EB Support v2 (include files part 2)
2008-06-12 14:14 ` [U-Boot-Users] [PATCH 4/6] AT572D940HF-EB Support v2 (include files part 2) Antonio R. Costa
2008-06-12 14:15 ` [U-Boot-Users] [PATCH 5/6] AT572D940HF-EB Support v2 (ethernet files) Antonio R. Costa
@ 2008-07-05 20:38 ` Jean-Christophe PLAGNIOL-VILLARD
1 sibling, 0 replies; 26+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2008-07-05 20:38 UTC (permalink / raw)
To: u-boot
On 16:14 Thu 12 Jun , Antonio R. Costa wrote:
>
> Signed-off-by: Antonio R. Costa <antonio.costa@atmel.com>
>
> diff --git a/include/asm-arm/arch-at572d940hf/at572d940hf.h b/include/asm-arm/arch-at572d940hf/at572d940hf.h
> new file mode 100644
> index 0000000..53f049b
> --- /dev/null
> +++ b/include/asm-arm/arch-at572d940hf/at572d940hf.h
> @@ -0,0 +1,147 @@
> +/*
> + * include/asm-arm/arch-at91/AT572D940HFhf.h
> + *
> + * (C) 2008 Antonio R. Costa
> + *
> + * Common definitions.
> + * Based on AT572D940HFHF datasheet rev A.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#ifndef AT572D940HFHF_H
> +#define AT572D940HFHF_H
> +
> +/*
> + * Peripheral identifiers/interrupts.
> + */
> +#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
> +#define AT91_ID_SYS 1 /* System Peripherals */
> +#define AT572D940HF_ID_PIOA 2 /* Parallel IO Controller A */
> +#define AT572D940HF_ID_PIOB 3 /* Parallel IO Controller B */
> +#define AT572D940HF_ID_PIOC 4 /* Parallel IO Controller C */
> +#define AT572D940HF_ID_EMAC 5 /* Ethernet */
> +#define AT572D940HF_ID_US0 6 /* USART 0 */
> +#define AT572D940HF_ID_US1 7 /* USART 1 */
> +#define AT572D940HF_ID_US2 8 /* USART 2 */
> +#define AT572D940HF_ID_MCI 9 /* Multimedia Card Interface */
> +#define AT572D940HF_ID_UDP 10 /* USB Device Port */
> +#define AT572D940HF_ID_TWI 11 /* Two-Wire Interface */
> +#define AT572D940HF_ID_TWI0 11 /* Two-Wire Interface */
> +#define AT572D940HF_ID_SPI0 12 /* Serial Peripheral Interface 0 */
> +#define AT572D940HF_ID_SPI1 13 /* Serial Peripheral Interface 1 */
> +#define AT572D940HF_ID_SSC 14 /* Serial Synchronous Controller */
> +#define AT572D940HF_ID_SSC0 14 /* Serial Synchronous Controller */
> +#define AT572D940HF_ID_SSC1 15 /* Serial Synchronous Controller */
> +#define AT572D940HF_ID_SSC2 16 /* Serial Synchronous Controller */
> +#define AT572D940HF_ID_TC0 17 /* Timer Counter 0 */
> +#define AT572D940HF_ID_TC1 18 /* Timer Counter 1 */
> +#define AT572D940HF_ID_TC2 19 /* Timer Counter 2 */
> +#define AT572D940HF_ID_UHP 20 /* USB Host port */
> +#define AT572D940HF_ID_SSC3 21 /* Serial Synchronous Controller */
> +#define AT572D940HF_ID_TWI1 22 /* Two-Wire Interface */
> +#define AT572D940HF_ID_CAN0 23 /* CAN Controller */
> +#define AT572D940HF_ID_CAN1 24 /* CAN Controller */
> +#define AT572D940HF_ID_mHALT 25 /* mAgicV DSP halt int */
> +#define AT572D940HF_ID_mSIRQ1 26 /* mAgicV DSP SIRQ1 int */
> +#define AT572D940HF_ID_mEXC 27 /* mAgicV DSP Exception int */
> +#define AT572D940HF_ID_mEDMA 28 /* mAgicV DSP end of DMA transfer int */
> +#define AT572D940HF_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
> +#define AT572D940HF_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
> +#define AT572D940HF_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
> +
> +#define AT91_ID_US0 AT572D940HF_ID_US0
> +#define AT91_ID_US1 AT572D940HF_ID_US1
> +#define AT91_ID_US2 AT572D940HF_ID_US2
> +#define AT91_ID_US3 AT572D940HF_ID_US3
few whitespaces
> +
> +#define AT91_ID_UHP AT572D940HF_ID_UHP
> +#define AT91_PMC_UHP AT572D940HF_ID_UHP
> +
> +/*
> + * User Peripheral physical base addresses.
> + */
> +#define AT572D940HF_BASE_TCB0 0xfffa0000
> +#define AT572D940HF_BASE_TC0 0xfffa0000
> +#define AT572D940HF_BASE_TC1 0xfffa0040
> +#define AT572D940HF_BASE_TC2 0xfffa0080
> +#define AT572D940HF_BASE_UDP 0xfffa4000
> +#define AT572D940HF_BASE_MCI 0xfffa8000
> +#define AT572D940HF_BASE_TWI 0xfffac000
> +#define AT572D940HF_BASE_US0 0xfffb0000
> +#define AT572D940HF_BASE_US1 0xfffb4000
> +#define AT572D940HF_BASE_US2 0xfffb8000
> +#define AT572D940HF_BASE_SSC 0xfffbc000
> +#define AT572D940HF_BASE_ISI 0xfffc0000
> +#define AT572D940HF_BASE_EMAC 0xfffd8000
> +#define AT572D940HF_BASE_SPI0 0xfffc8000
> +#define AT572D940HF_BASE_SPI1 0xfffcc000
> +#define AT572D940HF_BASE_US3 0xfffd0000
> +#define AT572D940HF_BASE_US4 0xfffd4000
> +#define AT572D940HF_BASE_US5 0xfffd8000
> +#define AT572D940HF_BASE_TCB1 0xfffdc000
> +#define AT572D940HF_BASE_TC3 0xfffdc000
> +#define AT572D940HF_BASE_TC4 0xfffdc040
> +#define AT572D940HF_BASE_TC5 0xfffdc080
> +#define AT572D940HF_BASE_ADC 0xfffe0000
> +#define AT572D940HF_BASE_RSTC 0xfffffd00
> +#define AT91_BASE_SYS 0xffffea00
> +
> +#define AT91_BASE_EMAC AT572D940HF_BASE_EMAC
> +#define AT91_BASE_SPI AT572D940HF_BASE_SPI0
> +#define MMCI_BASE AT572D940HF_BASE_MCI
> +
> +/*
> + * System Peripherals (offset from AT91_BASE_SYS)
> + */
> +#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
> +#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
> +#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
> +#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
> +#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
> +#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
> +#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
> +#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
> +#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
> +#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
> +#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
> +#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
> +#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
> +#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
> +#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
> +#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
> +#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
> +
> +#define AT91_USART0 AT572D940HF_BASE_US0
> +#define AT91_USART1 AT572D940HF_BASE_US1
> +#define AT91_USART2 AT572D940HF_BASE_US2
> +#define AT91_USART3 AT572D940HF_BASE_US3
> +#define AT91_USART4 AT572D940HF_BASE_US4
> +#define AT91_USART5 AT572D940HF_BASE_US5
> +
> +/*
> + * Internal Memory.
> + */
> +#define AT572D940HF_ROM_BASE 0x00400000 /* Internal ROM base address */
> +#define AT572D940HF_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
> +
> +#define AT572D940HF_SRAM0_BASE 0x00100000 /* Internal SRAM 0 base address */
> +#define AT572D940HF_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (4Kb) */
> +#define AT572D940HF_SRAM1_BASE 0x00200000 /* Internal SRAM 0 base address */
> +#define AT572D940HF_SRAM1_SIZE SZ_16K /* Internal SRAM 0 size (4Kb) */
> +#define AT572D940HF_SRAM2_BASE 0x00300000 /* Internal SRAM 1 base address */
> +#define AT572D940HF_SRAM2_SIZE SZ_16K /* Internal SRAM 1 size (4Kb) */
> +
> +//SDRAM
No c++ comment please
> +#define AT572D940HF_SDRAM_BASE 0x20000000
> +
> +// USB Host
No c++ comment please
> +#define AT572D940HF_UHP_BASE 0x00500000 /* USB Host controller */
> +
> +#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */
> +#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */
> +
> +#endif
> diff --git a/include/asm-arm/arch-at572d940hf/at572d940hf_matrix.h b/include/asm-arm/arch-at572d940hf/at572d940hf_matrix.h
> new file mode 100644
> index 0000000..a8e9fec
> --- /dev/null
> +++ b/include/asm-arm/arch-at572d940hf/at572d940hf_matrix.h
> @@ -0,0 +1,78 @@
> +/*
Please adapt this file for your the at572d940hf or if its really the
same include the at91sam9260_matrix.h
> + * include/asm-arm/arch-at91/at91sam9260_matrix.h
> + *
> + * Memory Controllers (MATRIX, EBI) - System peripherals registers.
> + * Based on AT91SAM9260 datasheet revision B.
> + *
> diff --git a/include/asm-arm/arch-at572d940hf/at572d940hf_mc.h b/include/asm-arm/arch-at572d940hf/at572d940hf_mc.h
> new file mode 100644
> index 0000000..161d504
> --- /dev/null
> +++ b/include/asm-arm/arch-at572d940hf/at572d940hf_mc.h
> @@ -0,0 +1,140 @@
> +/*
Please adapt this file for your the at572d940hf or if its really the
same include the at91sam926x_mc.h
> + * include/asm-arm/arch-at91/at91sam926x_mc.h
> + *
> + * Memory Controllers (SMC, SDRAMC) - System peripherals registers.
> + * Based on AT91SAM9261 datasheet revision D.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> diff --git a/include/asm-arm/arch-at572d940hf/interrupts.h b/include/asm-arm/arch-at572d940hf/interrupts.h
> new file mode 100644
> index 0000000..71d3f5d
> --- /dev/null
> +++ b/include/asm-arm/arch-at572d940hf/interrupts.h
> @@ -0,0 +1,41 @@
> +/*
> + * include/asm-arm/arch-at572d940/at91_aic.h
> + *
> + * Copyright (C) 2008 Antonio R. Costa
> + * Copyright (C) ATMEL
> + *
> + * Advanced Interrupt Controller (AIC).
> + * Based on AT572D940 datasheet.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#ifndef __AT572D940_INTERRUPTS_H__
> +#define __AT572D940_INTERRUPTS_H__
> +
> +#include <asm/arch/at91_aic.h>
> +
> +typedef void (*irq_handler_t) (unsigned long int);
> +
some coding style issue
> +#define SET_IRQ_HANDLER(s,m,h) \
> +do { \
> + AIC_WRITE(AIC_SMR(s),m); \
> + AIC_WRITE(AIC_SVR(s),h); \
> + AIC_WRITE(AIC_IECR,(1<<s)); \
> +} while(0)
> +
> +#define RESET_IRQ_HANDLER(s) \
> +do { \
> + AIC_WRITE(AIC_SMR(s),0); \
> + AIC_WRITE(AIC_SVR(s),0); \
> + AIC_WRITE(AIC_IDCR,(1<<s)); \
> +} while(0)
> +
> +#define IRQ_ACKNOWLEDGE(n) AIC_WRITE(AIC_EOICR,(n))
> +
> +extern reset_irqs(void);
> +
Best Regards,
J.
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot-Users] [PATCH 0/3] Move atmel_mci driver into drivers/mmc
2008-06-12 17:27 ` [U-Boot-Users] [PATCH 0/3] Move atmel_mci driver into drivers/mmc Haavard Skinnemoen
2008-06-12 17:27 ` [U-Boot-Users] [PATCH 1/3] Create drivers/mmc subdirectory Haavard Skinnemoen
2008-07-05 17:01 ` [U-Boot-Users] [PATCH 0/3] Move atmel_mci driver into drivers/mmc Jean-Christophe PLAGNIOL-VILLARD
@ 2008-07-05 22:32 ` Wolfgang Denk
2008-07-06 12:01 ` Haavard Skinnemoen
2 siblings, 1 reply; 26+ messages in thread
From: Wolfgang Denk @ 2008-07-05 22:32 UTC (permalink / raw)
To: u-boot
In message <1213291678-31022-1-git-send-email-haavard.skinnemoen@atmel.com> you wrote:
> > So how about we start by introducing a new drivers/mmc directory and
> > move the existing AVR32 driver there?
>
> In fact, this is so incredibly easy to do with git that I decided to
> just do it. The three patches posted as a follow-up to this e-mail is
> the result. I've verified that it compiles and that the driver gets
> included in the final image, but I haven't actually run it.
>
> Now, if you move your modified driver into drivers/mmc and generate a
> patch against this series, it will be much easier to review your
> changes. And any bug fixes done on one platform will benefit all.
>
> To use the driver, simply add "#define CONFIG_ATMEL_MCI" to your board
> config file.
>
> Shortlog and diffstat for the whole series follows.
>
> Haavard Skinnemoen (3):
> Create drivers/mmc subdirectory
> avr32: Use CONFIG_ATMEL_MCI to select the atmel_mci driver
> mmc: Move atmel_mci driver into drivers/mmc
>
> Makefile | 2 +
> cpu/at32ap/Makefile | 1 -
> drivers/mmc/Makefile | 46 +++++++++++++++++++++++++++++++
> {cpu/at32ap => drivers/mmc}/atmel_mci.c | 0
> {cpu/at32ap => drivers/mmc}/atmel_mci.h | 0
> include/configs/atngw100.h | 1 +
> include/configs/atstk1002.h | 1 +
> include/configs/atstk1003.h | 1 +
> include/configs/atstk1004.h | 1 +
> include/configs/atstk1006.h | 1 +
> 10 files changed, 53 insertions(+), 1 deletions(-)
> create mode 100644 drivers/mmc/Makefile
> rename {cpu/at32ap => drivers/mmc}/atmel_mci.c (100%)
> rename {cpu/at32ap => drivers/mmc}/atmel_mci.h (100%)
Will you apply this in your repo and send me a pull request, or do you
want me to pick this up directly?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Anyone who knows history, particularly the history of Europe, will, I
think, recognize that the domination of education or of government by
any one particular religious faith is never a happy arrangement for
the people. - Eleanor Roosevelt
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot-Users] [PATCH 0/3] Move atmel_mci driver into drivers/mmc
2008-07-05 22:32 ` Wolfgang Denk
@ 2008-07-06 12:01 ` Haavard Skinnemoen
0 siblings, 0 replies; 26+ messages in thread
From: Haavard Skinnemoen @ 2008-07-06 12:01 UTC (permalink / raw)
To: u-boot
On Sun, 06 Jul 2008 00:32:03 +0200
Wolfgang Denk <wd@denx.de> wrote:
> Will you apply this in your repo and send me a pull request, or do you
> want me to pick this up directly?
Please pick it up directly. I'm on vacation, so it may take some time
before I get around to pushing it anywhere.
Haavard
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot-Users] [PATCH 1/3] Create drivers/mmc subdirectory
2008-06-12 17:27 ` [U-Boot-Users] [PATCH 1/3] Create drivers/mmc subdirectory Haavard Skinnemoen
2008-06-12 17:27 ` [U-Boot-Users] [PATCH 2/3] avr32: Use CONFIG_ATMEL_MCI to select the atmel_mci driver Haavard Skinnemoen
@ 2008-07-09 22:02 ` Wolfgang Denk
1 sibling, 0 replies; 26+ messages in thread
From: Wolfgang Denk @ 2008-07-09 22:02 UTC (permalink / raw)
To: u-boot
In message <1213291678-31022-2-git-send-email-haavard.skinnemoen@atmel.com> you wrote:
> In order to consolidate more of the various MMC drivers around the
> tree, we must first have a common place to put them.
>
> Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
> ---
> Makefile | 2 ++
> drivers/mmc/Makefile | 44 ++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 46 insertions(+), 0 deletions(-)
> create mode 100644 drivers/mmc/Makefile
Applied, thanks.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
An optimist believes we live in the best world possible; a pessimist
fears this is true.
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot-Users] [PATCH 2/3] avr32: Use CONFIG_ATMEL_MCI to select the atmel_mci driver
2008-06-12 17:27 ` [U-Boot-Users] [PATCH 2/3] avr32: Use CONFIG_ATMEL_MCI to select the atmel_mci driver Haavard Skinnemoen
2008-06-12 17:27 ` [U-Boot-Users] [PATCH 3/3] mmc: Move atmel_mci driver into drivers/mmc Haavard Skinnemoen
@ 2008-07-09 22:05 ` Wolfgang Denk
2008-07-10 10:20 ` Haavard Skinnemoen
1 sibling, 1 reply; 26+ messages in thread
From: Wolfgang Denk @ 2008-07-09 22:05 UTC (permalink / raw)
To: u-boot
In message <1213291678-31022-3-git-send-email-haavard.skinnemoen@atmel.com> you wrote:
> After we move the atmel_mci driver into drivers/mmc, we can't select
> it with CONFIG_MMC anymore. Introduce a new symbol specifically for
> this driver so that there's no ambiguity.
>
> Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
> ---
> cpu/at32ap/Makefile | 2 +-
> include/configs/atngw100.h | 1 +
> include/configs/atstk1002.h | 1 +
> include/configs/atstk1003.h | 1 +
> include/configs/atstk1004.h | 1 +
> include/configs/atstk1006.h | 1 +
> 6 files changed, 6 insertions(+), 1 deletions(-)
Applied, with a merge conflict include/configs/atngw100.h; please
check the result. Thanks.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
They weren't that important. They were merely at the top. The people
who really run organizations are usually found several levels down,
where it's still possible to get things done.
- Terry Pratchett, _Small Gods_
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot-Users] [PATCH 3/3] mmc: Move atmel_mci driver into drivers/mmc
2008-06-12 17:27 ` [U-Boot-Users] [PATCH 3/3] mmc: Move atmel_mci driver into drivers/mmc Haavard Skinnemoen
@ 2008-07-09 22:06 ` Wolfgang Denk
0 siblings, 0 replies; 26+ messages in thread
From: Wolfgang Denk @ 2008-07-09 22:06 UTC (permalink / raw)
To: u-boot
In message <1213291678-31022-4-git-send-email-haavard.skinnemoen@atmel.com> you wrote:
> This makes it easier to use the driver on other platforms.
>
> Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
> ---
> cpu/at32ap/Makefile | 1 -
> drivers/mmc/Makefile | 2 ++
> {cpu/at32ap => drivers/mmc}/atmel_mci.c | 0
> {cpu/at32ap => drivers/mmc}/atmel_mci.h | 0
> 4 files changed, 2 insertions(+), 1 deletions(-)
> rename {cpu/at32ap => drivers/mmc}/atmel_mci.c (100%)
> rename {cpu/at32ap => drivers/mmc}/atmel_mci.h (100%)
Applied, thanks.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"The greatest warriors are the ones who fight for peace."
- Holly Near
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot-Users] [PATCH 2/3] avr32: Use CONFIG_ATMEL_MCI to select the atmel_mci driver
2008-07-09 22:05 ` [U-Boot-Users] [PATCH 2/3] avr32: Use CONFIG_ATMEL_MCI to select the atmel_mci driver Wolfgang Denk
@ 2008-07-10 10:20 ` Haavard Skinnemoen
0 siblings, 0 replies; 26+ messages in thread
From: Haavard Skinnemoen @ 2008-07-10 10:20 UTC (permalink / raw)
To: u-boot
On Thu, 10 Jul 2008 00:05:27 +0200
Wolfgang Denk <wd@denx.de> wrote:
> Applied, with a merge conflict include/configs/atngw100.h; please
> check the result. Thanks.
Looks good to me. Thanks.
Ho-hum...a default ATNGW100 build seems to have gone from 0 warnings to
around 20 quite recently. I'll have a look at that when I get back from
vacation.
Haavard
^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2008-07-10 10:20 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2008-06-12 14:14 [U-Boot-Users] [PATCH 1/6] AT572D940HF-EB Support v2 (board folder) Antonio R. Costa
2008-06-12 14:14 ` [U-Boot-Users] [PATCH 1/2] AT572D940HF-EB Support v2 (SDHC support part 1) Antonio R. Costa
2008-06-12 14:14 ` [U-Boot-Users] [PATCH 2/2] AT572D940HF-EB Support v2 (SDHC support part 2) Antonio R. Costa
2008-06-12 14:14 ` [U-Boot-Users] [PATCH 3/6] AT572D940HF-EB Support v2 (include files part 1) Antonio R. Costa
2008-06-12 14:14 ` [U-Boot-Users] [PATCH 4/6] AT572D940HF-EB Support v2 (include files part 2) Antonio R. Costa
2008-06-12 14:15 ` [U-Boot-Users] [PATCH 5/6] AT572D940HF-EB Support v2 (ethernet files) Antonio R. Costa
2008-07-05 20:38 ` [U-Boot-Users] [PATCH 4/6] AT572D940HF-EB Support v2 (include files part 2) Jean-Christophe PLAGNIOL-VILLARD
2008-06-12 16:36 ` [U-Boot-Users] [PATCH 1/2] AT572D940HF-EB Support v2 (SDHC support part 1) Haavard Skinnemoen
2008-06-12 17:19 ` Ulf Samuelsson
2008-06-12 17:31 ` Haavard Skinnemoen
2008-06-12 19:49 ` Ulf Samuelsson
2008-06-13 6:38 ` Wolfgang Denk
2008-06-13 7:18 ` Ulf Samuelsson
2008-06-13 7:53 ` Haavard Skinnemoen
2008-07-05 16:58 ` Jean-Christophe PLAGNIOL-VILLARD
2008-06-12 17:27 ` [U-Boot-Users] [PATCH 0/3] Move atmel_mci driver into drivers/mmc Haavard Skinnemoen
2008-06-12 17:27 ` [U-Boot-Users] [PATCH 1/3] Create drivers/mmc subdirectory Haavard Skinnemoen
2008-06-12 17:27 ` [U-Boot-Users] [PATCH 2/3] avr32: Use CONFIG_ATMEL_MCI to select the atmel_mci driver Haavard Skinnemoen
2008-06-12 17:27 ` [U-Boot-Users] [PATCH 3/3] mmc: Move atmel_mci driver into drivers/mmc Haavard Skinnemoen
2008-07-09 22:06 ` Wolfgang Denk
2008-07-09 22:05 ` [U-Boot-Users] [PATCH 2/3] avr32: Use CONFIG_ATMEL_MCI to select the atmel_mci driver Wolfgang Denk
2008-07-10 10:20 ` Haavard Skinnemoen
2008-07-09 22:02 ` [U-Boot-Users] [PATCH 1/3] Create drivers/mmc subdirectory Wolfgang Denk
2008-07-05 17:01 ` [U-Boot-Users] [PATCH 0/3] Move atmel_mci driver into drivers/mmc Jean-Christophe PLAGNIOL-VILLARD
2008-07-05 22:32 ` Wolfgang Denk
2008-07-06 12:01 ` Haavard Skinnemoen
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