[U-Boot-Users] [PATCH] PPC4xx: Correct SDRAM_MCSTAT for PPC405EX(r)

[Stefan Roese <sr@denx.de>]

On Wednesday 09 July 2008, Grant Erickson wrote:
> While the PowerPC 405EX(r) shares in common the AMCC/IBM DDR2 SDRAM
> controller core also used in the 440SP, 440SPe, 460EX, and 460GT, in
> the 405EX(r), SDRAM_MCSTAT has a different DCR value.
>
> Its present value on the 405EX(r) causes a read back of 0xFFFFFFFF
> which causes SDRAM initialization to periodically fail since it can
> prematurely indicate SDRAM ready status.
>
> Signed-off-by: Grant Erickson <gerickson@nuovations.com>
> ---
>  include/asm-ppc/ppc4xx-sdram.h |    3 +++
>  1 files changed, 3 insertions(+), 0 deletions(-)
>
> diff --git a/include/asm-ppc/ppc4xx-sdram.h
> b/include/asm-ppc/ppc4xx-sdram.h index 8a064df..5cf5ce3 100644
> --- a/include/asm-ppc/ppc4xx-sdram.h
> +++ b/include/asm-ppc/ppc4xx-sdram.h
> @@ -353,7 +353,10 @@
>  /*
>   * Memory controller registers
>   */
> +#ifndef CONFIG_405EX
>  #define SDRAM_MCSTAT	0x14	/* memory controller status                  */
> +#else
> +#define SDRAM_MCSTAT	0x1F	/* memory controller status                  */
>  #define SDRAM_MCOPT1	0x20	/* memory controller options 1               */
>  #define SDRAM_MCOPT2	0x21	/* memory controller options 2               */
>  #define SDRAM_MODT0	0x22	/* on die termination for bank 0             */

Isn't an #endif missing here?

Best regards,
Stefan

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