From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefan Roese Date: Fri, 11 Jul 2008 13:23:35 +0200 Subject: [U-Boot-Users] [PATCH v2] PPC4xx: Correct SDRAM_MCSTAT for PPC405EX(r) In-Reply-To: <1215629746-9571-1-git-send-email-gerickson@nuovations.com> References: <1215629746-9571-1-git-send-email-gerickson@nuovations.com> Message-ID: <200807111323.35731.sr@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Wednesday 09 July 2008, Grant Erickson wrote: > While the PowerPC 405EX(r) shares in common the AMCC/IBM DDR2 SDRAM > controller core also used in the 440SP, 440SPe, 460EX, and 460GT, in > the 405EX(r), SDRAM_MCSTAT has a different DCR value. > > Its present value on the 405EX(r) causes a read back of 0xFFFFFFFF > which causes SDRAM initialization to periodically fail since it can > prematurely indicate SDRAM ready status. > > Signed-off-by: Grant Erickson Applied to "next" branch in u-boot-ppc4xx repository. Thanks. Best regards, Stefan ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de =====================================================================