[U-Boot-Users] [PATCH] PPC4xx: Memory Queue Optimizations for PPC460EX/GT

public inbox for u-boot@lists.denx.de
 help / color / mirror / Atom feed

* [U-Boot-Users] [PATCH] PPC4xx: Memory Queue Optimizations for PPC460EX/GT
@ 2008-08-06 22:27 Prodyut Hazarika
  2008-08-07 10:18 ` Stefan Roese
  0 siblings, 1 reply; 3+ messages in thread
From: Prodyut Hazarika @ 2008-08-06 22:27 UTC (permalink / raw)
  To: u-boot


Set PL44 Arbiter Read pipeline depth to 4
Optimize Memory Queue Configuration registers for PPC460EX/GT

Signed-off-by: Prodyut Hazarika <phazarika@amcc.com>
---
 board/amcc/canyonlands/canyonlands.c |    9 +++
 cpu/ppc4xx/44x_spd_ddr2.c            |    4 +
 include/ppc440.h                     |  101 ++++++++++++++++++----------------
 3 files changed, 66 insertions(+), 48 deletions(-)

diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index e9eba49..dd285bc 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -113,6 +113,15 @@ int board_early_init_f(void)
 	mtdcr(AHB_TOP, 0x8000004B);
 	mtdcr(AHB_BOT, 0x8000004B);
 
+	mtdcr(plb0_acr, plb0_acr_ppm_fair    | 
+			plb0_acr_hbu_enabled |
+			plb0_acr_rdp_4deep   | 
+			plb0_acr_wrp_2deep);
+	mtdcr(plb1_acr, plb1_acr_ppm_fair    | 
+			plb1_acr_hbu_enabled |
+			plb1_acr_rdp_4deep   | 
+			plb1_acr_wrp_2deep);
+
 	if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) {
 		/*
 		 * Configure USB-STP pins as alternate and not GPIO
diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index e9940e8..c222507 100644
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -2251,6 +2251,10 @@ static void program_memory_queue(unsigned long *dimm_populated,
 	 */
 	mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
 	mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
+
+	mtdcr(SDRAM_CONF1HB, 0x80001c80); 
+	mtdcr(SDRAM_CONF1LL, 0x80001c80); 
+	mtdcr(SDRAM_CONFPATHB, 0x18a68000); 
 #endif
 }
 
diff --git a/include/ppc440.h b/include/ppc440.h
index c581f1b..650ee4f 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -422,53 +422,6 @@
 
 #define PLB4_ACR_WRP		(0x80000000 >> 7)
 
-/* Nebula PLB4 Arbiter - PowerPC440EP */
-#define PLB_ARBITER_BASE   0x80
-
-#define plb0_revid                (PLB_ARBITER_BASE+ 0x00)
-#define plb0_acr                  (PLB_ARBITER_BASE+ 0x01)
-#define   plb0_acr_ppm_mask             0xF0000000
-#define   plb0_acr_ppm_fixed            0x00000000
-#define   plb0_acr_ppm_fair             0xD0000000
-#define   plb0_acr_hbu_mask             0x08000000
-#define   plb0_acr_hbu_disabled         0x00000000
-#define   plb0_acr_hbu_enabled          0x08000000
-#define   plb0_acr_rdp_mask             0x06000000
-#define   plb0_acr_rdp_disabled         0x00000000
-#define   plb0_acr_rdp_2deep            0x02000000
-#define   plb0_acr_rdp_3deep            0x04000000
-#define   plb0_acr_rdp_4deep            0x06000000
-#define   plb0_acr_wrp_mask             0x01000000
-#define   plb0_acr_wrp_disabled         0x00000000
-#define   plb0_acr_wrp_2deep            0x01000000
-
-#define plb0_besrl                (PLB_ARBITER_BASE+ 0x02)
-#define plb0_besrh                (PLB_ARBITER_BASE+ 0x03)
-#define plb0_bearl                (PLB_ARBITER_BASE+ 0x04)
-#define plb0_bearh                (PLB_ARBITER_BASE+ 0x05)
-#define plb0_ccr                  (PLB_ARBITER_BASE+ 0x08)
-
-#define plb1_acr                  (PLB_ARBITER_BASE+ 0x09)
-#define   plb1_acr_ppm_mask             0xF0000000
-#define   plb1_acr_ppm_fixed            0x00000000
-#define   plb1_acr_ppm_fair             0xD0000000
-#define   plb1_acr_hbu_mask             0x08000000
-#define   plb1_acr_hbu_disabled         0x00000000
-#define   plb1_acr_hbu_enabled          0x08000000
-#define   plb1_acr_rdp_mask             0x06000000
-#define   plb1_acr_rdp_disabled         0x00000000
-#define   plb1_acr_rdp_2deep            0x02000000
-#define   plb1_acr_rdp_3deep            0x04000000
-#define   plb1_acr_rdp_4deep            0x06000000
-#define   plb1_acr_wrp_mask             0x01000000
-#define   plb1_acr_wrp_disabled         0x00000000
-#define   plb1_acr_wrp_2deep            0x01000000
-
-#define plb1_besrl                (PLB_ARBITER_BASE+ 0x0A)
-#define plb1_besrh                (PLB_ARBITER_BASE+ 0x0B)
-#define plb1_bearl                (PLB_ARBITER_BASE+ 0x0C)
-#define plb1_bearh                (PLB_ARBITER_BASE+ 0x0D)
-
 /* Pin Function Control Register 1 */
 #define SDR0_PFC1                    0x4101
 #define   SDR0_PFC1_U1ME_MASK         0x02000000    /* UART1 Mode Enable */
@@ -742,7 +695,59 @@
 #define   SDR0_PFC1_PLB_PME_PLB4_SEL  0x00001000      /* PLB3 Performance Monitor Enable */
 #define   SDR0_PFC1_GFGGI_MASK        0x0000000F    /* GPT Frequency Generation Gated In */
 
-#endif /* 440EP || 440GR || 440EPX || 440GRX */
+#endif  /* 440EP || 440GR || 440EPX || 440GRX */
+
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+
+#define PLB_ARBITER_BASE   0x80
+
+#define plb0_revid                (PLB_ARBITER_BASE+ 0x00)
+#define plb0_acr                  (PLB_ARBITER_BASE+ 0x01)
+#define   plb0_acr_ppm_mask             0xF0000000
+#define   plb0_acr_ppm_fixed            0x00000000
+#define   plb0_acr_ppm_fair             0xD0000000
+#define   plb0_acr_hbu_mask             0x08000000
+#define   plb0_acr_hbu_disabled         0x00000000
+#define   plb0_acr_hbu_enabled          0x08000000
+#define   plb0_acr_rdp_mask             0x06000000
+#define   plb0_acr_rdp_disabled         0x00000000
+#define   plb0_acr_rdp_2deep            0x02000000
+#define   plb0_acr_rdp_3deep            0x04000000
+#define   plb0_acr_rdp_4deep            0x06000000
+#define   plb0_acr_wrp_mask             0x01000000
+#define   plb0_acr_wrp_disabled         0x00000000
+#define   plb0_acr_wrp_2deep            0x01000000
+
+#define plb0_besrl                (PLB_ARBITER_BASE+ 0x02)
+#define plb0_besrh                (PLB_ARBITER_BASE+ 0x03)
+#define plb0_bearl                (PLB_ARBITER_BASE+ 0x04)
+#define plb0_bearh                (PLB_ARBITER_BASE+ 0x05)
+#define plb0_ccr                  (PLB_ARBITER_BASE+ 0x08)
+
+#define plb1_acr                  (PLB_ARBITER_BASE+ 0x09)
+#define   plb1_acr_ppm_mask             0xF0000000
+#define   plb1_acr_ppm_fixed            0x00000000
+#define   plb1_acr_ppm_fair             0xD0000000
+#define   plb1_acr_hbu_mask             0x08000000
+#define   plb1_acr_hbu_disabled         0x00000000
+#define   plb1_acr_hbu_enabled          0x08000000
+#define   plb1_acr_rdp_mask             0x06000000
+#define   plb1_acr_rdp_disabled         0x00000000
+#define   plb1_acr_rdp_2deep            0x02000000
+#define   plb1_acr_rdp_3deep            0x04000000
+#define   plb1_acr_rdp_4deep            0x06000000
+#define   plb1_acr_wrp_mask             0x01000000
+#define   plb1_acr_wrp_disabled         0x00000000
+#define   plb1_acr_wrp_2deep            0x01000000
+
+#define plb1_besrl                (PLB_ARBITER_BASE+ 0x0A)
+#define plb1_besrh                (PLB_ARBITER_BASE+ 0x0B)
+#define plb1_bearl                (PLB_ARBITER_BASE+ 0x0C)
+#define plb1_bearh                (PLB_ARBITER_BASE+ 0x0D)
+
+#endif /* 440EP || 440GR || 440EPX || 440GR || 460EX || 460GT */
 
 /*-----------------------------------------------------------------------------
  | L2 Cache
-------------- next part --------------
An HTML attachment was scrubbed...
URL: http://lists.denx.de/pipermail/u-boot/attachments/20080806/fbbd5aa5/attachment.htm 

^ permalink raw reply related	[flat|nested] 3+ messages in thread

* [U-Boot-Users] [PATCH] PPC4xx: Memory Queue Optimizations for PPC460EX/GT
  2008-08-06 22:27 [U-Boot-Users] [PATCH] PPC4xx: Memory Queue Optimizations for PPC460EX/GT Prodyut Hazarika
@ 2008-08-07 10:18 ` Stefan Roese
  2008-08-07 18:28   ` Prodyut Hazarika
  0 siblings, 1 reply; 3+ messages in thread
From: Stefan Roese @ 2008-08-07 10:18 UTC (permalink / raw)
  To: u-boot

On Thursday 07 August 2008, Prodyut Hazarika wrote:
> Set PL44 Arbiter Read pipeline depth to 4
> Optimize Memory Queue Configuration registers for PPC460EX/GT
>
> Signed-off-by: Prodyut Hazarika <phazarika@amcc.com>

Thanks. Please find some comments below.

> ---
>  board/amcc/canyonlands/canyonlands.c |    9 +++
>  cpu/ppc4xx/44x_spd_ddr2.c            |    4 +
>  include/ppc440.h                     |  101
> ++++++++++++++++++---------------- 3 files changed, 66 insertions(+), 48
> deletions(-)
>
> diff --git a/board/amcc/canyonlands/canyonlands.c
> b/board/amcc/canyonlands/canyonlands.c index e9eba49..dd285bc 100644
> --- a/board/amcc/canyonlands/canyonlands.c
> +++ b/board/amcc/canyonlands/canyonlands.c
> @@ -113,6 +113,15 @@ int board_early_init_f(void)
>  	mtdcr(AHB_TOP, 0x8000004B);
>  	mtdcr(AHB_BOT, 0x8000004B);
>
> +	mtdcr(plb0_acr, plb0_acr_ppm_fair    |
> +			plb0_acr_hbu_enabled |
> +			plb0_acr_rdp_4deep   |
> +			plb0_acr_wrp_2deep);
> +	mtdcr(plb1_acr, plb1_acr_ppm_fair    |
> +			plb1_acr_hbu_enabled |
> +			plb1_acr_rdp_4deep   |
> +			plb1_acr_wrp_2deep);
> +

Is this PLB0_ACR tuning Canyonlands specific? Or will all 460EX/GT boards 
profit from this configuration? Or even other 4xx PPC variants as well?

If this is the case then I suggest to move this code to a common place, 
perhaps in cpu_init_f(). What do you think?

>  	if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) {
>  		/*
>  		 * Configure USB-STP pins as alternate and not GPIO
> diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
> index e9940e8..c222507 100644
> --- a/cpu/ppc4xx/44x_spd_ddr2.c
> +++ b/cpu/ppc4xx/44x_spd_ddr2.c
> @@ -2251,6 +2251,10 @@ static void program_memory_queue(unsigned long
> *dimm_populated, */
>  	mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
>  	mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
> +
> +	mtdcr(SDRAM_CONF1HB, 0x80001c80);
> +	mtdcr(SDRAM_CONF1LL, 0x80001c80);
> +	mtdcr(SDRAM_CONFPATHB, 0x18a68000);

Could you please add a comment what exactly is configured with these "magic 
numbers"?

>  #endif
>  }
>
> diff --git a/include/ppc440.h b/include/ppc440.h
> index c581f1b..650ee4f 100644
> --- a/include/ppc440.h
> +++ b/include/ppc440.h
> @@ -422,53 +422,6 @@
>
>  #define PLB4_ACR_WRP		(0x80000000 >> 7)
>
> -/* Nebula PLB4 Arbiter - PowerPC440EP */
> -#define PLB_ARBITER_BASE   0x80
> -
> -#define plb0_revid                (PLB_ARBITER_BASE+ 0x00)
> -#define plb0_acr                  (PLB_ARBITER_BASE+ 0x01)
> -#define   plb0_acr_ppm_mask             0xF0000000
> -#define   plb0_acr_ppm_fixed            0x00000000
> -#define   plb0_acr_ppm_fair             0xD0000000
> -#define   plb0_acr_hbu_mask             0x08000000
> -#define   plb0_acr_hbu_disabled         0x00000000
> -#define   plb0_acr_hbu_enabled          0x08000000
> -#define   plb0_acr_rdp_mask             0x06000000
> -#define   plb0_acr_rdp_disabled         0x00000000
> -#define   plb0_acr_rdp_2deep            0x02000000
> -#define   plb0_acr_rdp_3deep            0x04000000
> -#define   plb0_acr_rdp_4deep            0x06000000
> -#define   plb0_acr_wrp_mask             0x01000000
> -#define   plb0_acr_wrp_disabled         0x00000000
> -#define   plb0_acr_wrp_2deep            0x01000000
> -
> -#define plb0_besrl                (PLB_ARBITER_BASE+ 0x02)
> -#define plb0_besrh                (PLB_ARBITER_BASE+ 0x03)
> -#define plb0_bearl                (PLB_ARBITER_BASE+ 0x04)
> -#define plb0_bearh                (PLB_ARBITER_BASE+ 0x05)
> -#define plb0_ccr                  (PLB_ARBITER_BASE+ 0x08)
> -
> -#define plb1_acr                  (PLB_ARBITER_BASE+ 0x09)
> -#define   plb1_acr_ppm_mask             0xF0000000
> -#define   plb1_acr_ppm_fixed            0x00000000
> -#define   plb1_acr_ppm_fair             0xD0000000
> -#define   plb1_acr_hbu_mask             0x08000000
> -#define   plb1_acr_hbu_disabled         0x00000000
> -#define   plb1_acr_hbu_enabled          0x08000000
> -#define   plb1_acr_rdp_mask             0x06000000
> -#define   plb1_acr_rdp_disabled         0x00000000
> -#define   plb1_acr_rdp_2deep            0x02000000
> -#define   plb1_acr_rdp_3deep            0x04000000
> -#define   plb1_acr_rdp_4deep            0x06000000
> -#define   plb1_acr_wrp_mask             0x01000000
> -#define   plb1_acr_wrp_disabled         0x00000000
> -#define   plb1_acr_wrp_2deep            0x01000000
> -
> -#define plb1_besrl                (PLB_ARBITER_BASE+ 0x0A)
> -#define plb1_besrh                (PLB_ARBITER_BASE+ 0x0B)
> -#define plb1_bearl                (PLB_ARBITER_BASE+ 0x0C)
> -#define plb1_bearh                (PLB_ARBITER_BASE+ 0x0D)
> -
>  /* Pin Function Control Register 1 */
>  #define SDR0_PFC1                    0x4101
>  #define   SDR0_PFC1_U1ME_MASK         0x02000000    /* UART1 Mode Enable
> */ @@ -742,7 +695,59 @@
>  #define   SDR0_PFC1_PLB_PME_PLB4_SEL  0x00001000      /* PLB3 Performance
> Monitor Enable */ #define   SDR0_PFC1_GFGGI_MASK        0x0000000F    /*
> GPT Frequency Generation Gated In */
>
> -#endif /* 440EP || 440GR || 440EPX || 440GRX */
> +#endif  /* 440EP || 440GR || 440EPX || 440GRX */
> +
> +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
> +    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
> +    defined(CONFIG_460EX) || defined(CONFIG_460GT)

Are the PLBx_ACR register really identical on all those PPC's? Just checking.

> +#define PLB_ARBITER_BASE   0x80
> +
> +#define plb0_revid                (PLB_ARBITER_BASE+ 0x00)
> +#define plb0_acr                  (PLB_ARBITER_BASE+ 0x01)
> +#define   plb0_acr_ppm_mask             0xF0000000
> +#define   plb0_acr_ppm_fixed            0x00000000
> +#define   plb0_acr_ppm_fair             0xD0000000
> +#define   plb0_acr_hbu_mask             0x08000000
> +#define   plb0_acr_hbu_disabled         0x00000000
> +#define   plb0_acr_hbu_enabled          0x08000000
> +#define   plb0_acr_rdp_mask             0x06000000
> +#define   plb0_acr_rdp_disabled         0x00000000
> +#define   plb0_acr_rdp_2deep            0x02000000
> +#define   plb0_acr_rdp_3deep            0x04000000
> +#define   plb0_acr_rdp_4deep            0x06000000
> +#define   plb0_acr_wrp_mask             0x01000000
> +#define   plb0_acr_wrp_disabled         0x00000000
> +#define   plb0_acr_wrp_2deep            0x01000000
> +
> +#define plb0_besrl                (PLB_ARBITER_BASE+ 0x02)
> +#define plb0_besrh                (PLB_ARBITER_BASE+ 0x03)
> +#define plb0_bearl                (PLB_ARBITER_BASE+ 0x04)
> +#define plb0_bearh                (PLB_ARBITER_BASE+ 0x05)
> +#define plb0_ccr                  (PLB_ARBITER_BASE+ 0x08)
> +
> +#define plb1_acr                  (PLB_ARBITER_BASE+ 0x09)
> +#define   plb1_acr_ppm_mask             0xF0000000
> +#define   plb1_acr_ppm_fixed            0x00000000
> +#define   plb1_acr_ppm_fair             0xD0000000
> +#define   plb1_acr_hbu_mask             0x08000000
> +#define   plb1_acr_hbu_disabled         0x00000000
> +#define   plb1_acr_hbu_enabled          0x08000000
> +#define   plb1_acr_rdp_mask             0x06000000
> +#define   plb1_acr_rdp_disabled         0x00000000
> +#define   plb1_acr_rdp_2deep            0x02000000
> +#define   plb1_acr_rdp_3deep            0x04000000
> +#define   plb1_acr_rdp_4deep            0x06000000
> +#define   plb1_acr_wrp_mask             0x01000000
> +#define   plb1_acr_wrp_disabled         0x00000000
> +#define   plb1_acr_wrp_2deep            0x01000000
> +
> +#define plb1_besrl                (PLB_ARBITER_BASE+ 0x0A)
> +#define plb1_besrh                (PLB_ARBITER_BASE+ 0x0B)
> +#define plb1_bearl                (PLB_ARBITER_BASE+ 0x0C)
> +#define plb1_bearh                (PLB_ARBITER_BASE+ 0x0D)
> +
> +#endif /* 440EP || 440GR || 440EPX || 440GR || 460EX || 460GT */

Please fix if necessary and resubmit. And please keep me on CC on 4xx related 
patches.

Thanks.

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

^ permalink raw reply	[flat|nested] 3+ messages in thread

* [U-Boot-Users] [PATCH] PPC4xx: Memory Queue Optimizations for PPC460EX/GT
  2008-08-07 10:18 ` Stefan Roese
@ 2008-08-07 18:28   ` Prodyut Hazarika
  0 siblings, 0 replies; 3+ messages in thread
From: Prodyut Hazarika @ 2008-08-07 18:28 UTC (permalink / raw)
  To: u-boot

Thanks Stefan for your comments. Please see reply below.
 
>> +     mtdcr(plb1_acr, plb1_acr_ppm_fair    |
>> +                     plb1_acr_hbu_enabled |
>> +                     plb1_acr_rdp_4deep   |
>> +                     plb1_acr_wrp_2deep);
>> +
>
>Is this PLB0_ACR tuning Canyonlands specific? Or will all 460EX/GT boards
>profit from this configuration? Or even other 4xx PPC variants as well?
>
>If this is the case then I suggest to move this code to a common place,
>perhaps in cpu_init_f(). What do you think?
The PLB Arbiter register configuration are definitely common to PPC460EX/GT boards.
I am working with PowerPC hardware architects to find out whether we can put the same
changes for other PPC4xx variants
 
>> +
>> +     mtdcr(SDRAM_CONF1HB, 0x80001c80);
>> +     mtdcr(SDRAM_CONF1LL, 0x80001c80);
>> +     mtdcr(SDRAM_CONFPATHB, 0x18a68000);
>
>Could you please add a comment what exactly is configured with these "magic
>numbers"?
I will add C defines corresponding to those register bits and resubmit
 
>> +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
>> +    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
>> +    defined(CONFIG_460EX) || defined(CONFIG_460GT)
>
>Are the PLBx_ACR register really identical on all those PPC's? Just checking.
They seem to be so. I will double-check the user manuals for all these processors.
 
>Please fix if necessary and resubmit. And please keep me on CC on 4xx related
>patches.
I will try to put out the modified patch latest by tommorow.
 
Best Regards,
Prodyut Hazarika
 
================================
Staff S/W Engineer
AMCC
================================
 
-------------- next part --------------
An HTML attachment was scrubbed...
URL: http://lists.denx.de/pipermail/u-boot/attachments/20080807/a80e3c4c/attachment.htm 

^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2008-08-07 18:28 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2008-08-06 22:27 [U-Boot-Users] [PATCH] PPC4xx: Memory Queue Optimizations for PPC460EX/GT Prodyut Hazarika
2008-08-07 10:18 ` Stefan Roese
2008-08-07 18:28   ` Prodyut Hazarika

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox