[U-Boot] [PATCH v2 0/6] i.MX31: Add NAND support and new PDK board.

[U-Boot] [PATCH v2 0/6] i.MX31: Add NAND support and new PDK board.

[Magnus Lilja]

Hi again

This series of patches adds support for the NAND flash controller in the
i.MX31 device and also introduces the Freescale i.MX31 PDK board.

Changes since v1:

- Moved PDK board to boards/freescale/mx31pdk
- Moved mxc_nd.c to driver/mtd/nand/mx31_nand.c
- Moved contents of mxc_nd.h to mx31-regs.h
- Cleaned up the mx31pdk.h config file after comments from this list
- CONFIG_CMD_IMLS is still #undef'd but a comment is added in the config
  file about that.
- A new patch has been inserted into the series, it makes the MC13783 SPI
  bus and chip select configurable.

The patches are based on the current main U-boot git repo.

Original intro for this series of patches:

At the moment, the patch series does not add support for booting from
NAND. This means that the PDK board support assumes that some other entity
configures the SDRAM and loads U-boot into RAM (e.g. another bootloader or a
JTAG debugger). Support for NAND boot is in progress and will be submitted
later.

The NAND driver is based on Freescale's Linux driver from their BSP. I've
cleaned it up a bit and made the (minor) modifications necessary for
U-boot. Perhaps the driver should be cleaned up even more, there are some
CONFIG_MTD_MXC_* leftovers in the driver.

I have tested the driver on the Litekit (small page NAND) and on the PDK
(large page NAND) by having the U-boot environment placed in NAND.



Regards, Magnus

[U-Boot] [PATCH v2 1/6] i.MX31: Add NFC_BASE_ADDR definition.

[Magnus Lilja]

Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
---
 include/asm-arm/arch-mx31/mx31-regs.h |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h
index b04a718..769c1e8 100644
--- a/include/asm-arm/arch-mx31/mx31-regs.h
+++ b/include/asm-arm/arch-mx31/mx31-regs.h
@@ -168,4 +168,15 @@
 #define CS5_BASE	0xB6000000
 #define PCMCIA_MEM_BASE	0xC0000000
 
+/*
+ * NAND controller
+ */
+#define NFC_BASE_ADDR	0xB8000000
+
+/*
+ * NFMS bit in RCSR register for pagesize of nandflash
+ */
+#define NFMS (*((volatile u32 *)CCM_RCSR))
+#define NFMS_BIT 30
+
 #endif /* __ASM_ARCH_MX31_REGS_H */
-- 
1.5.2.4

[U-Boot] [PATCH v2 2/6] i.MX31: Add reset_timer() and modify get_timer_masked().

[Magnus Lilja]

This patch adds the reset_timer() function (needed by nand_base.c) and
modifies the get_timer_masked() to work in the same way as the omap24xx
function.

Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
---
 cpu/arm1136/mx31/interrupts.c |   22 ++++++++++++++++++----
 1 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/cpu/arm1136/mx31/interrupts.c b/cpu/arm1136/mx31/interrupts.c
index 21b77a5..b173919 100644
--- a/cpu/arm1136/mx31/interrupts.c
+++ b/cpu/arm1136/mx31/interrupts.c
@@ -38,6 +38,9 @@
 #define GPTCR_CLKSOURCE_32 (4<<6)  /* Clock source */
 #define GPTCR_TEN       (1)     /* Timer enable */
 
+static ulong timestamp;
+static ulong lastinc;
+
 /* nothing really to do with interrupts, just starts up a counter. */
 int interrupt_init (void)
 {
@@ -54,14 +57,25 @@ int interrupt_init (void)
 
 void reset_timer_masked (void)
 {
-	GPTCR = 0;
-	GPTCR = GPTCR_CLKSOURCE_32 | GPTCR_TEN; /* Freerun Mode, PERCLK1 input */
+	lastinc = GPTCNT;
+	timestamp = 0;
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
 }
 
 ulong get_timer_masked (void)
 {
-	ulong val = GPTCNT;
-	return val;
+	ulong now = GPTCNT;
+
+	if (now >= lastinc)
+		timestamp += (now - lastinc);
+	else
+		timestamp += (0xFFFFFFFF - lastinc) + now;
+	lastinc = now;
+	return timestamp;
 }
 
 ulong get_timer (ulong base)
-- 
1.5.2.4

[U-Boot] [PATCH v2 3/6] i.MX31: Add i.MX31 NAND Flash Controller driver.

[Magnus Lilja]

Imported from Freescale's Linux NFC driver from the i.MX31 BSP
release 5 (Linux 2.6.22.5) and the i.MX31 PDK BSP (Linux 2.6.24).

The code has been changed to conform (better) with the coding style
in Linux/U-boot. Sections not used by U-boot have been removed.

The driver has been tested on i.MX31 Litekit (small page NAND)
and i.MX31 PDK (large page NAND). Both boards have 8 bit wide
NAND devices.
16 bit NAND devices have not been tested and probably requires a
minor code change.

Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
---
 drivers/mtd/nand/Makefile             |    1 +
 drivers/mtd/nand/mx31_nand.c          | 1172 +++++++++++++++++++++++++++++++++
 include/asm-arm/arch-mx31/mx31-regs.h |   85 +++
 3 files changed, 1258 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 1923310..729b8c2 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -37,6 +37,7 @@ endif
 
 COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
 COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
+COBJS-$(CONFIG_MX31_NAND) += mx31_nand.o
 endif
 
 COBJS	:= $(COBJS-y)
diff --git a/drivers/mtd/nand/mx31_nand.c b/drivers/mtd/nand/mx31_nand.c
new file mode 100644
index 0000000..af40772
--- /dev/null
+++ b/drivers/mtd/nand/mx31_nand.c
@@ -0,0 +1,1172 @@
+/*
+ * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
+ *
+ * Based on Freescale's Linux MXC NAND driver.
+ *
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm-arm/arch/mx31-regs.h>
+
+/* The bool type is used locally in this file, added for U-boot. */
+typedef enum {false = 0, true = 1 } bool;
+
+struct mxc_mtd_s {
+	struct mtd_info mtd;
+	struct nand_chip nand;
+	struct device *dev;
+};
+
+static struct mxc_mtd_s *mxc_nand_data;
+
+/*
+ * Define delays in microsec for NAND device operations
+ */
+#define TROP_US_DELAY   2000
+
+/*
+ * Macros to get byte and bit positions of ECC
+ */
+#define COLPOS(x) ((x) >> 4)
+#define BITPOS(x) ((x) & 0xf)
+
+/* Define single bit Error positions in Main & Spare area */
+#define MAIN_SINGLEBIT_ERROR 0x4
+#define SPARE_SINGLEBIT_ERROR 0x1
+
+struct nand_info {
+	bool bSpareOnly;
+	bool bStatusRequest;
+	u16 colAddr;
+};
+
+static struct nand_info g_nandfc_info;
+
+#ifdef CONFIG_MTD_NAND_MXC_SWECC
+static int hardware_ecc;
+#else
+static int hardware_ecc = 1;
+#endif
+
+#ifndef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2
+static int Ecc_disabled;
+#endif
+
+static int is2k_Pagesize;
+
+/*
+ * OOB placement block for use with hardware ecc generation
+ */
+static struct nand_ecclayout nand_hw_eccoob_8 = {
+	.eccbytes = 5,
+	.eccpos = {6, 7, 8, 9, 10},
+	.oobfree = {
+		{.offset = 0,
+		 .length = 5},
+		{.offset = 11,
+		 .length = 5}}
+};
+
+static struct nand_ecclayout nand_hw_eccoob_16 = {
+	.eccbytes = 5,
+	.eccpos = {6, 7, 8, 9, 10},
+	.oobfree = {
+		{.offset = 0,
+		 .length = 6},
+		{.offset = 12,
+		 .length = 4}}
+};
+
+static struct nand_ecclayout nand_hw_eccoob_2k = {
+	.eccbytes = 20,
+	.eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
+		   38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
+	.oobfree = {
+		{.offset = 0,
+		 .length = 5},
+		{.offset = 11,
+		 .length = 10},
+		{.offset = 27,
+		 .length = 10},
+		{.offset = 43,
+		 .length = 10},
+		{.offset = 59,
+		 .length = 5}}
+};
+
+/* Define some generic bad / good block scan pattern which are used
+ * while scanning a device for factory marked good / bad blocks. */
+static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
+
+static struct nand_bbt_descr smallpage_memorybased = {
+	.options = NAND_BBT_SCAN2NDPAGE,
+	.offs = 5,
+	.len = 1,
+	.pattern = scan_ff_pattern
+};
+
+static struct nand_bbt_descr largepage_memorybased = {
+	.options = 0,
+	.offs = 0,
+	.len = 2,
+	.pattern = scan_ff_pattern
+};
+
+/* Generic flash bbt decriptors */
+static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
+static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
+
+static struct nand_bbt_descr bbt_main_descr = {
+	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
+	    | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+	.offs = 0,
+	.len = 4,
+	.veroffs = 4,
+	.maxblocks = 4,
+	.pattern = bbt_pattern
+};
+
+static struct nand_bbt_descr bbt_mirror_descr = {
+	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
+	    | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+	.offs = 0,
+	.len = 4,
+	.veroffs = 4,
+	.maxblocks = 4,
+	.pattern = mirror_pattern
+};
+
+/**
+ * memcpy variant that copies 32 bit words. This is needed since the
+ * NFC only allows 32 bit accesses. Added for U-boot.
+ */
+static void *memcpy_32(void *dest, const void *src, size_t n)
+{
+	u32 *dst_32 = (u32 *)dest;
+	const u32 *src_32 = (u32 *)src;
+
+	while (n > 0) {
+		*dst_32++ = *src_32++;
+		n -= 4;
+	}
+
+	return dest;
+}
+
+/**
+ * This function polls the NANDFC to wait for the basic operation to
+ * complete by checking the INT bit of config2 register.
+ *
+ * @param       maxRetries     number of retry attempts (separated by 1 us)
+ * @param       param          parameter for debug
+ * @param       useirq         True if IRQ should be used rather than polling
+ */
+static void wait_op_done(int maxRetries, u16 param, bool useirq)
+{
+	while (maxRetries-- > 0) {
+		if (NFC_CONFIG2 & NFC_INT) {
+			NFC_CONFIG2 &= ~NFC_INT;
+			break;
+		}
+		udelay(1);
+	}
+	if (maxRetries <= 0)
+		MTDDEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n",
+			 __FUNCTION__, param);
+}
+
+/**
+ * This function issues the specified command to the NAND device and
+ * waits for completion.
+ *
+ * @param       cmd     command for NAND Flash
+ * @param       useirq  True if IRQ should be used rather than polling
+ */
+static void send_cmd(u16 cmd, bool useirq)
+{
+	MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(0x%x, %d)\n", cmd, useirq);
+
+	NFC_FLASH_CMD = (u16) cmd;
+	NFC_CONFIG2 = NFC_CMD;
+
+	/* Wait for operation to complete */
+	wait_op_done(TROP_US_DELAY, cmd, useirq);
+}
+
+/**
+ * This function sends an address (or partial address) to the
+ * NAND device.  The address is used to select the source/destination for
+ * a NAND command.
+ *
+ * @param       addr    address to be written to NFC.
+ * @param       islast  True if this is the last address cycle for command
+ */
+static void send_addr(u16 addr, bool islast)
+{
+	MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(0x%x %d)\n", addr, islast);
+
+	NFC_FLASH_ADDR = addr;
+	NFC_CONFIG2 = NFC_ADDR;
+
+	/* Wait for operation to complete */
+	wait_op_done(TROP_US_DELAY, addr, islast);
+}
+
+/**
+ * This function requests the NANDFC to initate the transfer
+ * of data currently in the NANDFC RAM buffer to the NAND device.
+ *
+ * @param	buf_id	      Specify Internal RAM Buffer number (0-3)
+ * @param       bSpareOnly    set true if only the spare area is transferred
+ */
+static void send_prog_page(u8 buf_id, bool bSpareOnly)
+{
+	MTDDEBUG(MTD_DEBUG_LEVEL3, "send_prog_page (%d)\n", bSpareOnly);
+
+	/* NANDFC buffer 0 is used for page read/write */
+
+	NFC_BUF_ADDR = buf_id;
+
+	/* Configure spare or page+spare access */
+	if (!is2k_Pagesize) {
+		if (bSpareOnly)
+			NFC_CONFIG1 |= NFC_SP_EN;
+		else
+			NFC_CONFIG1 &= ~NFC_SP_EN;
+	}
+	NFC_CONFIG2 = NFC_INPUT;
+
+	/* Wait for operation to complete */
+	wait_op_done(TROP_US_DELAY, bSpareOnly, true);
+}
+
+/**
+ * This function will correct the single bit ECC error
+ *
+ * @param  buf_id	Specify Internal RAM Buffer number (0-3)
+ * @param  eccpos 	Ecc byte and bit position
+ * @param  bSpareOnly  	set to true if only spare area needs correction
+ */
+static void mxc_nd_correct_error(u8 buf_id, u16 eccpos, bool bSpareOnly)
+{
+	u16 col;
+	u8 pos;
+	volatile u16 *buf;
+
+	/* Get col & bit position of error
+	   these macros works for both 8 & 16 bits */
+	col = COLPOS(eccpos);	/* Get half-word position */
+	pos = BITPOS(eccpos);	/* Get bit position */
+
+	MTDDEBUG(MTD_DEBUG_LEVEL3,
+		 "mxc_nd_correct_error (col=%d pos=%d)\n", col, pos);
+
+	/* Set the pointer for main / spare area */
+	if (!bSpareOnly)
+		buf = (volatile u16 *)(MAIN_AREA0 + col + (256 * buf_id));
+	else
+		buf = (volatile u16 *)(SPARE_AREA0 + col + (8 * buf_id));
+
+	/* Fix the data */
+	*buf ^= 1 << pos;
+}
+
+/**
+ * This function will maintains state of single bit Error
+ * in Main & spare  area
+ *
+ * @param buf_id	Specify Internal RAM Buffer number (0-3)
+ * @param spare  	set to true if only spare area needs correction
+ */
+static void mxc_nd_correct_ecc(u8 buf_id, bool spare)
+{
+#ifdef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2
+	/* To maintain single bit error in previous page */
+	static int lastErrMain, lastErrSpare;
+#endif
+	u16 value, ecc_status;
+
+	/* Read the ECC result */
+	ecc_status = NFC_ECC_STATUS_RESULT;
+	MTDDEBUG(MTD_DEBUG_LEVEL3,
+		 "mxc_nd_correct_ecc (Ecc status=%x)\n", ecc_status);
+
+#ifdef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2
+	/* Check for Error in Mainarea */
+	if ((ecc_status & 0xC) == MAIN_SINGLEBIT_ERROR) {
+		/* Check for error in previous page */
+		if (lastErrMain && !spare) {
+			value = NFC_RSLTMAIN_AREA;
+			/* Correct single bit error in Mainarea
+			   NFC will not correct the error in
+			   current page */
+			mxc_nd_correct_error(buf_id, value, false);
+		} else
+			/* Set if single bit error in current page */
+			lastErrMain = 1;
+	} else
+		/* Reset if no single bit error in current page */
+		lastErrMain = 0;
+
+	/* Check for Error in Sparearea */
+	if ((ecc_status & 0x3) == SPARE_SINGLEBIT_ERROR) {
+		/* Check for error in previous page */
+		if (lastErrSpare) {
+			value = NFC_RSLTSPARE_AREA;
+			/* Correct single bit error in Mainarea
+			   NFC will not correct the error in
+			   current page */
+			mxc_nd_correct_error(buf_id, value, true);
+		} else
+			/* Set if single bit error in current page */
+			lastErrSpare = 1;
+	} else
+		/* Reset if no single bit error in current page */
+		lastErrSpare = 0;
+#else
+	if (((ecc_status & 0xC) == MAIN_SINGLEBIT_ERROR)
+	    || ((ecc_status & 0x3) == SPARE_SINGLEBIT_ERROR)) {
+		if (Ecc_disabled) {
+			if ((ecc_status & 0xC) == MAIN_SINGLEBIT_ERROR) {
+				value = NFC_RSLTMAIN_AREA;
+				/* Correct single bit error in Mainarea
+				   NFC will not correct the error in
+				   current page */
+				mxc_nd_correct_error(buf_id, value, false);
+			}
+			if ((ecc_status & 0x3) == SPARE_SINGLEBIT_ERROR) {
+				value = NFC_RSLTSPARE_AREA;
+				/* Correct single bit error in Mainarea
+				   NFC will not correct the error in
+				   current page */
+				mxc_nd_correct_error(buf_id, value, true);
+			}
+
+		} else {
+			/* Disable ECC  */
+			NFC_CONFIG1 &= ~NFC_ECC_EN;
+			Ecc_disabled = 1;
+		}
+	} else if (ecc_status == 0) {
+		if (Ecc_disabled) {
+			/* Enable ECC */
+			NFC_CONFIG1 |= NFC_ECC_EN;
+			Ecc_disabled = 0;
+		}
+	} /* else 2-bit Error. Do nothing */
+#endif /* CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2 */
+}
+
+/**
+ * This function requests the NANDFC to initated the transfer
+ * of data from the NAND device into in the NANDFC ram buffer.
+ *
+ * @param  	buf_id		Specify Internal RAM Buffer number (0-3)
+ * @param       bSpareOnly    	set true if only the spare area is
+ * transferred
+ */
+static void send_read_page(u8 buf_id, bool bSpareOnly)
+{
+	MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", bSpareOnly);
+
+	/* NANDFC buffer 0 is used for page read/write */
+	NFC_BUF_ADDR = buf_id;
+
+	/* Configure spare or page+spare access */
+	if (!is2k_Pagesize) {
+		if (bSpareOnly)
+			NFC_CONFIG1 |= NFC_SP_EN;
+		else
+			NFC_CONFIG1 &= ~NFC_SP_EN;
+	}
+
+	NFC_CONFIG2 = NFC_OUTPUT;
+
+	/* Wait for operation to complete */
+	wait_op_done(TROP_US_DELAY, bSpareOnly, true);
+
+	/* If there are single bit errors in
+	   two consecutive page reads then
+	   the error is not  corrected by the
+	   NFC for the second page.
+	   Correct single bit error in driver */
+
+	mxc_nd_correct_ecc(buf_id, bSpareOnly);
+}
+
+/**
+ * This function requests the NANDFC to perform a read of the
+ * NAND device ID.
+ */
+static void send_read_id(void)
+{
+	struct nand_chip *this = &mxc_nand_data->nand;
+
+	/* NANDFC buffer 0 is used for device ID output */
+	NFC_BUF_ADDR = 0x0;
+
+	/* Read ID into main buffer */
+	NFC_CONFIG1 &= ~NFC_SP_EN;
+	NFC_CONFIG2 = NFC_ID;
+
+	/* Wait for operation to complete */
+	wait_op_done(TROP_US_DELAY, 0, true);
+
+	if (this->options & NAND_BUSWIDTH_16) {
+		volatile u16 *mainBuf = MAIN_AREA0;
+
+		/*
+		 * Pack the every-other-byte result for 16-bit ID reads
+		 * into every-byte as the generic code expects and various
+		 * chips implement.
+		 */
+
+		mainBuf[0] = (mainBuf[0] & 0xff) | ((mainBuf[1] & 0xff) << 8);
+		mainBuf[1] = (mainBuf[2] & 0xff) | ((mainBuf[3] & 0xff) << 8);
+		mainBuf[2] = (mainBuf[4] & 0xff) | ((mainBuf[5] & 0xff) << 8);
+	}
+}
+
+/**
+ * This function requests the NANDFC to perform a read of the
+ * NAND device status and returns the current status.
+ *
+ * @return  device status
+ */
+static u16 get_dev_status(void)
+{
+	volatile u16 *mainBuf = MAIN_AREA1;
+	u32 store;
+	u16 ret;
+	/* Issue status request to NAND device */
+
+	/* store the main area1 first word, later do recovery */
+	store = *((u32 *) mainBuf);
+	/*
+	 * NANDFC buffer 1 is used for device status to prevent
+	 * corruption of read/write buffer on status requests.
+	 */
+	NFC_BUF_ADDR = 1;
+
+	/* Read status into main buffer */
+	NFC_CONFIG1 &= ~NFC_SP_EN;
+	NFC_CONFIG2 = NFC_STATUS;
+
+	/* Wait for operation to complete */
+	wait_op_done(TROP_US_DELAY, 0, true);
+
+	/* Status is placed in first word of main buffer */
+	/* get status, then recovery area 1 data */
+	ret = mainBuf[0];
+	*((u32 *) mainBuf) = store;
+
+	return ret;
+}
+
+/**
+ * This functions is used by upper layer to checks if device is ready
+ *
+ * @param       mtd     MTD structure for the NAND Flash
+ *
+ * @return  0 if device is busy else 1
+ */
+static int mxc_nand_dev_ready(struct mtd_info *mtd)
+{
+	/*
+	 * NFC handles R/B internally.Therefore,this function
+	 * always returns status as ready.
+	 */
+	return 1;
+}
+
+static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
+{
+	/*
+	 * If HW ECC is enabled, we turn it on during init.  There is
+	 * no need to enable again here.
+	 */
+}
+
+static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
+				 u_char *read_ecc, u_char *calc_ecc)
+{
+	/*
+	 * 1-Bit errors are automatically corrected in HW.  No need for
+	 * additional correction.  2-Bit errors cannot be corrected by
+	 * HW ECC, so we need to return failure
+	 */
+	u16 ecc_status = NFC_ECC_STATUS_RESULT;
+
+	if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
+		MTDDEBUG(MTD_DEBUG_LEVEL0,
+			 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
+				  u_char *ecc_code)
+{
+	/*
+	 * Just return success.  HW ECC does not read/write the NFC spare
+	 * buffer.  Only the FLASH spare area contains the calcuated ECC.
+	 */
+	return 0;
+}
+
+/**
+ * This function reads byte from the NAND Flash
+ *
+ * @param       mtd     MTD structure for the NAND Flash
+ *
+ * @return    data read from the NAND Flash
+ */
+static u_char mxc_nand_read_byte(struct mtd_info *mtd)
+{
+	u_char retVal = 0;
+	u16 col, rdWord;
+	volatile u16 *mainBuf = MAIN_AREA0;
+	volatile u16 *spareBuf = SPARE_AREA0;
+
+	/* Check for status request */
+	if (g_nandfc_info.bStatusRequest)
+		return get_dev_status() & 0xFF;
+
+	/* Get column for 16-bit access */
+	col = g_nandfc_info.colAddr >> 1;
+
+	/* If we are accessing the spare region */
+	if (g_nandfc_info.bSpareOnly)
+		rdWord = spareBuf[col];
+	else
+		rdWord = mainBuf[col];
+
+	/* Pick upper/lower byte of word from RAM buffer */
+	if (g_nandfc_info.colAddr & 0x1)
+		retVal = (rdWord >> 8) & 0xFF;
+	else
+		retVal = rdWord & 0xFF;
+
+	/* Update saved column address */
+	g_nandfc_info.colAddr++;
+
+	return retVal;
+}
+
+/**
+  * This function reads word from the NAND Flash
+  *
+  * @param       mtd     MTD structure for the NAND Flash
+  *
+  * @return    data read from the NAND Flash
+  */
+static u16 mxc_nand_read_word(struct mtd_info *mtd)
+{
+	u16 col;
+	u16 rdWord, retVal;
+	volatile u16 *p;
+
+	MTDDEBUG(MTD_DEBUG_LEVEL3,
+		 "mxc_nand_read_word(col = %d)\n", g_nandfc_info.colAddr);
+
+	col = g_nandfc_info.colAddr;
+	/* Adjust saved column address */
+	if (col < mtd->writesize && g_nandfc_info.bSpareOnly)
+		col += mtd->writesize;
+
+	if (col < mtd->writesize)
+		p = (MAIN_AREA0) + (col >> 1);
+	else
+		p = (SPARE_AREA0) + ((col - mtd->writesize) >> 1);
+
+	if (col & 1) {
+		rdWord = *p;
+		retVal = (rdWord >> 8) & 0xff;
+		rdWord = *(p + 1);
+		retVal |= (rdWord << 8) & 0xff00;
+
+	} else
+		retVal = *p;
+
+	/* Update saved column address */
+	g_nandfc_info.colAddr = col + 2;
+
+	return retVal;
+}
+
+/**
+ * This function writes data of length \b len to buffer \b buf. The data
+ * to be written on NAND Flash is first copied to RAMbuffer. After the
+ * Data Input Operation by the NFC, the data is written to NAND Flash.
+ *
+ * @param       mtd     MTD structure for the NAND Flash
+ * @param       buf     data to be written to NAND Flash
+ * @param       len     number of bytes to be written
+ */
+static void mxc_nand_write_buf(struct mtd_info *mtd,
+			       const u_char *buf, int len)
+{
+	int n;
+	int col;
+	int i = 0;
+
+	MTDDEBUG(MTD_DEBUG_LEVEL3,
+		 "mxc_nand_write_buf(col = %d, len = %d)\n",
+		 g_nandfc_info.colAddr, len);
+
+	col = g_nandfc_info.colAddr;
+
+	/* Adjust saved column address */
+	if (col < mtd->writesize && g_nandfc_info.bSpareOnly)
+		col += mtd->writesize;
+
+	n = mtd->writesize + mtd->oobsize - col;
+	n = min(len, n);
+
+	MTDDEBUG(MTD_DEBUG_LEVEL3,
+		 "%s:%d: col = %d, n = %d\n", __FUNCTION__, __LINE__, col, n);
+
+	while (n) {
+		volatile u32 *p;
+		if (col < mtd->writesize)
+			p = (volatile u32 *)((ulong) (MAIN_AREA0) + (col & ~3));
+		else
+			p = (volatile u32 *)((ulong) (SPARE_AREA0) -
+					     mtd->writesize + (col & ~3));
+
+		MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n",
+			 __FUNCTION__, __LINE__, p);
+
+		if (((col | (int)&buf[i]) & 3) || n < 16) {
+			u32 data = 0;
+
+			if (col & 3 || n < 4)
+				data = *p;
+
+			switch (col & 3) {
+			case 0:
+				if (n) {
+					data = (data & 0xffffff00) |
+					    (buf[i++] << 0);
+					n--;
+					col++;
+				}
+			case 1:
+				if (n) {
+					data = (data & 0xffff00ff) |
+					    (buf[i++] << 8);
+					n--;
+					col++;
+				}
+			case 2:
+				if (n) {
+					data = (data & 0xff00ffff) |
+					    (buf[i++] << 16);
+					n--;
+					col++;
+				}
+			case 3:
+				if (n) {
+					data = (data & 0x00ffffff) |
+					    (buf[i++] << 24);
+					n--;
+					col++;
+				}
+			}
+
+			*p = data;
+		} else {
+			int m = mtd->writesize - col;
+
+			if (col >= mtd->writesize)
+				m += mtd->oobsize;
+
+			m = min(n, m) & ~3;
+
+			MTDDEBUG(MTD_DEBUG_LEVEL3,
+				 "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
+				 __FUNCTION__, __LINE__, n, m, i, col);
+
+			memcpy_32((void *)(p), &buf[i], m);
+			col += m;
+			i += m;
+			n -= m;
+		}
+	}
+	/* Update saved column address */
+	g_nandfc_info.colAddr = col;
+}
+
+/**
+ * This function id is used to read the data buffer from the NAND Flash. To
+ * read the data from NAND Flash first the data output cycle is initiated by
+ * the NFC, which copies the data to RAMbuffer. This data of length \b len is
+ * then copied to buffer \b buf.
+ *
+ * @param       mtd     MTD structure for the NAND Flash
+ * @param       buf     data to be read from NAND Flash
+ * @param       len     number of bytes to be read
+ */
+static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+	int n;
+	int col;
+	int i = 0;
+
+	MTDDEBUG(MTD_DEBUG_LEVEL3,
+		 "mxc_nand_read_buf(col = %d, len = %d)\n",
+		 g_nandfc_info.colAddr, len);
+
+	col = g_nandfc_info.colAddr;
+	/* Adjust saved column address */
+	if (col < mtd->writesize && g_nandfc_info.bSpareOnly)
+		col += mtd->writesize;
+
+	n = mtd->writesize + mtd->oobsize - col;
+	n = min(len, n);
+
+	while (n) {
+		volatile u32 *p;
+
+		if (col < mtd->writesize)
+			p = (volatile u32 *)((ulong) (MAIN_AREA0) + (col & ~3));
+		else
+			p = (volatile u32 *)((ulong) (SPARE_AREA0) -
+					     mtd->writesize + (col & ~3));
+
+		if (((col | (int)&buf[i]) & 3) || n < 16) {
+			u32 data;
+
+			data = *p;
+			switch (col & 3) {
+			case 0:
+				if (n) {
+					buf[i++] = (u8) (data);
+					n--;
+					col++;
+				}
+			case 1:
+				if (n) {
+					buf[i++] = (u8) (data >> 8);
+					n--;
+					col++;
+				}
+			case 2:
+				if (n) {
+					buf[i++] = (u8) (data >> 16);
+					n--;
+					col++;
+				}
+			case 3:
+				if (n) {
+					buf[i++] = (u8) (data >> 24);
+					n--;
+					col++;
+				}
+			}
+		} else {
+			int m = mtd->writesize - col;
+
+			if (col >= mtd->writesize)
+				m += mtd->oobsize;
+
+			m = min(n, m) & ~3;
+			memcpy_32(&buf[i], (void *)(p), m);
+			col += m;
+			i += m;
+			n -= m;
+		}
+	}
+	/* Update saved column address */
+	g_nandfc_info.colAddr = col;
+}
+
+/**
+ * This function is used by the upper layer to verify the data in NAND Flash
+ * with the data in the \b buf.
+ *
+ * @param       mtd     MTD structure for the NAND Flash
+ * @param       buf     data to be verified
+ * @param       len     length of the data to be verified
+ *
+ * @return      -EFAULT if error else 0
+ */
+static int
+mxc_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+	return -1; /* Was -EFAULT */
+}
+
+/**
+ * This function is used by upper layer for select and deselect of the NAND
+ * chip.
+ *
+ * @param       mtd     MTD structure for the NAND Flash
+ * @param       chip    val indicating select or deselect
+ */
+static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
+{
+#ifdef CONFIG_MTD_NAND_MXC_FORCE_CE
+	if (chip > 0) {
+		MTDDEBUG(MTD_DEBUG_LEVEL0,
+			 "ERROR:  Illegal chip select (chip = %d)\n", chip);
+		return;
+	}
+
+	if (chip == -1) {
+		NFC_CONFIG1 &= ~NFC_CE;
+		return;
+	}
+
+	NFC_CONFIG1 |= NFC_CE;
+#endif
+}
+
+/**
+ * This function is used by the upper layer to write command to NAND Flash
+ * for different operations to be carried out on NAND Flash
+ *
+ * @param       mtd             MTD structure for the NAND Flash
+ * @param       command         command for NAND Flash
+ * @param       column          column offset for the page read
+ * @param       page_addr       page to be read from NAND Flash
+ */
+static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
+			     int column, int page_addr)
+{
+	bool useirq = false;
+
+	MTDDEBUG(MTD_DEBUG_LEVEL3,
+		 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
+		 command, column, page_addr);
+
+	/*
+	 * Reset command state information
+	 */
+	g_nandfc_info.bStatusRequest = false;
+
+	/*
+	 * Command pre-processing step
+	 */
+	switch (command) {
+
+	case NAND_CMD_STATUS:
+		g_nandfc_info.colAddr = 0;
+		g_nandfc_info.bStatusRequest = true;
+		break;
+
+	case NAND_CMD_READ0:
+		g_nandfc_info.colAddr = column;
+		g_nandfc_info.bSpareOnly = false;
+		useirq = false;
+		break;
+
+	case NAND_CMD_READOOB:
+		g_nandfc_info.colAddr = column;
+		g_nandfc_info.bSpareOnly = true;
+		useirq = false;
+		if (is2k_Pagesize)
+			command = NAND_CMD_READ0; /* only READ0 is valid */
+		break;
+
+	case NAND_CMD_SEQIN:
+		if (column >= mtd->writesize) {
+			if (is2k_Pagesize) {
+				/*
+				 * FIXME: before send SEQIN command for
+				 * write OOB, we must read one page out.
+				 * For K9F1GXX has no READ1 command to set
+				 * current HW pointer to spare area, we must
+				 * write the whole page including OOB
+				 * together.
+				 */
+				/* call itself to read a page */
+				mxc_nand_command(mtd, NAND_CMD_READ0, 0,
+						 page_addr);
+			}
+			g_nandfc_info.colAddr = column - mtd->writesize;
+			g_nandfc_info.bSpareOnly = true;
+			/* Set program pointer to spare region */
+			if (!is2k_Pagesize)
+				send_cmd(NAND_CMD_READOOB, false);
+		} else {
+			g_nandfc_info.bSpareOnly = false;
+			g_nandfc_info.colAddr = column;
+			/* Set program pointer to page start */
+			if (!is2k_Pagesize)
+				send_cmd(NAND_CMD_READ0, false);
+		}
+		useirq = false;
+		break;
+
+	case NAND_CMD_PAGEPROG:
+#ifndef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2
+		if (Ecc_disabled) {
+			/* Enable Ecc for page writes */
+			NFC_CONFIG1 |= NFC_ECC_EN;
+		}
+#endif
+		send_prog_page(0, g_nandfc_info.bSpareOnly);
+
+		if (is2k_Pagesize) {
+			/* data in 4 areas datas */
+			send_prog_page(1, g_nandfc_info.bSpareOnly);
+			send_prog_page(2, g_nandfc_info.bSpareOnly);
+			send_prog_page(3, g_nandfc_info.bSpareOnly);
+		}
+
+		break;
+
+	case NAND_CMD_ERASE1:
+		useirq = false;
+		break;
+	}
+
+	/*
+	 * Write out the command to the device.
+	 */
+	send_cmd(command, useirq);
+
+	/*
+	 * Write out column address, if necessary
+	 */
+	if (column != -1) {
+		/*
+		 * MXC NANDFC can only perform full page+spare or
+		 * spare-only read/write.  When the upper layers
+		 * layers perform a read/write buf operation,
+		 * we will used the saved column adress to index into
+		 * the full page.
+		 */
+		send_addr(0, page_addr == -1);
+		if (is2k_Pagesize)
+			/* another col addr cycle for 2k page */
+			send_addr(0, false);
+	}
+
+	/*
+	 * Write out page address, if necessary
+	 */
+	if (page_addr != -1) {
+		/* paddr_0 - p_addr_7 */
+		send_addr((page_addr & 0xff), false);
+
+		if (is2k_Pagesize) {
+			/* One more address cycle for higher
+			 * density devices */
+
+			if (mtd->size >= 0x10000000) {
+				/* paddr_8 - paddr_15 */
+				send_addr((page_addr >> 8) & 0xff, false);
+				send_addr((page_addr >> 16) & 0xff, true);
+			} else
+				/* paddr_8 - paddr_15 */
+				send_addr((page_addr >> 8) & 0xff, true);
+		} else {
+			/* One more address cycle for higher
+			 * density devices */
+
+			if (mtd->size >= 0x4000000) {
+				/* paddr_8 - paddr_15 */
+				send_addr((page_addr >> 8) & 0xff, false);
+				send_addr((page_addr >> 16) & 0xff, true);
+			} else
+				/* paddr_8 - paddr_15 */
+				send_addr((page_addr >> 8) & 0xff, true);
+		}
+	}
+
+	/*
+	 * Command post-processing step
+	 */
+	switch (command) {
+
+	case NAND_CMD_RESET:
+		break;
+
+	case NAND_CMD_READOOB:
+	case NAND_CMD_READ0:
+		if (is2k_Pagesize) {
+			/* send read confirm command */
+			send_cmd(NAND_CMD_READSTART, true);
+			/* read for each AREA */
+			send_read_page(0, g_nandfc_info.bSpareOnly);
+			send_read_page(1, g_nandfc_info.bSpareOnly);
+			send_read_page(2, g_nandfc_info.bSpareOnly);
+			send_read_page(3, g_nandfc_info.bSpareOnly);
+		} else
+			send_read_page(0, g_nandfc_info.bSpareOnly);
+		break;
+
+	case NAND_CMD_READID:
+		send_read_id();
+		break;
+
+	case NAND_CMD_PAGEPROG:
+#ifndef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2
+		if (Ecc_disabled) {
+			/* Disable Ecc after page writes */
+			NFC_CONFIG1 &= ~NFC_ECC_EN;
+		}
+#endif
+		break;
+
+	case NAND_CMD_STATUS:
+		break;
+
+	case NAND_CMD_ERASE2:
+		break;
+	}
+}
+
+static int mxc_nand_scan_bbt(struct mtd_info *mtd)
+{
+	struct nand_chip *this = mtd->priv;
+
+	/* Config before scanning */
+	/* Do not rely on NFMS_BIT, set/clear NFMS bit based
+	 * on mtd->writesize */
+	if (mtd->writesize == 2048) {
+		NFMS |= 1 << NFMS_BIT;
+		is2k_Pagesize = 1;
+	} else {
+		if ((NFMS >> NFMS_BIT) & 0x1) {
+			/* This case has happened on some SoCs */
+			printk(KERN_INFO
+			       "NFMS Bit set for 512B Page, resetting it."
+			       " [RCSR: 0x%08x]\n",
+			       NFMS);
+			NFMS &= ~(1 << NFMS_BIT);
+		}
+		is2k_Pagesize = 0;
+	}
+
+	if (is2k_Pagesize)
+		this->ecc.layout = &nand_hw_eccoob_2k;
+
+	/* use flash based bbt */
+	this->bbt_td = &bbt_main_descr;
+	this->bbt_md = &bbt_mirror_descr;
+
+	/* update flash based bbt */
+	this->options |= NAND_USE_FLASH_BBT;
+
+	if (!this->badblock_pattern) {
+		if (mtd->writesize == 2048)
+			this->badblock_pattern = &smallpage_memorybased;
+		else
+			this->badblock_pattern = (mtd->writesize > 512) ?
+			    &largepage_memorybased : &smallpage_memorybased;
+	}
+	/* Build bad block table */
+	return nand_scan_bbt(mtd, this->badblock_pattern);
+}
+
+#ifdef CONFIG_MXC_NAND_LOW_LEVEL_ERASE
+static void mxc_low_erase(struct mtd_info *mtd)
+{
+	struct nand_chip *this = mtd->priv;
+	unsigned int page_addr, addr;
+	u_char status;
+
+	MTDDEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : mxc_low_erase:Erasing NAND\n");
+	for (addr = 0; addr < this->chipsize; addr += mtd->erasesize) {
+		page_addr = addr / mtd->writesize;
+		mxc_nand_command(mtd, NAND_CMD_ERASE1, -1, page_addr);
+		mxc_nand_command(mtd, NAND_CMD_ERASE2, -1, -1);
+		mxc_nand_command(mtd, NAND_CMD_STATUS, -1, -1);
+		status = mxc_nand_read_byte(mtd);
+		if (status & NAND_STATUS_FAIL) {
+			printk(KERN_ERR
+			       "ERASE FAILED(block = %d,status = 0x%x)\n",
+			       addr / mtd->erasesize, status);
+		}
+	}
+
+}
+#endif
+
+int board_nand_init(struct nand_chip *nand)
+{
+	struct nand_chip *this;
+	struct mtd_info *mtd;
+
+	mxc_nand_data = malloc(sizeof(struct mxc_mtd_s));
+	if (!mxc_nand_data) {
+		printf("mxc_nd: No memory from malloc!\n");
+		return -1;
+	}
+	memset(mxc_nand_data, 0, sizeof(struct mxc_mtd_s));
+
+	memset((char *)&g_nandfc_info, 0, sizeof(g_nandfc_info));
+
+	this = nand;
+	mtd = &mxc_nand_data->mtd;
+	mtd->priv = this;
+	this->priv = mxc_nand_data;
+
+	/* 50 us command delay time */
+	this->chip_delay = 5;
+
+	this->dev_ready = mxc_nand_dev_ready;
+	this->cmdfunc = mxc_nand_command;
+	this->select_chip = mxc_nand_select_chip;
+	this->read_byte = mxc_nand_read_byte;
+	this->read_word = mxc_nand_read_word;
+	this->write_buf = mxc_nand_write_buf;
+	this->read_buf = mxc_nand_read_buf;
+	this->verify_buf = mxc_nand_verify_buf;
+	this->scan_bbt = mxc_nand_scan_bbt;
+
+	NFC_CONFIG1 |= NFC_INT_MSK;
+
+	if (hardware_ecc) {
+		this->ecc.calculate = mxc_nand_calculate_ecc;
+		this->ecc.hwctl = mxc_nand_enable_hwecc;
+		this->ecc.correct = mxc_nand_correct_data;
+		this->ecc.mode = NAND_ECC_HW;
+		this->ecc.layout = &nand_hw_eccoob_8;
+		this->ecc.size = 512;
+		this->ecc.bytes = 3;
+		NFC_CONFIG1 |= NFC_ECC_EN;
+	} else
+		this->ecc.mode = NAND_ECC_SOFT;
+
+	/* Reset NAND */
+	this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+
+	/* Unlock the internal RAM buffer */
+	NFC_CONFIG = 0x2;
+
+	/* Block to be unlocked */
+	NFC_UNLOCKSTART_BLKADDR = 0x0;
+	NFC_UNLOCKEND_BLKADDR = 0x4000;
+
+	/* Unlock Block Command for given address range */
+	NFC_WRPROT = 0x4;
+
+	/* Only 8 bit bus support for now */
+	this->options |= 0;
+
+	if ((NFMS >> NFMS_BIT) & 1) {
+		is2k_Pagesize = 1;
+		this->ecc.layout = &nand_hw_eccoob_2k;
+	} else
+		is2k_Pagesize = 0;
+
+	return 0;
+}
+
diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h
index 769c1e8..0f5378b 100644
--- a/include/asm-arm/arch-mx31/mx31-regs.h
+++ b/include/asm-arm/arch-mx31/mx31-regs.h
@@ -174,9 +174,94 @@
 #define NFC_BASE_ADDR	0xB8000000
 
 /*
+ * Addresses for NFC registers
+ */
+#define NFC_BUF_SIZE            (*((volatile u16 *)(NFC_BASE_ADDR + 0xE00)))
+#define NFC_BUF_ADDR            (*((volatile u16 *)(NFC_BASE_ADDR + 0xE04)))
+#define NFC_FLASH_ADDR          (*((volatile u16 *)(NFC_BASE_ADDR + 0xE06)))
+#define NFC_FLASH_CMD           (*((volatile u16 *)(NFC_BASE_ADDR + 0xE08)))
+#define NFC_CONFIG              (*((volatile u16 *)(NFC_BASE_ADDR + 0xE0A)))
+#define NFC_ECC_STATUS_RESULT   (*((volatile u16 *)(NFC_BASE_ADDR + 0xE0C)))
+#define NFC_RSLTMAIN_AREA       (*((volatile u16 *)(NFC_BASE_ADDR + 0xE0E)))
+#define NFC_RSLTSPARE_AREA      (*((volatile u16 *)(NFC_BASE_ADDR + 0xE10)))
+#define NFC_WRPROT              (*((volatile u16 *)(NFC_BASE_ADDR + 0xE12)))
+#define NFC_UNLOCKSTART_BLKADDR (*((volatile u16 *)(NFC_BASE_ADDR + 0xE14)))
+#define NFC_UNLOCKEND_BLKADDR   (*((volatile u16 *)(NFC_BASE_ADDR + 0xE16)))
+#define NFC_NF_WRPRST           (*((volatile u16 *)(NFC_BASE_ADDR + 0xE18)))
+#define NFC_CONFIG1             (*((volatile u16 *)(NFC_BASE_ADDR + 0xE1A)))
+#define NFC_CONFIG2             (*((volatile u16 *)(NFC_BASE_ADDR + 0xE1C)))
+
+/*
+ * Addresses for NFC RAM BUFFER Main area 0
+ */
+#define MAIN_AREA0        (volatile u16 *)(NFC_BASE_ADDR + 0x000)
+#define MAIN_AREA1        (volatile u16 *)(NFC_BASE_ADDR + 0x200)
+#define MAIN_AREA2        (volatile u16 *)(NFC_BASE_ADDR + 0x400)
+#define MAIN_AREA3        (volatile u16 *)(NFC_BASE_ADDR + 0x600)
+
+/*
+ * Addresses for NFC SPARE BUFFER Spare area 0
+ */
+#define SPARE_AREA0       (volatile u16 *)(NFC_BASE_ADDR + 0x800)
+#define SPARE_AREA1       (volatile u16 *)(NFC_BASE_ADDR + 0x810)
+#define SPARE_AREA2       (volatile u16 *)(NFC_BASE_ADDR + 0x820)
+#define SPARE_AREA3       (volatile u16 *)(NFC_BASE_ADDR + 0x830)
+
+/*
+ * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register for Command
+ * operation
+ */
+#define NFC_CMD            0x1
+
+/*
+ * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register for Address
+ * operation
+ */
+#define NFC_ADDR           0x2
+
+/*
+ * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register for Input
+ * operation
+ */
+#define NFC_INPUT          0x4
+
+/*
+ * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register for Data
+ * Output operation
+ */
+#define NFC_OUTPUT         0x8
+
+/*
+ * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register for Read ID
+ * operation
+ */
+#define NFC_ID             0x10
+
+/*
+ * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register for Read
+ * Status operation
+ */
+#define NFC_STATUS         0x20
+
+/*
+ * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read Status
+ * operation
+ */
+#define NFC_INT            0x8000
+
+#define NFC_SP_EN           (1 << 2)
+#define NFC_ECC_EN          (1 << 3)
+#define NFC_INT_MSK         (1 << 4)
+#define NFC_BIG             (1 << 5)
+#define NFC_RST             (1 << 6)
+#define NFC_CE              (1 << 7)
+#define NFC_ONE_CYCLE       (1 << 8)
+
+/*
  * NFMS bit in RCSR register for pagesize of nandflash
  */
 #define NFMS (*((volatile u32 *)CCM_RCSR))
 #define NFMS_BIT 30
 
 #endif /* __ASM_ARCH_MX31_REGS_H */
+
-- 
1.5.2.4

[U-Boot] [PATCH v2 4/6] i.MX31: Add NAND support in the i.MX31 Litekit config file.

[Magnus Lilja]

Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
---
 include/configs/imx31_litekit.h |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h
index c476333..493ec8e 100644
--- a/include/configs/imx31_litekit.h
+++ b/include/configs/imx31_litekit.h
@@ -36,6 +36,8 @@
 #define CONFIG_MX31_HCLK_FREQ	26000000
 #define CONFIG_MX31_CLK32	32000
 
+#define CONFIG_MX31_NAND	1
+
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
@@ -87,6 +89,8 @@
 #define CONFIG_CMD_SPI
 #define CONFIG_CMD_DATE
 
+#define CONFIG_CMD_NAND
+
 #define CONFIG_BOOTDELAY	3
 
 #define CONFIG_NETMASK		255.255.255.0
@@ -172,4 +176,12 @@
 #undef CONFIG_JFFS2_CMDLINE
 #define CONFIG_JFFS2_DEV	"nor0"
 
+/*
+ * NAND flash
+ */
+
+#define NAND_MAX_CHIPS		1
+#define CFG_MAX_NAND_DEVICE	1
+#define CFG_NAND_BASE		0x40000000
+
 #endif /* __CONFIG_H */
-- 
1.5.2.4

[U-Boot] [PATCH v2 5/6] i.MX31: Make the SPI bus and chip select configurable for MC13783

[Magnus Lilja]

The i.MX31 has three SPI buses and each bus has several chip selects
and the MC13783 chip can be connected to any of these. The current
RTC driver for MC13783 is hardcoded for CSPI2/SS2.

This patch makes make MC13783 SPI bus and chip select configurable
via CONFIG_MC13783_SPI_BUS and CONFIG_MC13783_SPI_CS.

Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
---
 drivers/rtc/mc13783-rtc.c       |    6 ++++--
 include/configs/imx31_litekit.h |    3 +++
 include/configs/mx31ads.h       |    3 +++
 3 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/rtc/mc13783-rtc.c b/drivers/rtc/mc13783-rtc.c
index b6e1501..38ef3aa 100644
--- a/drivers/rtc/mc13783-rtc.c
+++ b/drivers/rtc/mc13783-rtc.c
@@ -34,7 +34,8 @@ int rtc_get(struct rtc_time *rtc)
 
 	if (!slave) {
 		/* FIXME: Verify the max SCK rate */
-		slave = spi_setup_slave(1, 0, 1000000,
+		slave = spi_setup_slave(CONFIG_MC13783_SPI_BUS,
+				CONFIG_MC13783_SPI_CS, 1000000,
 				SPI_MODE_2 | SPI_CS_HIGH);
 		if (!slave)
 			return -1;
@@ -83,7 +84,8 @@ void rtc_set(struct rtc_time *rtc)
 
 	if (!slave) {
 		/* FIXME: Verify the max SCK rate */
-		slave = spi_setup_slave(1, 0, 1000000,
+		slave = spi_setup_slave(CONFIG_MC13783_SPI_BUS,
+				CONFIG_MC13783_SPI_CS, 1000000,
 				SPI_MODE_2 | SPI_CS_HIGH);
 		if (!slave)
 			return;
diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h
index 493ec8e..da155cf 100644
--- a/include/configs/imx31_litekit.h
+++ b/include/configs/imx31_litekit.h
@@ -71,6 +71,9 @@
 #define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_2 | SPI_CS_HIGH)
 
 #define CONFIG_RTC_MC13783	1
+/* MC13783 connected to CSPI2 and SS0 */
+#define CONFIG_MC13783_SPI_BUS	1
+#define CONFIG_MC13783_SPI_CS	0
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h
index 9ede764..b9ad3e4 100644
--- a/include/configs/mx31ads.h
+++ b/include/configs/mx31ads.h
@@ -66,6 +66,9 @@
 #define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_2 | SPI_CS_HIGH)
 
 #define CONFIG_RTC_MC13783	1
+/* MC13783 connected to CSPI2 and SS0 */
+#define CONFIG_MC13783_SPI_BUS	1
+#define CONFIG_MC13783_SPI_CS	0
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
-- 
1.5.2.4

[U-Boot] [PATCH v2 6/6] i.MX31: Add basic support for Freescale's i.MX31 PDK board.

[Magnus Lilja]

Add support for NAND and ethernet on the Freescale i.MX31 PDK (a.k.a.
3DS) board.

Booting from NAND is not supported yet so U-boot relies on some other
initial boot loader to set up SDRAM and clocks and copying U-boot to SDRAM.

Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
---
 MAKEALL                                 |    1 +
 Makefile                                |    3 +
 board/freescale/mx31pdk/Makefile        |   53 +++++++++
 board/freescale/mx31pdk/config.mk       |    1 +
 board/freescale/mx31pdk/lowlevel_init.S |   30 +++++
 board/freescale/mx31pdk/mx31pdk.c       |   76 +++++++++++++
 board/freescale/mx31pdk/u-boot.lds      |   59 ++++++++++
 include/configs/mx31pdk.h               |  181 +++++++++++++++++++++++++++++++
 8 files changed, 404 insertions(+), 0 deletions(-)

diff --git a/MAKEALL b/MAKEALL
index ad68152..b03e86e 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -518,6 +518,7 @@ LIST_ARM11="		\
 	imx31_litekit	\
 	imx31_phycore	\
 	mx31ads		\
+	mx31pdk		\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index 00ae9ca..237cf64 100644
--- a/Makefile
+++ b/Makefile
@@ -2734,6 +2734,9 @@ imx31_phycore_config	: unconfig
 mx31ads_config		: unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads freescale mx31
 
+mx31pdk_config		: unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm1136 mx31pdk freescale mx31
+
 omap2420h4_config	: unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx
 
diff --git a/board/freescale/mx31pdk/Makefile b/board/freescale/mx31pdk/Makefile
new file mode 100644
index 0000000..6ae34ea
--- /dev/null
+++ b/board/freescale/mx31pdk/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= mx31pdk.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mx31pdk/config.mk b/board/freescale/mx31pdk/config.mk
new file mode 100644
index 0000000..d34dc02
--- /dev/null
+++ b/board/freescale/mx31pdk/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x87f00000
diff --git a/board/freescale/mx31pdk/lowlevel_init.S b/board/freescale/mx31pdk/lowlevel_init.S
new file mode 100644
index 0000000..a94ea7f
--- /dev/null
+++ b/board/freescale/mx31pdk/lowlevel_init.S
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This is just to keep the linker happy.
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+	mov	pc, lr
+
diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c
new file mode 100644
index 0000000..9eed979
--- /dev/null
+++ b/board/freescale/mx31pdk/mx31pdk.c
@@ -0,0 +1,76 @@
+/*
+ *
+ * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* CS5: CPLD incl. network controller */
+	__REG(CSCR_U(5)) = 0x0000d843;
+	__REG(CSCR_L(5)) = 0x22252521;
+	__REG(CSCR_A(5)) = 0x22220a00;
+
+	/* setup pins for UART1 */
+	mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
+	mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
+	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
+	mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
+
+	/* SPI2 */
+	mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
+	mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
+	mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
+	mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
+	mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
+	mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
+	mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
+
+	/* start SPI2 clock */
+	__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
+
+	gd->bd->bi_arch_number = MACH_TYPE_MX31_3DS; /* board id for linux */
+	gd->bd->bi_boot_params = 0x80000100; /* adress of boot parameters */
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("Board: i.MX31 MAX PDK (3DS)\n");
+	return 0;
+}
diff --git a/board/freescale/mx31pdk/u-boot.lds b/board/freescale/mx31pdk/u-boot.lds
new file mode 100644
index 0000000..1460adc
--- /dev/null
+++ b/board/freescale/mx31pdk/u-boot.lds
@@ -0,0 +1,59 @@
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	   :
+	{
+	  cpu/arm1136/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
new file mode 100644
index 0000000..b511e36
--- /dev/null
+++ b/include/configs/mx31pdk.h
@@ -0,0 +1,181 @@
+/*
+ * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
+ *
+ * (C) Copyright 2004
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Kshitij Gupta <kshitij@ti.com>
+ *
+ * Configuration settings for the Freescale i.MX31 PDK board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx31-regs.h>
+
+/* High Level Configuration Options */
+#define CONFIG_ARM1136		1    /* This is an arm1136 CPU core */
+#define CONFIG_MX31		1    /* in a mx31 */
+#define CONFIG_MX31_HCLK_FREQ	26000000
+#define CONFIG_MX31_CLK32	32768
+
+#define CONFIG_MX31_NAND		1
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_CMDLINE_TAG		1    /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+/* No support for NAND boot for i.MX31 PDK yet, so we rely on some other
+ * program to initialize the SDRAM.
+ */
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * Size of malloc() pool
+ * An extra 128kbyte is needed for the NAND Bad Block table.
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024 + 128 * 1024)
+#define CFG_GBL_DATA_SIZE	128  /* bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_MX31_UART	1
+#define CFG_MX31_UART1		1
+
+#define CONFIG_HARD_SPI		1
+#define CONFIG_MXC_SPI		1
+#define CONFIG_MXC_SPI_IFACE	1
+#define CONFIG_DEFAULT_SPI_BUS	1
+#define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_2 | SPI_CS_HIGH)
+
+#define CONFIG_RTC_MC13783	1
+
+/* MC13783 connected to CSPI2 and SS2 */
+#define CONFIG_MC13783_SPI_BUS	1
+#define CONFIG_MC13783_SPI_CS	2
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_DATE
+
+#define CONFIG_CMD_NAND
+
+/* Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require
+ * that CFG_NO_FLASH is undefined).
+ */
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY	3
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"bootargs_base=setenv bootargs console=ttymxc0,115200\0"	\
+	"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs "	\
+		"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"	\
+	"bootcmd=run bootcmd_net\0"					\
+	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; "	\
+		"tftpboot 0x81000000 uImage-mx31; bootm\0"
+
+#define CONFIG_DRIVER_SMC911X		1
+#define CONFIG_DRIVER_SMC911X_BASE	CS5_BASE
+#define CONFIG_DRIVER_SMC911X_32_BIT	1
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP		/* undef to save memory */
+#define CFG_PROMPT		"uboot> "
+#define CFG_CBSIZE		256  /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS		16          /* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE  /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START	PHYS_SDRAM_1  /* memtest works on */
+#define CFG_MEMTEST_END		0x10000
+
+#define CFG_LOAD_ADDR		0x81000000 /* default load address */
+
+#define CFG_HZ			CONFIG_MX31_CLK32
+
+#define CONFIG_CMDLINE_EDITING	1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		CSD0_BASE
+#define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+/* No NOR flash present */
+#define CFG_NO_FLASH		1
+
+/*
+ * NAND flash
+ */
+
+#define NAND_MAX_CHIPS		1
+#define CFG_MAX_NAND_DEVICE	1
+#define CFG_NAND_BASE		0x40000000
+
+/*
+ * Place U-boot environment right after the U-boot code.
+ */
+#define CFG_ENV_IS_IN_NAND	1
+#define CFG_ENV_OFFSET		0x40000
+/* CFG_ENV_SIZE has to be a multiple of the NAND block size */
+#define CFG_ENV_SIZE		(128 * 1024)
+
+/*
+ * JFFS2 partitions
+ */
+#define CONFIG_JFFS2_DEV	"nand0"
+
+#endif /* __CONFIG_H */
+
-- 
1.5.2.4

[U-Boot] [PATCH v2 3/6] i.MX31: Add i.MX31 NAND Flash Controller driver.

[Scott Wood]

On Mon, Aug 18, 2008 at 11:30:44AM +0200, Magnus Lilja wrote:
> +/* The bool type is used locally in this file, added for U-boot. */
> +typedef enum {false = 0, true = 1 } bool;

Please remove this.

> +struct nand_info {
> +	bool bSpareOnly;
> +	bool bStatusRequest;

No Hungarian notation.  noJavaCaps.

> +static struct nand_ecclayout nand_hw_eccoob_2k = {
> +	.eccbytes = 20,
> +	.eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
> +		   38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
> +	.oobfree = {
> +		{.offset = 0,
> +		 .length = 5},

Bytes 0 and 1 are not free (they're the bad block marker).  Byte 5 *is*
free.

> +		{.offset = 11,
> +		 .length = 10},

Length should be 11.

> +/* Define some generic bad / good block scan pattern which are used
> + * while scanning a device for factory marked good / bad blocks. */
> +static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
> +
> +static struct nand_bbt_descr smallpage_memorybased = {
> +	.options = NAND_BBT_SCAN2NDPAGE,
> +	.offs = 5,
> +	.len = 1,
> +	.pattern = scan_ff_pattern
> +};
> +
> +static struct nand_bbt_descr largepage_memorybased = {
> +	.options = 0,
> +	.offs = 0,
> +	.len = 2,
> +	.pattern = scan_ff_pattern
> +};
> +
> +/* Generic flash bbt decriptors */
> +static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
> +static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
> +
> +static struct nand_bbt_descr bbt_main_descr = {
> +	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
> +	    | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
> +	.offs = 0,
> +	.len = 4,
> +	.veroffs = 4,
> +	.maxblocks = 4,
> +	.pattern = bbt_pattern
> +};
> +
> +static struct nand_bbt_descr bbt_mirror_descr = {
> +	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
> +	    | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
> +	.offs = 0,
> +	.len = 4,
> +	.veroffs = 4,
> +	.maxblocks = 4,
> +	.pattern = mirror_pattern
> +};

Is there any reason the default layout can't be used?

> +/**
> + * This function will maintains state of single bit Error
> + * in Main & spare  area
> + *
> + * @param buf_id	Specify Internal RAM Buffer number (0-3)
> + * @param spare  	set to true if only spare area needs correction
> + */
> +static void mxc_nd_correct_ecc(u8 buf_id, bool spare)
> +{
> +#ifdef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2
> +	/* To maintain single bit error in previous page */
> +	static int lastErrMain, lastErrSpare;
> +#endif
> +	u16 value, ecc_status;
> +
> +	/* Read the ECC result */
> +	ecc_status = NFC_ECC_STATUS_RESULT;
> +	MTDDEBUG(MTD_DEBUG_LEVEL3,
> +		 "mxc_nd_correct_ecc (Ecc status=%x)\n", ecc_status);
> +
> +#ifdef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2

What is this ifdef for?  Please document.

> +/**
> + * This function requests the NANDFC to perform a read of the
> + * NAND device status and returns the current status.
> + *
> + * @return  device status
> + */
> +static u16 get_dev_status(void)
> +{
> +	volatile u16 *mainBuf = MAIN_AREA1;
> +	u32 store;
> +	u16 ret;
> +	/* Issue status request to NAND device */
> +
> +	/* store the main area1 first word, later do recovery */
> +	store = *((u32 *) mainBuf);
> +	/*
> +	 * NANDFC buffer 1 is used for device status to prevent
> +	 * corruption of read/write buffer on status requests.
> +	 */
> +	NFC_BUF_ADDR = 1;
> +
> +	/* Read status into main buffer */
> +	NFC_CONFIG1 &= ~NFC_SP_EN;
> +	NFC_CONFIG2 = NFC_STATUS;
> +
> +	/* Wait for operation to complete */
> +	wait_op_done(TROP_US_DELAY, 0, true);
> +
> +	/* Status is placed in first word of main buffer */
> +	/* get status, then recovery area 1 data */
> +	ret = mainBuf[0];
> +	*((u32 *) mainBuf) = store;

This cast violates C strict aliasing rules.  Use a union if you
absolutely must use a 32-bit access here.

> +static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
> +				  u_char *ecc_code)
> +{
> +	/*
> +	 * Just return success.  HW ECC does not read/write the NFC spare
> +	 * buffer.  Only the FLASH spare area contains the calcuated ECC.
> +	 */
> +	return 0;
> +}

Hmm, maybe you should implement write_page() instead.

You may want to do a read-back after write to fill in oob_poi.

> +/**
> + * This function reads byte from the NAND Flash
> + *
> + * @param       mtd     MTD structure for the NAND Flash
> + *
> + * @return    data read from the NAND Flash
> + */
> +static u_char mxc_nand_read_byte(struct mtd_info *mtd)
> +{
> +	u_char retVal = 0;
> +	u16 col, rdWord;
> +	volatile u16 *mainBuf = MAIN_AREA0;
> +	volatile u16 *spareBuf = SPARE_AREA0;
> +
> +	/* Check for status request */
> +	if (g_nandfc_info.bStatusRequest)
> +		return get_dev_status() & 0xFF;
> +
> +	/* Get column for 16-bit access */
> +	col = g_nandfc_info.colAddr >> 1;
> +
> +	/* If we are accessing the spare region */
> +	if (g_nandfc_info.bSpareOnly)
> +		rdWord = spareBuf[col];
> +	else
> +		rdWord = mainBuf[col];

I thought you could only do 32-bit accesses?

> +/**
> + * This function writes data of length \b len to buffer \b buf. The data
> + * to be written on NAND Flash is first copied to RAMbuffer. After the
> + * Data Input Operation by the NFC, the data is written to NAND Flash.
> + *
> + * @param       mtd     MTD structure for the NAND Flash
> + * @param       buf     data to be written to NAND Flash
> + * @param       len     number of bytes to be written
> + */
> +static void mxc_nand_write_buf(struct mtd_info *mtd,
> +			       const u_char *buf, int len)
> +{
> +	int n;
> +	int col;
> +	int i = 0;
> +
> +	MTDDEBUG(MTD_DEBUG_LEVEL3,
> +		 "mxc_nand_write_buf(col = %d, len = %d)\n",
> +		 g_nandfc_info.colAddr, len);
> +
> +	col = g_nandfc_info.colAddr;
> +
> +	/* Adjust saved column address */
> +	if (col < mtd->writesize && g_nandfc_info.bSpareOnly)
> +		col += mtd->writesize;
> +
> +	n = mtd->writesize + mtd->oobsize - col;
> +	n = min(len, n);

If len exceeds mtd->writesize + mtd->oobsize - col, then print an error,
don't silently clip it.

> +	MTDDEBUG(MTD_DEBUG_LEVEL3,
> +		 "%s:%d: col = %d, n = %d\n", __FUNCTION__, __LINE__, col, n);
> +
> +	while (n) {
> +		volatile u32 *p;
> +		if (col < mtd->writesize)
> +			p = (volatile u32 *)((ulong) (MAIN_AREA0) + (col & ~3));
> +		else
> +			p = (volatile u32 *)((ulong) (SPARE_AREA0) -
> +					     mtd->writesize + (col & ~3));
> +
> +		MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n",
> +			 __FUNCTION__, __LINE__, p);
> +
> +		if (((col | (int)&buf[i]) & 3) || n < 16) {

Don't cast pointers to "int"; use uintptr_t if you must cast to an
integer type.

> +			u32 data = 0;
> +
> +			if (col & 3 || n < 4)
> +				data = *p;
> +
> +			switch (col & 3) {
> +			case 0:
> +				if (n) {
> +					data = (data & 0xffffff00) |
> +					    (buf[i++] << 0);
> +					n--;
> +					col++;
> +				}

If this controller really insists on 32-bit accesses to the buffer
(yuck), and the requested access isn't aligned, then memcpy_32 the hw
buffer to a sw buffer, and do an ordinary memcpy from that to the
requested location.

For full page accesses, the buffer should be aligned, so the only likely
double-copy is for small OOB accesses, where the double copy doesn't
matter much.

Likewise in read_buf().

> +/**
> + * This function is used by the upper layer to verify the data in NAND Flash
> + * with the data in the \b buf.
> + *
> + * @param       mtd     MTD structure for the NAND Flash
> + * @param       buf     data to be verified
> + * @param       len     length of the data to be verified
> + *
> + * @return      -EFAULT if error else 0
> + */
> +static int
> +mxc_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
> +{
> +	return -1; /* Was -EFAULT */
> +}

Is there any particular reason you don't implement this?

> +/**
> + * This function is used by upper layer for select and deselect of the NAND
> + * chip.
> + *
> + * @param       mtd     MTD structure for the NAND Flash
> + * @param       chip    val indicating select or deselect
> + */
> +static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
> +{
> +#ifdef CONFIG_MTD_NAND_MXC_FORCE_CE

What does this option do, and why is it an option?

> +/**
> + * This function is used by the upper layer to write command to NAND Flash
> + * for different operations to be carried out on NAND Flash
> + *
> + * @param       mtd             MTD structure for the NAND Flash
> + * @param       command         command for NAND Flash
> + * @param       column          column offset for the page read
> + * @param       page_addr       page to be read from NAND Flash
> + */
> +static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
> +			     int column, int page_addr)
> +{
> +	bool useirq = false;

This is never set to anything but false.

> +	case NAND_CMD_SEQIN:
> +		if (column >= mtd->writesize) {
> +			if (is2k_Pagesize) {
> +				/*
> +				 * FIXME: before send SEQIN command for
> +				 * write OOB, we must read one page out.
> +				 * For K9F1GXX has no READ1 command to set
> +				 * current HW pointer to spare area, we must
> +				 * write the whole page including OOB
> +				 * together.

NACK.  Large page devices have a 2-byte column address; use that with
READ0 to select the OOB.

> +	/*
> +	 * Write out column address, if necessary
> +	 */
> +	if (column != -1) {
> +		/*
> +		 * MXC NANDFC can only perform full page+spare or
> +		 * spare-only read/write.  When the upper layers
> +		 * layers perform a read/write buf operation,
> +		 * we will used the saved column adress to index into
> +		 * the full page.
> +		 */
> +		send_addr(0, page_addr == -1);
> +		if (is2k_Pagesize)
> +			/* another col addr cycle for 2k page */
> +			send_addr(0, false);

In the spare-only case, the second address byte should be
"mtd->writesize >> 8" (or ">> 9" for 16-bit devices).

> +#ifdef CONFIG_MXC_NAND_LOW_LEVEL_ERASE
> +static void mxc_low_erase(struct mtd_info *mtd)
> +{
> +	struct nand_chip *this = mtd->priv;
> +	unsigned int page_addr, addr;
> +	u_char status;
> +
> +	MTDDEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : mxc_low_erase:Erasing NAND\n");
> +	for (addr = 0; addr < this->chipsize; addr += mtd->erasesize) {
> +		page_addr = addr / mtd->writesize;
> +		mxc_nand_command(mtd, NAND_CMD_ERASE1, -1, page_addr);
> +		mxc_nand_command(mtd, NAND_CMD_ERASE2, -1, -1);
> +		mxc_nand_command(mtd, NAND_CMD_STATUS, -1, -1);
> +		status = mxc_nand_read_byte(mtd);
> +		if (status & NAND_STATUS_FAIL) {
> +			printk(KERN_ERR
> +			       "ERASE FAILED(block = %d,status = 0x%x)\n",
> +			       addr / mtd->erasesize, status);
> +		}
> +	}
> +
> +}
> +#endif

What is this for?  Where is it called?

> +	memset((char *)&g_nandfc_info, 0, sizeof(g_nandfc_info));

Unnecessary cast -- and unnecessary memset.

> +	this = nand;

Why not just refer to it as "nand", or rename the parameter "this"?

> +	mtd = &mxc_nand_data->mtd;
> +	mtd->priv = this;
> +	this->priv = mxc_nand_data;
> +
> +	/* 50 us command delay time */
> +	this->chip_delay = 5;

I don't think you need chip_delay if you implement cmdfunc and dev_ready.

-Scott

[U-Boot] [PATCH v2 1/6] i.MX31: Add NFC_BASE_ADDR definition.

[Jean-Christophe PLAGNIOL-VILLARD]

On 11:30 Mon 18 Aug     , Magnus Lilja wrote:
> Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
> ---
>  include/asm-arm/arch-mx31/mx31-regs.h |   11 +++++++++++
>  1 files changed, 11 insertions(+), 0 deletions(-)
> 
> diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h
> index b04a718..769c1e8 100644
> --- a/include/asm-arm/arch-mx31/mx31-regs.h
> +++ b/include/asm-arm/arch-mx31/mx31-regs.h
> @@ -168,4 +168,15 @@
>  #define CS5_BASE	0xB6000000
>  #define PCMCIA_MEM_BASE	0xC0000000
>  
> +/*
> + * NAND controller
> + */
> +#define NFC_BASE_ADDR	0xB8000000
> +
> +/*
> + * NFMS bit in RCSR register for pagesize of nandflash
> + */
> +#define NFMS (*((volatile u32 *)CCM_RCSR))
> +#define NFMS_BIT 30
I'll prefer to align it

it's more readable IMHO

Best Regards,
J.

[U-Boot] [PATCH v2 2/6] i.MX31: Add reset_timer() and modify get_timer_masked().

[Jean-Christophe PLAGNIOL-VILLARD]

On 11:30 Mon 18 Aug     , Magnus Lilja wrote:
> This patch adds the reset_timer() function (needed by nand_base.c) and
> modifies the get_timer_masked() to work in the same way as the omap24xx
> function.
> 
> Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
> ---
>  cpu/arm1136/mx31/interrupts.c |   22 ++++++++++++++++++----
>  1 files changed, 18 insertions(+), 4 deletions(-)
Could you add the comment like omap24xx?

Best Regards,
J.

[U-Boot] [PATCH v2 1/6] i.MX31: Add NFC_BASE_ADDR definition.

[Magnus Lilja]

Hi

2008/8/18 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>:
> On 11:30 Mon 18 Aug     , Magnus Lilja wrote:
>> Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
>> ---
>>  include/asm-arm/arch-mx31/mx31-regs.h |   11 +++++++++++
>>  1 files changed, 11 insertions(+), 0 deletions(-)
>>
>> diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h
>> index b04a718..769c1e8 100644
>> --- a/include/asm-arm/arch-mx31/mx31-regs.h
>> +++ b/include/asm-arm/arch-mx31/mx31-regs.h
>> @@ -168,4 +168,15 @@
>>  #define CS5_BASE     0xB6000000
>>  #define PCMCIA_MEM_BASE      0xC0000000
>>
>> +/*
>> + * NAND controller
>> + */
>> +#define NFC_BASE_ADDR        0xB8000000
>> +
>> +/*
>> + * NFMS bit in RCSR register for pagesize of nandflash
>> + */
>> +#define NFMS (*((volatile u32 *)CCM_RCSR))
>> +#define NFMS_BIT 30
> I'll prefer to align it
>
> it's more readable IMHO

I'll change that.

Thanks, Magnus

[U-Boot] [PATCH v2 2/6] i.MX31: Add reset_timer() and modify get_timer_masked().

[Magnus Lilja]

Hi

2008/8/18 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>:
> On 11:30 Mon 18 Aug     , Magnus Lilja wrote:
>> This patch adds the reset_timer() function (needed by nand_base.c) and
>> modifies the get_timer_masked() to work in the same way as the omap24xx
>> function.
>>
>> Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
>> ---
>>  cpu/arm1136/mx31/interrupts.c |   22 ++++++++++++++++++----
>>  1 files changed, 18 insertions(+), 4 deletions(-)
> Could you add the comment like omap24xx?

Hmm, I probably could but I'm not sure that I understand what you mean
here. Shall I add a comment to the patch description or to the code
itself? The patch description mentions omap24xx already.

Thanks, Magnus

[U-Boot] [PATCH v2 2/6] i.MX31: Add reset_timer() and modify get_timer_masked().

[Jean-Christophe PLAGNIOL-VILLARD]

On 10:55 Tue 19 Aug     , Magnus Lilja wrote:
> Hi
> 
> 2008/8/18 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>:
> > On 11:30 Mon 18 Aug     , Magnus Lilja wrote:
> >> This patch adds the reset_timer() function (needed by nand_base.c) and
> >> modifies the get_timer_masked() to work in the same way as the omap24xx
> >> function.
> >>
> >> Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
> >> ---
> >>  cpu/arm1136/mx31/interrupts.c |   22 ++++++++++++++++++----
> >>  1 files changed, 18 insertions(+), 4 deletions(-)
> > Could you add the comment like omap24xx?
> 
> Hmm, I probably could but I'm not sure that I understand what you mean
> here. Shall I add a comment to the patch description or to the code
> itself? The patch description mentions omap24xx already.

Just comment like done in the omap24xx interreupt

other the patch is OK

Best Regards,
J.

[U-Boot] [PATCH v2 5/6] i.MX31: Make the SPI bus and chip select configurable for MC13783

[Jean-Christophe PLAGNIOL-VILLARD]

On 11:30 Mon 18 Aug     , Magnus Lilja wrote:
> The i.MX31 has three SPI buses and each bus has several chip selects
> and the MC13783 chip can be connected to any of these. The current
> RTC driver for MC13783 is hardcoded for CSPI2/SS2.
> 
> This patch makes make MC13783 SPI bus and chip select configurable
> via CONFIG_MC13783_SPI_BUS and CONFIG_MC13783_SPI_CS.

Please add a readme about it in README.imx31 maybe.

Best Regards,
J.

[U-Boot] [PATCH v2 5/6] i.MX31: Make the SPI bus and chip select configurable for MC13783

[Magnus Lilja]

2008/8/19 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>:
> On 11:30 Mon 18 Aug     , Magnus Lilja wrote:
>> The i.MX31 has three SPI buses and each bus has several chip selects
>> and the MC13783 chip can be connected to any of these. The current
>> RTC driver for MC13783 is hardcoded for CSPI2/SS2.
>>
>> This patch makes make MC13783 SPI bus and chip select configurable
>> via CONFIG_MC13783_SPI_BUS and CONFIG_MC13783_SPI_CS.
>
> Please add a readme about it in README.imx31 maybe.

Ok, I'll create a doc/README.imx31 (as far as I can see it doesn't exist yet).

Thanks, Magnus

[U-Boot] [PATCH v2 0/6] i.MX31: Add NAND support and new PDK board.

[Jean-Christophe PLAGNIOL-VILLARD]

On 11:30 Mon 18 Aug     , Magnus Lilja wrote:
> Hi again
> 
> This series of patches adds support for the NAND flash controller in the
> i.MX31 device and also introduces the Freescale i.MX31 PDK board.
> 
> Changes since v1:
> 

Do you have any plans to send a V3 before the end of the merge window?

Best Regards,
J.

[U-Boot] [PATCH v2 0/6] i.MX31: Add NAND support and new PDK board.

[Magnus Lilja]

Hi

2008/8/28 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>:
> On 11:30 Mon 18 Aug     , Magnus Lilja wrote:
>> Hi again
>>
>> This series of patches adds support for the NAND flash controller in the
>> i.MX31 device and also introduces the Freescale i.MX31 PDK board.
>>
>> Changes since v1:
>>
>
> Do you have any plans to send a V3 before the end of the merge window?

Yes, I have implemented all comments that aren't related to the NAND
driver. I also re-ordered the patch series so all NAND and PDK related
patches are placed first in the series and those can be merged into
the ARM-tree without adding the NAND driver. This way other i.MX31
related patches that people have made on top of mine can be merged as
well, I seem to recall that someone fixed the CFG_HZ issue for i.MX31.

Regarding the NAND driver, I have implemented most of the coding style
related comments and removed un-unused functions, but some of Scott's
more detailed NAND driver issues have not been sorted out yet so I
don't know if the NAND driver will be ready before the merge window
closes. Since the PDK only has NAND flash I'm not sure if it is
meaningful to add the board without the NAND enabled.

I was planning to send V3 today but I won't be able to do that since I
wanted to at least make a quick test on hardware before submitting but
I hope to do that tomorrow.

Regards, Magnus