[U-Boot] [PATCH] 440spe MQ initialization

[Stefan Roese <sr@denx.de>]

Hi Yuri,

On Tuesday 23 September 2008, Yuri Tikhonov wrote:
>  Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC
> values. This fixes the occasional 440SPe hard locking issues when the
> 440SPe's dedicated DMA engines are used (e.g. by the h/w accelerated RAID
> driver).
>
>  Previously the appropriate initialization had been made in Linux, by the
> ppc440spe ADMA driver, which is wrong because modifying the MQ
> configuration registers after normal operation has begun is not supported
> and could have unpredictable results.

AMCC just recently updated the 440SP(e) MQ initialization with this patch:

commit 079589bcfb24ba11068460276a3cc9549ab5346f
Author: Prodyut  Hazarika <phazarika@amcc.com>
Date:   Wed Aug 20 09:38:51 2008 -0700

    ppc4xx: Optimize PLB4 Arbiter and Memory Queue settings for PPC440SP/SPe,
        PPC405EX and PPC460EX/GT/SX

    - Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX
      processors
    - Moved PLB4 Arbiter register definitions to ppc4xx.h since it is shared
      across processors (405 and 440/460)
    - Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX
      processors
    - Add register bit definitions for Memory Queue Configuration registers

    Signed-off-by: Prodyut Hazarika <phazarika@amcc.com>
    Signed-off-by: Stefan Roese <sr@denx.de>


I have a bad feeling changing this "optimized" settings without AMCC's 
specific ACK.

Prodyut, are you ok with Yuri's change?

Thanks.

Best regards,
Stefan

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