* [U-Boot] [PATCH 1/3] ppc4xx: Initial support of the AMCC dual PPC460GT Arches reference board.
@ 2008-09-24 8:11 Adam Graham
2008-09-24 12:09 ` Wolfgang Denk
2008-09-25 8:41 ` Stefan Roese
0 siblings, 2 replies; 5+ messages in thread
From: Adam Graham @ 2008-09-24 8:11 UTC (permalink / raw)
To: u-boot
These are the initial support files for the AMCC dual PPC460GT Arches reference board.
Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
---
Makefile | 3 +
board/amcc/arches/Makefile | 51 ++++
board/amcc/arches/arches.c | 356 +++++++++++++++++++++++++++++
board/amcc/arches/config.mk | 41 ++++
board/amcc/arches/init.S | 110 +++++++++
board/amcc/arches/u-boot.lds | 143 ++++++++++++
include/configs/amcc-common.h | 20 ++-
include/configs/arches.h | 505 +++++++++++++++++++++++++++++++++++++++++
include/ppc440.h | 3 +
9 files changed, 1231 insertions(+), 1 deletions(-)
create mode 100644 board/amcc/arches/Makefile
create mode 100644 board/amcc/arches/arches.c
create mode 100644 board/amcc/arches/config.mk
create mode 100644 board/amcc/arches/init.S
create mode 100644 board/amcc/arches/u-boot.lds
create mode 100644 include/configs/arches.h
diff --git a/Makefile b/Makefile
index 7c13ce8..2241290 100644
--- a/Makefile
+++ b/Makefile
@@ -1186,6 +1186,9 @@ APC405_config: unconfig
AR405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx ar405 esd
+arches_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx arches amcc
+
ASH405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx ash405 esd
diff --git a/board/amcc/arches/Makefile b/board/amcc/arches/Makefile
new file mode 100644
index 0000000..6b0c838
--- /dev/null
+++ b/board/amcc/arches/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2008
+# Stefan Roese, DENX Software Engineering, sr at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o
+SOBJS := init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/amcc/arches/arches.c b/board/amcc/arches/arches.c
new file mode 100644
index 0000000..34b6bb1
--- /dev/null
+++ b/board/amcc/arches/arches.c
@@ -0,0 +1,356 @@
+/*
+ * (C) Copyright 2008
+ * Adam Graham, Applied Micro Circuits Corp., agraham at amcc.com.
+ * Victor Gallardo, Applied Micro Circuits Corp., agraham at amcc.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/4xx_pcie.h>
+
+/*
+ * FPGA read/write helper macros
+ */
+#define FPGA_READ(offset) ({ \
+ in_8((void *)(CFG_FPGA_BASE + offset)); })
+#define FPGA_WRITE(offset, data) ({ \
+ out_8((void *)(CFG_FPGA_BASE + offset), data); })
+
+/*
+ * CPLD read/write helper macros
+ */
+#define CPLD_READ(offset) ({ \
+ out_8((void *)(CFG_CPLD_ADDR), offset); \
+ in_8((void *)(CFG_CPLD_DATA)); })
+#define CPLD_WRITE(offset, data) ({ \
+ out_8((void *)(CFG_CPLD_ADDR), offset); \
+ out_8((void *)(CFG_CPLD_DATA), data); })
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * Setup the interrupt controller polarities, triggers, etc.
+ */
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+ mtdcr(uic0er, 0x00000000); /* disable all */
+ mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
+ mtdcr(uic0pr, 0xffffffff); /* per ref-board manual */
+ mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
+ mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+ mtdcr(uic1er, 0x00000000); /* disable all */
+ mtdcr(uic1cr, 0x00000000); /* all non-critical */
+ mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
+ mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
+ mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic2sr, 0xffffffff); /* clear all */
+ mtdcr(uic2er, 0x00000000); /* disable all */
+ mtdcr(uic2cr, 0x00000000); /* all non-critical */
+ mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
+ mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
+ mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic2sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic3sr, 0xffffffff); /* clear all */
+ mtdcr(uic3er, 0x00000000); /* disable all */
+ mtdcr(uic3cr, 0x00000000); /* all non-critical */
+ mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */
+ mtdcr(uic3tr, 0x00000000); /* per ref-board manual */
+ mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic3sr, 0xffffffff); /* clear all */
+
+ /*
+ * Configure PFC (Pin Function Control) registers
+ * UART0: 4 pins
+ */
+ mtsdr(SDR0_PFC1, 0x00040000);
+
+ /* Enable PCI host functionality in SDR0_PCI0 */
+ mtsdr(SDR0_PCI0, 0xe0000000);
+
+ return 0;
+}
+
+u32 get_cpu_num(void)
+{
+ return FPGA_READ(3);
+}
+
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+
+ printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n");
+ printf(" Revision %02X.%02X ", FPGA_READ(0), FPGA_READ(1));
+
+ /* Only CPU0 has access to CPLD registers */
+ if (get_cpu_num() == 0)
+ printf("(FPGA=%02X, CPLD=%02X)\n", FPGA_READ(2), CPLD_READ(0));
+ else
+ printf("(FPGA=%02X, CPLD=xx)\n", FPGA_READ(2));
+
+ if (s != NULL)
+ printf(" Serial# %s\n", s);
+
+ return 0;
+}
+
+/*
+ * pci_target_init
+ *
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ */
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+ /*
+ * Disable everything
+ */
+ out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
+ out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
+ out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
+ out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
+
+ /*
+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
+ * strapping options to not support sizes such as 128/256 MB.
+ */
+ out_le32((void *)PCIX0_PIM0LAL, CFG_SDRAM_BASE);
+ out_le32((void *)PCIX0_PIM0LAH, 0);
+ out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
+ out_le32((void *)PCIX0_BAR0, 0);
+
+ /*
+ * Program the board's subsystem id/vendor id
+ */
+ out_le16((void *)PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
+ out_le16((void *)PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
+
+ out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+#if defined(CONFIG_PCI)
+/*
+ * is_pci_host
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ */
+int is_pci_host(struct pci_controller *hose)
+{
+ /* Board is always configured as host. */
+ return 1;
+}
+
+static struct pci_controller pcie_hose[2] = { {0}, {0} };
+
+void pcie_setup_hoses(int busno)
+{
+ struct pci_controller *hose;
+ int i, bus;
+ int ret = 0;
+ char *env;
+ unsigned int delay;
+ int end;
+
+ /*
+ * assume we're called after the PCIX hose is initialized, which takes
+ * bus ID 0 and therefore start numbering PCIe's from 1.
+ */
+ bus = busno;
+
+#if defined(CONFIG_RAPIDIO)
+ end = 0;
+#else
+ end = 1;
+#endif
+
+ for (i = 0; i <= end; i++) {
+
+ if (is_end_point(i))
+ ret = ppc4xx_init_pcie_endport(i);
+ else
+ ret = ppc4xx_init_pcie_rootport(i);
+ if (ret) {
+ printf("PCIE%d: initialization as %s failed\n", i,
+ is_end_point(i) ? "endpoint" : "root-complex");
+ continue;
+ }
+
+ hose = &pcie_hose[i];
+ hose->first_busno = bus;
+ hose->last_busno = bus;
+ hose->current_busno = bus;
+
+ /* setup mem resource */
+ pci_set_region(hose->regions + 0,
+ CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
+ CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
+ CFG_PCIE_MEMSIZE,
+ PCI_REGION_MEM);
+ hose->region_count = 1;
+ pci_register_hose(hose);
+
+ if (is_end_point(i)) {
+ ppc4xx_setup_pcie_endpoint(hose, i);
+ /*
+ * Reson for no scanning is endpoint can not generate
+ * upstream configuration accesses.
+ */
+ } else {
+ ppc4xx_setup_pcie_rootpoint(hose, i);
+ env = getenv("pciscandelay");
+ if (env != NULL) {
+ delay = simple_strtoul(env, NULL, 10);
+ if (delay > 5)
+ printf("Warning, expect noticable "
+ "delay before PCIe scan due "
+ "to 'pciscandelay' value!\n");
+ mdelay(delay * 1000);
+ }
+
+ /*
+ * Config access can only go down stream
+ */
+ hose->last_busno = pci_hose_scan(hose);
+ bus = hose->last_busno + 1;
+ }
+ }
+}
+#endif /* CONFIG_PCI */
+
+int board_early_init_r(void)
+{
+ /*
+ * Arches has 32MBytes of NOR FLASH (Spansion 29GL256), but the
+ * boot EBC mapping only supports a maximum of 16MBytes
+ * (4.ff00.0000 - 4.ffff.ffff).
+ * To solve this problem, the FLASH has to get remapped to another
+ * EBC address which accepts bigger regions:
+ *
+ * 0xfe00.0000 -> 4.ce00.0000
+ */
+
+ /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
+ mtebc(pb0cr, CFG_FLASH_BASE_PHYS_L | EBC_BXCR_BS_32MB |
+ EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
+
+ /* Remove TLB entry of boot EBC mapping */
+ remove_tlb(CFG_BOOT_BASE_ADDR, 16 << 20);
+
+ /* Add TLB entry for 0xfe00.0000 -> 0x4.ce00.0000 */
+ program_tlb(CFG_FLASH_BASE_PHYS, CFG_FLASH_BASE, CFG_FLASH_SIZE,
+ TLB_WORD2_I_ENABLE);
+
+ /*
+ * Now accessing of the whole 32Mbytes of NOR FLASH at virtual address
+ * 0xfe00.0000 is possible
+ */
+
+ /*
+ * Clear potential errors resulting from auto-calibration.
+ * If not done, then we could get an interrupt later on when
+ * exceptions are enabled.
+ */
+ set_mcsr(get_mcsr());
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ u32 eth_cfg = 0;
+ u32 eth_pll;
+ int timeout;
+
+ /*
+ * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
+ * This is board specific, so let's do it here.
+ */
+
+ /* enable SGMII mode */
+ eth_cfg |= (SDR0_ETH_CFG_SGMII0_ENABLE |
+ SDR0_ETH_CFG_SGMII1_ENABLE |
+ SDR0_ETH_CFG_SGMII2_ENABLE);
+
+ /* Set EMAC for MDIO */
+ eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
+
+ /* bypass the TAHOE0/TAHOE1 cores for U-Boot */
+ eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
+
+ mtsdr(SDR0_ETH_CFG, eth_cfg);
+
+ /* reset SGMII interface */
+ mtsdr(SDR0_SRST1, 0x00000380);
+ mtsdr(SDR0_ETH_STS, 0xFFFFFFFF);
+ mtsdr(SDR0_SRST1, 0x00000000);
+
+ for (timeout = 60; timeout > 0; timeout--) {
+ udelay(1000);
+ mfsdr(SDR0_ETH_PLL, eth_pll);
+ if ((eth_pll & 0x80000000) != 0)
+ break;
+ }
+
+ if (timeout == 0)
+ printf("timeout: while waiting for SGMII PLL lock\n");
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ u32 val[4];
+ int rc;
+
+ ft_cpu_setup(blob, bd);
+
+ /* Fixup NOR mapping */
+ val[0] = 0; /* chip select number */
+ val[1] = 0; /* always 0 */
+ val[2] = CFG_FLASH_BASE_PHYS_L; /* we fixed up this address */
+ val[3] = gd->bd->bi_flashsize;
+ rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
+ val, sizeof(val), 1);
+ if (rc)
+ printf("Unable to update property NOR mapping, err=%s\n",
+ fdt_strerror(rc));
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/amcc/arches/config.mk b/board/amcc/arches/config.mk
new file mode 100644
index 0000000..065e39e
--- /dev/null
+++ b/board/amcc/arches/config.mk
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2008
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# AMCC dual 460GT Evaluation Board (Arches) board
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xFFFA0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/amcc/arches/init.S b/board/amcc/arches/init.S
new file mode 100644
index 0000000..d53f044
--- /dev/null
+++ b/board/amcc/arches/init.S
@@ -0,0 +1,110 @@
+/*
+ * (C) Copyright 2008
+ * Adam Graham, Applied Micro Circuits Corp., agraham at amcc.com.
+ * Victor Gallardo, Applied Micro Circuits Corp., agraham at amcc.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm-ppc/mmu.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
+ * use the speed up boot process. It is patched after relocation to
+ * enable SA_I
+ */
+ tlbentry(CFG_BOOT_BASE_ADDR, SZ_16M, CFG_BOOT_BASE_ADDR,
+ 4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR(2) detection
+ * routine.
+ */
+
+#ifdef CFG_INIT_RAM_DCACHE
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR,
+ 0, AC_R|AC_W|AC_X|SA_G)
+#endif
+
+ tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC,
+ AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC,
+ AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD,
+ AC_R|AC_W|SA_G|SA_I)
+
+ tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD,
+ AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD,
+ AC_R|AC_W|SA_G|SA_I)
+
+#if defined(CONFIG_RAPIDIO)
+ /* TLB-entries for RapidIO (SRIO) */
+ tlbentry(CFG_SRGPL0_REG_BAR, SZ_16M, CFG_SRGPL0_REG_BAR,
+ 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_SRGPL0_CFG_BAR, SZ_16M, CFG_SRGPL0_CFG_BAR,
+ 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_SRGPL0_MNT_BAR, SZ_16M, CFG_SRGPL0_MNT_BAR,
+ 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_I2ODMA_BASE, SZ_1K, 0x00100000,
+ 0x4, AC_R|AC_W|SA_G|SA_I)
+#else
+ tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD,
+ AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD,
+ AC_R|AC_W|SA_G|SA_I)
+#endif
+
+ /* PCIe UTL register */
+ tlbentry(CFG_PCIE_BASE, SZ_16K, 0x08010000,
+ 0xC, AC_R|AC_W|SA_G|SA_I)
+
+ /* TLB-entry for FPGA */
+ tlbentry(CFG_FPGA_BASE, SZ_16M, CFG_FPGA_BASE,
+ 4, AC_R|AC_W|SA_G|SA_I)
+
+ /* TLB-entry for OCM */
+ tlbentry(CFG_OCM_BASE, SZ_64K, 0x00040000,
+ 4, AC_R|AC_W|AC_X|SA_I)
+
+ /* TLB-entry for Local Configuration registers => peripherals */
+ tlbentry(CFG_LOCAL_CONF_REGS, SZ_16M, CFG_LOCAL_CONF_REGS,
+ 4, AC_R|AC_W|AC_X|SA_G|SA_I)
+
+ tlbtab_end
diff --git a/board/amcc/arches/u-boot.lds b/board/amcc/arches/u-boot.lds
new file mode 100644
index 0000000..0a2e7a1
--- /dev/null
+++ b/board/amcc/arches/u-boot.lds
@@ -0,0 +1,143 @@
+/*
+ * (C) Copyright 2008
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ board/amcc/arches/init.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h
index 1f27d78..fb19e0d 100644
--- a/include/configs/amcc-common.h
+++ b/include/configs/amcc-common.h
@@ -55,6 +55,14 @@
#endif
/*
+ * Only very few boards have default netdev not set to eth0 (like Arches)
+ */
+#if !defined(CONFIG_NETDEV)
+#define CONFIG_NETDEV eth0
+#endif
+
+
+/*
* Commands
*/
#include <config_cmd_default.h>
@@ -147,9 +155,11 @@
/*
* Booting and default environment
*/
+#if !defined(CONFIG_PREBOOT)
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
+#endif
#define CONFIG_BOOTCOMMAND "run flash_self"
/*
@@ -184,7 +194,7 @@
* General common environment variables shared on all AMCC eval boards
*/
#define CONFIG_AMCC_DEF_ENV \
- "netdev=eth0\0" \
+ "netdev=" xstr(CONFIG_NETDEV) "\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
@@ -197,8 +207,10 @@
"initrd_high=30000000\0" \
"kernel_addr_r=400000\0" \
"fdt_addr_r=800000\0" \
+ "ramdisk_addr_r=C00000\0" \
"hostname=" xstr(CONFIG_HOSTNAME) "\0" \
"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
+ "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
CONFIG_AMCC_DEF_ENV_ROOTPATH
/*
@@ -214,6 +226,12 @@
"tftp ${fdt_addr_r} ${fdt_file}; " \
"run nfsargs addip addtty addmisc;" \
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
+ "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
+ "tftp ${fdt_addr_r} ${fdt_file};" \
+ "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
+ "net_self=run net_self_load;" \
+ "run ramargs addip addtty addmisc;" \
+ "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
"fdt_file=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0"
/*
diff --git a/include/configs/arches.h b/include/configs/arches.h
new file mode 100644
index 0000000..6ad862f
--- /dev/null
+++ b/include/configs/arches.h
@@ -0,0 +1,505 @@
+/*
+ * (C) Copyright 2008
+ * Adam Graham, Applied Micro Circuits Corp., agraham at amcc.com.
+ * Victor Gallardo, Applied Micro Circuits Corp., agraham at amcc.com.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * arches.h - configuration for Arches (460GT)
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+/* This config file is used for Arches (460GT) */
+#define CONFIG_ARCHES 1 /* Board is Arches */
+#define CONFIG_460GT 1 /* Specific PPC460GT */
+#define CONFIG_440 1
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_NETDEV eth1
+
+/*
+ * Update default PREBOOT environment variables
+ * defined in amcc-common.h
+ */
+#define CONFIG_PREBOOT \
+ "setenv ethact ppc_4xx_eth1;" \
+ "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo;"
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME arches
+#include "amcc-common.h"
+
+#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+#define CONFIG_BOARD_TYPES 1 /* support board types */
+
+/*-----------------------------------------------------------------------
+ * RapidIO I/O and Registers
+ *----------------------------------------------------------------------*/
+
+#define CONFIG_RAPIDIO
+#define CFG_460GT_SRIO_ERRATA_1
+
+#define SRGPL0_REG_BAR 0x0000000DAA000000ull /* 16MB */
+#define SRGPL0_CFG_BAR 0x0000000DAB000000ull /* 16MB */
+#define SRGPL0_MNT_BAR 0x0000000DAC000000ull /* 16MB */
+#define SRGPL0_MSG_BAR 0x0000000DAD000000ull /* 16MB */
+#define SRGPL0_OUT_BAR 0x0000000DB0000000ull /* 256MB */
+
+#define CFG_SRGPL0_REG_BAR 0xAA000000 /* 16MB */
+#define CFG_SRGPL0_CFG_BAR 0xAB000000 /* 16MB */
+#define CFG_SRGPL0_MNT_BAR 0xAC000000 /* 16MB */
+#define CFG_SRGPL0_MSG_BAR 0xAD000000 /* 16MB */
+
+#define CFG_I2ODMA_BASE 0xCF000000
+#define CFG_I2ODMA_PHYS_ADDR 0x0000000400100000ull
+
+#define CONFIG_PPC4XX_RAPIDIO_PROMISCUOUS_MODE
+#undef CONFIG_PPC4XX_RAPIDIO_DEBUG
+#undef CONFIG_PPC4XX_RAPIDIO_IN_BAR_USE_OCM
+#define CONFIG_PPC4XX_RAPIDIO_USE_HB_PLB
+#undef CONFIG_PPC4XX_RAPIDIO_LOOPBACK
+
+/* EBC stuff */
+#define CFG_NAND_ADDR 0xE0000000
+#define CFG_FPGA_BASE 0xE1000000
+#define CFG_CPLD_ADDR (CFG_FPGA_BASE + 0x00080000)
+#define CFG_CPLD_DATA (CFG_FPGA_BASE + 0x00080002)
+#define CFG_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space: 0xFF000000 */
+#define CFG_FLASH_BASE 0xFE000000 /* later mapped to this addr */
+#define CFG_FLASH_BASE_PHYS_H 0x4
+#define CFG_FLASH_BASE_PHYS_L 0xCE000000
+#define CFG_FLASH_BASE_PHYS (((u64)CFG_FLASH_BASE_PHYS_H << 32) | \
+ (u64)CFG_FLASH_BASE_PHYS_L)
+#define CFG_FLASH_SIZE (32 << 20)
+
+#define CFG_OCM_BASE 0xE3000000 /* OCM: 64k */
+#define CFG_OCM_PHYS_ADDR 0x0000000400040000ull
+
+#define CFG_SRAM_BASE 0xE8000000 /* SRAM: 256k */
+#define CFG_LOCAL_CONF_REGS 0xEF000000
+
+#define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals */
+
+#define CFG_AHB_BASE 0xE2000000 /* internal AHB peripherals */
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in OCM)
+ *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
+#define CFG_INIT_RAM_END (4 << 10)
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+/*
+ * Define here the location of the environment variables (FLASH).
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CFG_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */
+
+#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector flinfo */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of 1 complete sector */
+#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*----------------------------------------------------------------------------
+ * DDR SDRAM
+ *---------------------------------------------------------------------------*/
+#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
+
+#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
+#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
+#undef CONFIG_PPC4xx_DDR_METHOD_A
+
+#define CFG_MBYTES_SDRAM 512
+
+/* DDR1/2 SDRAM Device Control Register Data Values */
+/* Memory Queue */
+#define CFG_SDRAM_R0BAS 0x0000f000
+#define CFG_SDRAM_R1BAS 0x00000000
+#define CFG_SDRAM_R2BAS 0x00000000
+#define CFG_SDRAM_R3BAS 0x00000000
+#define CFG_SDRAM_PLBADDULL 0x00000000
+#define CFG_SDRAM_PLBADDUHB 0x00000008
+#define CFG_SDRAM_CONF1LL 0x00001080
+#define CFG_SDRAM_CONF1HB 0x00001080
+#define CFG_SDRAM_CONFPATHB 0x10a68000
+
+/* SDRAM Controller */
+#define CFG_SDRAM0_MB0CF 0x00000701
+#define CFG_SDRAM0_MB1CF 0x00000000
+#define CFG_SDRAM0_MB2CF 0x00000000
+#define CFG_SDRAM0_MB3CF 0x00000000
+#define CFG_SDRAM0_MCOPT1 0x05322000
+#define CFG_SDRAM0_MCOPT2 0x00000000
+#define CFG_SDRAM0_MODT0 0x01000000
+#define CFG_SDRAM0_MODT1 0x00000000
+#define CFG_SDRAM0_MODT2 0x00000000
+#define CFG_SDRAM0_MODT3 0x00000000
+#define CFG_SDRAM0_CODT 0x00800021
+#define CFG_SDRAM0_RTR 0x06180000
+#define CFG_SDRAM0_INITPLR0 0xb5380000
+#define CFG_SDRAM0_INITPLR1 0x82100400
+#define CFG_SDRAM0_INITPLR2 0x80820000
+#define CFG_SDRAM0_INITPLR3 0x80830000
+#define CFG_SDRAM0_INITPLR4 0x80810040
+#define CFG_SDRAM0_INITPLR5 0x80800532
+#define CFG_SDRAM0_INITPLR6 0x82100400
+#define CFG_SDRAM0_INITPLR7 0x8a080000
+#define CFG_SDRAM0_INITPLR8 0x8a080000
+#define CFG_SDRAM0_INITPLR9 0x8a080000
+#define CFG_SDRAM0_INITPLR10 0x8a080000
+#define CFG_SDRAM0_INITPLR11 0x80000432
+#define CFG_SDRAM0_INITPLR12 0x808103c0
+#define CFG_SDRAM0_INITPLR13 0x80810040
+#define CFG_SDRAM0_INITPLR14 0x00000000
+#define CFG_SDRAM0_INITPLR15 0x00000000
+#define CFG_SDRAM0_RQDC 0x80000038
+#define CFG_SDRAM0_RFDC 0x00000257
+#define CFG_SDRAM0_RDCC 0x40000000
+#define CFG_SDRAM0_DLCR 0x03000091
+#define CFG_SDRAM0_CLKTR 0x40000000
+#define CFG_SDRAM0_WRDTR 0x82000823
+#define CFG_SDRAM0_SDTR1 0x80201000
+#define CFG_SDRAM0_SDTR2 0x42204243
+#define CFG_SDRAM0_SDTR3 0x090c0d1a
+#define CFG_SDRAM0_MMODE 0x00000432
+#define CFG_SDRAM0_MEMODE 0x00000004
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CFG_I2C_SPEED 400000 /* I2C speed */
+
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/* I2C SYSMON (LM75, AD7414 is almost compatible) */
+#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
+#define CONFIG_DTT_AD7414 1 /* use AD7414 */
+#define CFG_I2C_DTT_ADDR 0x4a /* AD7414 I2C address */
+#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */
+#define CFG_DTT_MAX_TEMP 70
+#define CFG_DTT_LOW_TEMP -30
+#define CFG_DTT_HYSTERESIS 3
+
+/*-----------------------------------------------------------------------
+ * Ethernet
+ *----------------------------------------------------------------------*/
+#define CONFIG_FIXED_PHY 0xFFFFFFFF
+#define CONFIG_IBM_EMAC4_V4 1
+#define CONFIG_PHY_ADDR CONFIG_FIXED_PHY
+#define CONFIG_PHY1_ADDR 0
+#define CONFIG_PHY2_ADDR 1
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+
+#define CFG_FIXED_PHY_PORT(devnum, speed, duplex) \
+ {devnum, speed, duplex},
+#define CFG_FIXED_PHY_PORTS \
+ CFG_FIXED_PHY_PORT(0, 1000, FULL) \
+
+#define CONFIG_M88E1112_PHY
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+#define CONFIG_PHY_DYNAMIC_ANEG 1
+
+/*
+ * The following PHY addresses 0xB,0xC,0xD are reserved
+ * in M88E1112 so use these for GPCS PHY addresses
+ */
+#define CONFIG_GPCS_PHY_ADDR 0xB
+#define CONFIG_GPCS_PHY1_ADDR 0xC
+#define CONFIG_GPCS_PHY2_ADDR 0xD
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_AMCC_DEF_ENV \
+ CONFIG_AMCC_DEF_ENV_POWERPC \
+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
+ "kernel_addr=fe000000\0" \
+ "fdt_addr=fe1e0000\0" \
+ "ramdisk_addr=fe200000\0" \
+ "pciconfighost=1\0" \
+ "pcie_mode=RP:RP\0" \
+ ""
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_PCI
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#undef CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
+
+/* Board-specific PCI */
+#define CFG_PCI_TARGET_INIT /* let board init pci target */
+#undef CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
+#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
+#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE
+
+#define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
+#define CFG_PCIE_MEMSIZE 0x08000000 /* smallest inc for PCIe port */
+#define CFG_PCIE_BASE 0xc4000000 /* PCIe UTL regs */
+
+#define CFG_PCIE0_CFGBASE 0xc0000000
+#define CFG_PCIE1_CFGBASE 0xc1000000
+#define CFG_PCIE0_XCFGBASE 0xc3000000
+#define CFG_PCIE1_XCFGBASE 0xc3001000
+
+#define CFG_PCIE0_UTLBASE 0xc08010000ULL /* 36bit physical addr */
+
+/* base address of inbound PCIe window */
+#define CFG_PCIE_INBOUND_BASE 0x000000000ULL /* 36bit physical addr */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+
+/*
+ * Arches has 32MBytes of NOR FLASH (Spansion 29GL256), but the
+ * boot EBC mapping only supports a maximum of 16MBytes
+ * (4.ff00.0000 - 4.ffff.ffff).
+ * To solve this problem, the FLASH has to get remapped to another
+ * EBC address which accepts bigger regions:
+ *
+ * 0xfe00.0000 -> 4.ce00.0000
+ */
+
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CFG_EBC_PB0AP 0x10055e00
+#define CFG_EBC_PB0CR (CFG_BOOT_BASE_ADDR | 0x9a000)
+
+/* Memory Bank 1 (FPGA) initialization */
+#define CFG_EBC_PB1AP 0x7f8ffe80
+#define CFG_EBC_PB1CR (CFG_FPGA_BASE | 0x3a000)
+/* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/
+
+#define CFG_EBC_CFG 0xB8400000 /* EBC0_CFG */
+
+/*
+ * PPC4xx GPIO Configuration
+ */
+/* 460GT: Use EMAC2+3 configuration */
+#define CFG_4xx_GPIO_TABLE { \
+/* Out GPIO Alternate1 Alternate2 Alternate3 */ \
+ { \
+ /* GPIO Core 0 */ \
+ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
+ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
+ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
+ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
+ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
+ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
+ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
+ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
+ {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
+ {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
+ {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
+ {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
+ {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
+ {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
+ {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
+ {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
+ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO16 GMC1TxER USB2HostStop */ \
+ {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO17 GMC1CD USB2HostNext */ \
+ {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO18 GMC1RxER USB2HostDir */ \
+ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO19 GMC1TxEN USB2OTGStop */ \
+ {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO20 GMC1CRS USB2OTGNext */ \
+ {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO21 GMC1RxDV USB2OTGDir */ \
+ {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO22 NFRDY */ \
+ {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO23 NFREN */ \
+ {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO24 NFWEN */ \
+ {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO25 NFCLE */ \
+ {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO26 NFALE */ \
+ {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO27 IRQ(0) */ \
+ {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO28 IRQ(1) */ \
+ {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO29 IRQ(2) */ \
+ {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
+ /* GPIO30 PerPar0 DMAReq2 IRQ(7) */ \
+ {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
+ /* GPIO31 PerPar1 DMAAck2 IRQ(8) */ \
+ }, \
+ { \
+ /* GPIO Core 1 */ \
+ {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
+ /* GPIO32 PerPar2 EOT2/TC2 IRQ(9) */ \
+ {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
+ /* GPIO33 PerPar3 DMAReq3 IRQ(4) */ \
+ {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, \
+ /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */ \
+ {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, \
+ /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */ \
+ {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, \
+ /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN */ \
+ {GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, \
+ /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT */ \
+ {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, \
+ /* GPIO38 UART0_DTR_N UART1_SOUT */ \
+ {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, \
+ /* GPIO39 UART0_RI_N UART1_SIN */ \
+ {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO40 IRQ(3) */ \
+ {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO41 CS(1) */ \
+ {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO42 CS(2) */ \
+ {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO43 CS(3) DMAReq1 IRQ(10) */ \
+ {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, \
+ /* GPIO44 CS(4) DMAAck1 IRQ(11) */ \
+ {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, \
+ /* GPIO45 CS(5) EOT/TC1 IRQ(12) */ \
+ {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO46 PerAddr(5) DMAReq0 IRQ(13) */ \
+ {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO47 PerAddr(6) DMAAck0 IRQ(14) */ \
+ {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
+ /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15) */ \
+ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
+ /* GPIO49 Unselect via TraceSelect Bit */ \
+ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
+ /* GPIO50 Unselect via TraceSelect Bit */ \
+ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
+ /* GPIO51 Unselect via TraceSelect Bit */ \
+ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
+ /* GPIO52 Unselect via TraceSelect Bit */ \
+ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
+ /* GPIO53 Unselect via TraceSelect Bit */ \
+ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
+ /* GPIO54 Unselect via TraceSelect Bit */ \
+ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
+ /* GPIO55 Unselect via TraceSelect Bit */ \
+ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
+ /* GPIO56 Unselect via TraceSelect Bit */ \
+ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
+ /* GPIO57 Unselect via TraceSelect Bit */ \
+ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
+ /* GPIO58 Unselect via TraceSelect Bit */ \
+ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
+ /* GPIO59 Unselect via TraceSelect Bit */ \
+ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
+ /* GPIO60 Unselect via TraceSelect Bit */ \
+ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
+ /* GPIO61 Unselect via TraceSelect Bit */ \
+ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
+ /* GPIO62 Unselect via TraceSelect Bit */ \
+ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
+ /* GPIO63 Unselect via TraceSelect Bit */ \
+ } \
+}
+
+#endif /* __CONFIG_H */
diff --git a/include/ppc440.h b/include/ppc440.h
index be8d3ff..7ffc640 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1349,6 +1349,9 @@
#define SDR0_ETH_CFG_ZMII_RMII_MODE_10M 0x10
#define SDR0_ETH_CFG_ZMII_RMII_MODE_100M 0x11
+/* Ethernet Status Register */
+#define SDR0_ETH_STS 0x4104
+
/* Miscealleneaous Function Reg. (SDR0_MFR) */
#define SDR0_MFR 0x4300
#define SDR0_MFR_T0TxFL 0x00800000 /* force parity error TAHOE0 Tx FIFO bits 0:63 */
--
1.5.5
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH 1/3] ppc4xx: Initial support of the AMCC dual PPC460GT Arches reference board.
2008-09-24 8:11 [U-Boot] [PATCH 1/3] ppc4xx: Initial support of the AMCC dual PPC460GT Arches reference board Adam Graham
@ 2008-09-24 12:09 ` Wolfgang Denk
2008-09-25 9:09 ` Stefan Roese
2008-09-25 8:41 ` Stefan Roese
1 sibling, 1 reply; 5+ messages in thread
From: Wolfgang Denk @ 2008-09-24 12:09 UTC (permalink / raw)
To: u-boot
Dear Adam Graham,
In message <1222243872-15226-1-git-send-email-agraham@amcc.com> you wrote:
>
> +/*
> + * FPGA read/write helper macros
> + */
> +#define FPGA_READ(offset) ({ \
> + in_8((void *)(CFG_FPGA_BASE + offset)); })
> +#define FPGA_WRITE(offset, data) ({ \
> + out_8((void *)(CFG_FPGA_BASE + offset), data); })
> +
> +/*
> + * CPLD read/write helper macros
> + */
> +#define CPLD_READ(offset) ({ \
> + out_8((void *)(CFG_CPLD_ADDR), offset); \
> + in_8((void *)(CFG_CPLD_DATA)); })
> +#define CPLD_WRITE(offset, data) ({ \
> + out_8((void *)(CFG_CPLD_ADDR), offset); \
> + out_8((void *)(CFG_CPLD_DATA), data); })
Please make these inline functions instead. (See CodingStyle
document: "Generally, inline functions are preferable to macros
resembling functions.").
> + mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
It would be nice to use symbolic constatnts instead of hardcoded
numeric valies here.
> + /*
> + * Configure PFC (Pin Function Control) registers
> + * UART0: 4 pins
> + */
> + mtsdr(SDR0_PFC1, 0x00040000);
Ditto.
> + /* Enable PCI host functionality in SDR0_PCI0 */
> + mtsdr(SDR0_PCI0, 0xe0000000);
Ditto.
> + return 0;
> +}
Hm... most of this code looks suspiciously similar to what we have in
"board/amcc/canyonlands/canyonlands.c" - which is not a big surprise,
given the fact how closely related these two boards are.
Do we really need a separate board directory for arches?
Wouldn't it make more sense to use a common source tree for both,
like we do in Linux, too?
> +/*
> + * pci_target_init
> + *
> + * The bootstrap configuration provides default settings for the pci
> + * inbound map (PIM). But the bootstrap config choices are limited and
> + * may not be sufficient for a given board.
> + */
> +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
> +void pci_target_init(struct pci_controller *hose)
> +{
> + /*
> + * Disable everything
> + */
> + out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
> + out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
> + out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
> + out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
> +
> + /*
> + * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
> + * strapping options to not support sizes such as 128/256 MB.
> + */
> + out_le32((void *)PCIX0_PIM0LAL, CFG_SDRAM_BASE);
> + out_le32((void *)PCIX0_PIM0LAH, 0);
> + out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
> + out_le32((void *)PCIX0_BAR0, 0);
> +
> + /*
> + * Program the board's subsystem id/vendor id
> + */
> + out_le16((void *)PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
> + out_le16((void *)PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
> +
> + out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
> +}
> +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
> +
> +#if defined(CONFIG_PCI)
> +/*
> + * is_pci_host
> + *
> + * This routine is called to determine if a pci scan should be
> + * performed. With various hardware environments (especially cPCI and
> + * PPMC) it's insufficient to depend on the state of the arbiter enable
> + * bit in the strap register, or generic host/adapter assumptions.
> + *
> + * Rather than hard-code a bad assumption in the general 440 code, the
> + * 440 pci code requires the board to decide at runtime.
> + *
> + * Return 0 for adapter mode, non-zero for host (monarch) mode.
> + */
> +int is_pci_host(struct pci_controller *hose)
> +{
> + /* Board is always configured as host. */
> + return 1;
> +}
> +
> +static struct pci_controller pcie_hose[2] = { {0}, {0} };
> +
> +void pcie_setup_hoses(int busno)
> +{
> + struct pci_controller *hose;
> + int i, bus;
> + int ret = 0;
> + char *env;
> + unsigned int delay;
> + int end;
> +
> + /*
> + * assume we're called after the PCIX hose is initialized, which takes
> + * bus ID 0 and therefore start numbering PCIe's from 1.
> + */
> + bus = busno;
> +
> +#if defined(CONFIG_RAPIDIO)
> + end = 0;
> +#else
> + end = 1;
> +#endif
> +
> + for (i = 0; i <= end; i++) {
> +
> + if (is_end_point(i))
> + ret = ppc4xx_init_pcie_endport(i);
> + else
> + ret = ppc4xx_init_pcie_rootport(i);
> + if (ret) {
> + printf("PCIE%d: initialization as %s failed\n", i,
> + is_end_point(i) ? "endpoint" : "root-complex");
> + continue;
> + }
> +
> + hose = &pcie_hose[i];
> + hose->first_busno = bus;
> + hose->last_busno = bus;
> + hose->current_busno = bus;
> +
> + /* setup mem resource */
> + pci_set_region(hose->regions + 0,
> + CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
> + CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
> + CFG_PCIE_MEMSIZE,
> + PCI_REGION_MEM);
> + hose->region_count = 1;
> + pci_register_hose(hose);
> +
> + if (is_end_point(i)) {
> + ppc4xx_setup_pcie_endpoint(hose, i);
> + /*
> + * Reson for no scanning is endpoint can not generate
> + * upstream configuration accesses.
> + */
> + } else {
> + ppc4xx_setup_pcie_rootpoint(hose, i);
> + env = getenv("pciscandelay");
> + if (env != NULL) {
> + delay = simple_strtoul(env, NULL, 10);
> + if (delay > 5)
> + printf("Warning, expect noticable "
> + "delay before PCIe scan due "
> + "to 'pciscandelay' value!\n");
> + mdelay(delay * 1000);
> + }
> +
> + /*
> + * Config access can only go down stream
> + */
> + hose->last_busno = pci_hose_scan(hose);
> + bus = hose->last_busno + 1;
> + }
> + }
> +}
> +#endif /* CONFIG_PCI */
All this looks liek verbatim copies of the canyonlands code.
Similar for the rest of the code.
I think we should avoid such an extensive code duplication.
NAK.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"There's always been Tower of Babel sort of bickering inside Unix,
but this is the most extreme form ever. This means at least several
years of confusion." - Bill Gates, founder and chairman of Microsoft,
about the Open Systems Foundation
^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH 1/3] ppc4xx: Initial support of the AMCC dual PPC460GT Arches reference board.
2008-09-24 8:11 [U-Boot] [PATCH 1/3] ppc4xx: Initial support of the AMCC dual PPC460GT Arches reference board Adam Graham
2008-09-24 12:09 ` Wolfgang Denk
@ 2008-09-25 8:41 ` Stefan Roese
1 sibling, 0 replies; 5+ messages in thread
From: Stefan Roese @ 2008-09-25 8:41 UTC (permalink / raw)
To: u-boot
On Wednesday 24 September 2008, Adam Graham wrote:
> These are the initial support files for the AMCC dual PPC460GT Arches
> reference board.
I suggest that you add a small description about this board this the commit
log here.
Please find some comments below.
<snip>
> diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h
> index 1f27d78..fb19e0d 100644
> --- a/include/configs/amcc-common.h
> +++ b/include/configs/amcc-common.h
> @@ -55,6 +55,14 @@
> #endif
>
> /*
> + * Only very few boards have default netdev not set to eth0 (like Arches)
> + */
> +#if !defined(CONFIG_NETDEV)
> +#define CONFIG_NETDEV eth0
> +#endif
> +
> +
Nitpick: Don't add two empty lines please.
> +/*
> * Commands
> */
> #include <config_cmd_default.h>
> @@ -147,9 +155,11 @@
> /*
> * Booting and default environment
> */
> +#if !defined(CONFIG_PREBOOT)
> #define CONFIG_PREBOOT "echo;" \
> "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
> "echo"
> +#endif
> #define CONFIG_BOOTCOMMAND "run flash_self"
>
> /*
> @@ -184,7 +194,7 @@
> * General common environment variables shared on all AMCC eval boards
> */
> #define CONFIG_AMCC_DEF_ENV \
> - "netdev=eth0\0" \
> + "netdev=" xstr(CONFIG_NETDEV) "\0" \
> "nfsargs=setenv bootargs root=/dev/nfs rw " \
> "nfsroot=${serverip}:${rootpath}\0" \
> "ramargs=setenv bootargs root=/dev/ram rw\0" \
> @@ -197,8 +207,10 @@
> "initrd_high=30000000\0" \
> "kernel_addr_r=400000\0" \
> "fdt_addr_r=800000\0" \
> + "ramdisk_addr_r=C00000\0" \
> "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
> "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
> + "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
> CONFIG_AMCC_DEF_ENV_ROOTPATH
>
> /*
> @@ -214,6 +226,12 @@
> "tftp ${fdt_addr_r} ${fdt_file}; " \
> "run nfsargs addip addtty addmisc;" \
> "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
> + "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
> + "tftp ${fdt_addr_r} ${fdt_file};" \
> + "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
> + "net_self=run net_self_load;" \
> + "run ramargs addip addtty addmisc;" \
> + "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
> "fdt_file=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0"
>
> /*
> diff --git a/include/configs/arches.h b/include/configs/arches.h
> new file mode 100644
> index 0000000..6ad862f
> --- /dev/null
> +++ b/include/configs/arches.h
> @@ -0,0 +1,505 @@
> +/*
> + * (C) Copyright 2008
> + * Adam Graham, Applied Micro Circuits Corp., agraham at amcc.com.
> + * Victor Gallardo, Applied Micro Circuits Corp., agraham at amcc.com.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +/************************************************************************
> + * arches.h - configuration for Arches (460GT)
> + ***********************************************************************/
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +/*-----------------------------------------------------------------------
> + * High Level Configuration Options
> + *----------------------------------------------------------------------*/
> +/* This config file is used for Arches (460GT) */
> +#define CONFIG_ARCHES 1 /* Board is Arches */
> +#define CONFIG_460GT 1 /* Specific PPC460GT */
> +#define CONFIG_440 1
> +#define CONFIG_4xx 1 /* ... PPC4xx family */
> +#define CONFIG_NETDEV eth1
> +
> +/*
> + * Update default PREBOOT environment variables
> + * defined in amcc-common.h
> + */
> +#define CONFIG_PREBOOT \
> + "setenv ethact ppc_4xx_eth1;" \
> + "echo;" \
> + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
> + "echo;"
> +
> +/*
> + * Include common defines/options for all AMCC eval boards
> + */
> +#define CONFIG_HOSTNAME arches
> +#include "amcc-common.h"
> +
> +#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */
> +
> +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
> +#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
> +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
> +#define CONFIG_BOARD_TYPES 1 /* support board types */
> +
> +/*-----------------------------------------------------------------------
> + * RapidIO I/O and Registers
> + *----------------------------------------------------------------------*/
> +
> +#define CONFIG_RAPIDIO
> +#define CFG_460GT_SRIO_ERRATA_1
> +
> +#define SRGPL0_REG_BAR 0x0000000DAA000000ull /* 16MB */
> +#define SRGPL0_CFG_BAR 0x0000000DAB000000ull /* 16MB */
> +#define SRGPL0_MNT_BAR 0x0000000DAC000000ull /* 16MB */
> +#define SRGPL0_MSG_BAR 0x0000000DAD000000ull /* 16MB */
> +#define SRGPL0_OUT_BAR 0x0000000DB0000000ull /* 256MB */
> +
> +#define CFG_SRGPL0_REG_BAR 0xAA000000 /* 16MB */
> +#define CFG_SRGPL0_CFG_BAR 0xAB000000 /* 16MB */
> +#define CFG_SRGPL0_MNT_BAR 0xAC000000 /* 16MB */
> +#define CFG_SRGPL0_MSG_BAR 0xAD000000 /* 16MB */
> +
> +#define CFG_I2ODMA_BASE 0xCF000000
> +#define CFG_I2ODMA_PHYS_ADDR 0x0000000400100000ull
> +
> +#define CONFIG_PPC4XX_RAPIDIO_PROMISCUOUS_MODE
> +#undef CONFIG_PPC4XX_RAPIDIO_DEBUG
> +#undef CONFIG_PPC4XX_RAPIDIO_IN_BAR_USE_OCM
> +#define CONFIG_PPC4XX_RAPIDIO_USE_HB_PLB
> +#undef CONFIG_PPC4XX_RAPIDIO_LOOPBACK
> +
> +/* EBC stuff */
> +#define CFG_NAND_ADDR 0xE0000000
> +#define CFG_FPGA_BASE 0xE1000000
> +#define CFG_CPLD_ADDR (CFG_FPGA_BASE + 0x00080000)
> +#define CFG_CPLD_DATA (CFG_FPGA_BASE + 0x00080002)
> +#define CFG_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space: 0xFF000000 */
> +#define CFG_FLASH_BASE 0xFE000000 /* later mapped to this addr */
> +#define CFG_FLASH_BASE_PHYS_H 0x4
> +#define CFG_FLASH_BASE_PHYS_L 0xCE000000
> +#define CFG_FLASH_BASE_PHYS (((u64)CFG_FLASH_BASE_PHYS_H << 32) | \
> + (u64)CFG_FLASH_BASE_PHYS_L)
> +#define CFG_FLASH_SIZE (32 << 20)
> +
> +#define CFG_OCM_BASE 0xE3000000 /* OCM: 64k */
> +#define CFG_OCM_PHYS_ADDR 0x0000000400040000ull
> +
> +#define CFG_SRAM_BASE 0xE8000000 /* SRAM: 256k */
> +#define CFG_LOCAL_CONF_REGS 0xEF000000
> +
> +#define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals */
> +
> +#define CFG_AHB_BASE 0xE2000000 /* internal AHB peripherals */
> +
> +/*-----------------------------------------------------------------------
> + * Initial RAM & stack pointer (placed in OCM)
> + *----------------------------------------------------------------------*/
> +#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
> +#define CFG_INIT_RAM_END (4 << 10)
> +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
> +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
> +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
> +
> +/*-----------------------------------------------------------------------
> + * Serial Port
> + *----------------------------------------------------------------------*/
> +#undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */
> +
> +/*-----------------------------------------------------------------------
> + * Environment
> + *----------------------------------------------------------------------*/
> +/*
> + * Define here the location of the environment variables (FLASH).
> + */
> +#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
> +
> +/*-----------------------------------------------------------------------
> + * FLASH related
> + *----------------------------------------------------------------------*/
> +#define CFG_FLASH_CFI /* The flash is CFI compatible */
> +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
> +#define CFG_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */
> +
> +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
> +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
> +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
> +
> +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms)
> */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms)
> */ +
> +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster)
> */ +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector flinfo */ +
> +#ifdef CONFIG_ENV_IS_IN_FLASH
> +#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of 1 complete sector */
> +#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
> +#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
> +
> +/* Address and size of Redundant Environment Sector */
> +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
> +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
> +#endif /* CFG_ENV_IS_IN_FLASH */
> +
> +/*------------------------------------------------------------------------
>---- + * DDR SDRAM
> +
> *--------------------------------------------------------------------------
>-*/ +#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */ +
> +#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
> +#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
> +#undef CONFIG_PPC4xx_DDR_METHOD_A
> +
> +#define CFG_MBYTES_SDRAM 512
> +
> +/* DDR1/2 SDRAM Device Control Register Data Values */
> +/* Memory Queue */
> +#define CFG_SDRAM_R0BAS 0x0000f000
> +#define CFG_SDRAM_R1BAS 0x00000000
> +#define CFG_SDRAM_R2BAS 0x00000000
> +#define CFG_SDRAM_R3BAS 0x00000000
> +#define CFG_SDRAM_PLBADDULL 0x00000000
> +#define CFG_SDRAM_PLBADDUHB 0x00000008
> +#define CFG_SDRAM_CONF1LL 0x00001080
> +#define CFG_SDRAM_CONF1HB 0x00001080
> +#define CFG_SDRAM_CONFPATHB 0x10a68000
> +
> +/* SDRAM Controller */
> +#define CFG_SDRAM0_MB0CF 0x00000701
> +#define CFG_SDRAM0_MB1CF 0x00000000
> +#define CFG_SDRAM0_MB2CF 0x00000000
> +#define CFG_SDRAM0_MB3CF 0x00000000
> +#define CFG_SDRAM0_MCOPT1 0x05322000
> +#define CFG_SDRAM0_MCOPT2 0x00000000
> +#define CFG_SDRAM0_MODT0 0x01000000
> +#define CFG_SDRAM0_MODT1 0x00000000
> +#define CFG_SDRAM0_MODT2 0x00000000
> +#define CFG_SDRAM0_MODT3 0x00000000
> +#define CFG_SDRAM0_CODT 0x00800021
> +#define CFG_SDRAM0_RTR 0x06180000
> +#define CFG_SDRAM0_INITPLR0 0xb5380000
> +#define CFG_SDRAM0_INITPLR1 0x82100400
> +#define CFG_SDRAM0_INITPLR2 0x80820000
> +#define CFG_SDRAM0_INITPLR3 0x80830000
> +#define CFG_SDRAM0_INITPLR4 0x80810040
> +#define CFG_SDRAM0_INITPLR5 0x80800532
> +#define CFG_SDRAM0_INITPLR6 0x82100400
> +#define CFG_SDRAM0_INITPLR7 0x8a080000
> +#define CFG_SDRAM0_INITPLR8 0x8a080000
> +#define CFG_SDRAM0_INITPLR9 0x8a080000
> +#define CFG_SDRAM0_INITPLR10 0x8a080000
> +#define CFG_SDRAM0_INITPLR11 0x80000432
> +#define CFG_SDRAM0_INITPLR12 0x808103c0
> +#define CFG_SDRAM0_INITPLR13 0x80810040
> +#define CFG_SDRAM0_INITPLR14 0x00000000
> +#define CFG_SDRAM0_INITPLR15 0x00000000
> +#define CFG_SDRAM0_RQDC 0x80000038
> +#define CFG_SDRAM0_RFDC 0x00000257
> +#define CFG_SDRAM0_RDCC 0x40000000
> +#define CFG_SDRAM0_DLCR 0x03000091
> +#define CFG_SDRAM0_CLKTR 0x40000000
> +#define CFG_SDRAM0_WRDTR 0x82000823
> +#define CFG_SDRAM0_SDTR1 0x80201000
> +#define CFG_SDRAM0_SDTR2 0x42204243
> +#define CFG_SDRAM0_SDTR3 0x090c0d1a
> +#define CFG_SDRAM0_MMODE 0x00000432
> +#define CFG_SDRAM0_MEMODE 0x00000004
> +
> +/*-----------------------------------------------------------------------
> + * I2C
> + *----------------------------------------------------------------------*/
> +#define CFG_I2C_SPEED 400000 /* I2C speed */
> +
> +#define CFG_I2C_MULTI_EEPROMS
> +#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
> +#define CFG_I2C_EEPROM_ADDR_LEN 1
> +#define CFG_EEPROM_PAGE_WRITE_ENABLE
> +#define CFG_EEPROM_PAGE_WRITE_BITS 3
> +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
> +
> +/* I2C SYSMON (LM75, AD7414 is almost compatible) */
> +#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
> +#define CONFIG_DTT_AD7414 1 /* use AD7414 */
> +#define CFG_I2C_DTT_ADDR 0x4a /* AD7414 I2C address */
> +#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */
> +#define CFG_DTT_MAX_TEMP 70
> +#define CFG_DTT_LOW_TEMP -30
> +#define CFG_DTT_HYSTERESIS 3
> +
> +/*-----------------------------------------------------------------------
> + * Ethernet
> + *----------------------------------------------------------------------*/
> +#define CONFIG_FIXED_PHY 0xFFFFFFFF
> +#define CONFIG_IBM_EMAC4_V4 1
> +#define CONFIG_PHY_ADDR CONFIG_FIXED_PHY
> +#define CONFIG_PHY1_ADDR 0
> +#define CONFIG_PHY2_ADDR 1
> +#define CONFIG_HAS_ETH0
> +#define CONFIG_HAS_ETH1
> +#define CONFIG_HAS_ETH2
> +
> +#define CFG_FIXED_PHY_PORT(devnum, speed, duplex) \
> + {devnum, speed, duplex},
> +#define CFG_FIXED_PHY_PORTS \
> + CFG_FIXED_PHY_PORT(0, 1000, FULL) \
> +
> +#define CONFIG_M88E1112_PHY
> +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
> +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
> +#define CONFIG_PHY_DYNAMIC_ANEG 1
> +
> +/*
> + * The following PHY addresses 0xB,0xC,0xD are reserved
> + * in M88E1112 so use these for GPCS PHY addresses
> + */
> +#define CONFIG_GPCS_PHY_ADDR 0xB
> +#define CONFIG_GPCS_PHY1_ADDR 0xC
> +#define CONFIG_GPCS_PHY2_ADDR 0xD
> +
> +/*
> + * Default environment variables
> + */
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + CONFIG_AMCC_DEF_ENV \
> + CONFIG_AMCC_DEF_ENV_POWERPC \
> + CONFIG_AMCC_DEF_ENV_NOR_UPD \
> + "kernel_addr=fe000000\0" \
> + "fdt_addr=fe1e0000\0" \
> + "ramdisk_addr=fe200000\0" \
> + "pciconfighost=1\0" \
> + "pcie_mode=RP:RP\0" \
> + ""
> +
> +/*
> + * Commands additional to the ones defined in amcc-common.h
> + */
> +#define CONFIG_CMD_DTT
> +#define CONFIG_CMD_PCI
> +
> +/* Partitions */
> +#define CONFIG_MAC_PARTITION
> +#define CONFIG_DOS_PARTITION
> +#define CONFIG_ISO_PARTITION
> +
> +/*-----------------------------------------------------------------------
> + * PCI stuff
> + *----------------------------------------------------------------------*/
> +/* General PCI */
> +#define CONFIG_PCI /* include pci support */
> +#undef CONFIG_PCI_PNP /* do pci plug-and-play */
> +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
> +#define CONFIG_PCI_CONFIG_HOST_BRIDGE
> +
> +/* Board-specific PCI */
> +#define CFG_PCI_TARGET_INIT /* let board init pci target */
> +#undef CFG_PCI_MASTER_INIT
> +
> +#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
> +#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
> +
> +/*-----------------------------------------------------------------------
> + * Base addresses -- Note these are effective addresses where the
> + * actual resources get mapped (not physical addresses)
> + *----------------------------------------------------------------------*/
> +#define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
> +#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
> +#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE
> +
> +#define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
> +#define CFG_PCIE_MEMSIZE 0x08000000 /* smallest inc for PCIe port */
> +#define CFG_PCIE_BASE 0xc4000000 /* PCIe UTL regs */
> +
> +#define CFG_PCIE0_CFGBASE 0xc0000000
> +#define CFG_PCIE1_CFGBASE 0xc1000000
> +#define CFG_PCIE0_XCFGBASE 0xc3000000
> +#define CFG_PCIE1_XCFGBASE 0xc3001000
> +
> +#define CFG_PCIE0_UTLBASE 0xc08010000ULL /* 36bit physical addr */
> +
> +/* base address of inbound PCIe window */
> +#define CFG_PCIE_INBOUND_BASE 0x000000000ULL /* 36bit physical addr */
> +
> +/*-----------------------------------------------------------------------
> + * External Bus Controller (EBC) Setup
> + *----------------------------------------------------------------------*/
> +
> +/*
> + * Arches has 32MBytes of NOR FLASH (Spansion 29GL256), but the
> + * boot EBC mapping only supports a maximum of 16MBytes
> + * (4.ff00.0000 - 4.ffff.ffff).
> + * To solve this problem, the FLASH has to get remapped to another
> + * EBC address which accepts bigger regions:
> + *
> + * 0xfe00.0000 -> 4.ce00.0000
> + */
> +
> +/* Memory Bank 0 (NOR-FLASH) initialization */
> +#define CFG_EBC_PB0AP 0x10055e00
> +#define CFG_EBC_PB0CR (CFG_BOOT_BASE_ADDR | 0x9a000)
> +
> +/* Memory Bank 1 (FPGA) initialization */
> +#define CFG_EBC_PB1AP 0x7f8ffe80
> +#define CFG_EBC_PB1CR (CFG_FPGA_BASE | 0x3a000)
> +/* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/
> +
> +#define CFG_EBC_CFG 0xB8400000 /* EBC0_CFG */
> +
> +/*
> + * PPC4xx GPIO Configuration
> + */
> +/* 460GT: Use EMAC2+3 configuration */
> +#define CFG_4xx_GPIO_TABLE { \
> +/* Out GPIO Alternate1 Alternate2 Alternate3 */ \
> + { \
> + /* GPIO Core 0 */ \
> + {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
> + /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
You wrapped the line here. I know that the original CFG_4xx_GPIO_TABLE
implementation on some other boards uses too longs lines. But it makes the
code better readable this way. So I think it makes sense to break the 80
chars per line rule in this case.
Best regards,
Stefan
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH 1/3] ppc4xx: Initial support of the AMCC dual PPC460GT Arches reference board.
2008-09-24 12:09 ` Wolfgang Denk
@ 2008-09-25 9:09 ` Stefan Roese
2008-09-25 9:48 ` Wolfgang Denk
0 siblings, 1 reply; 5+ messages in thread
From: Stefan Roese @ 2008-09-25 9:09 UTC (permalink / raw)
To: u-boot
On Wednesday 24 September 2008, Wolfgang Denk wrote:
> > +/*
> > + * FPGA read/write helper macros
> > + */
> > +#define FPGA_READ(offset) ({ \
> > + in_8((void *)(CFG_FPGA_BASE + offset)); })
> > +#define FPGA_WRITE(offset, data) ({ \
> > + out_8((void *)(CFG_FPGA_BASE + offset), data); })
> > +
> > +/*
> > + * CPLD read/write helper macros
> > + */
> > +#define CPLD_READ(offset) ({ \
> > + out_8((void *)(CFG_CPLD_ADDR), offset); \
> > + in_8((void *)(CFG_CPLD_DATA)); })
> > +#define CPLD_WRITE(offset, data) ({ \
> > + out_8((void *)(CFG_CPLD_ADDR), offset); \
> > + out_8((void *)(CFG_CPLD_DATA), data); })
>
> Please make these inline functions instead. (See CodingStyle
> document: "Generally, inline functions are preferable to macros
> resembling functions.").
ACK.
> > + mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
>
> It would be nice to use symbolic constatnts instead of hardcoded
> numeric valies here.
I don't think that this makes sense here. We would need to add 32 defines
times the number of UIC's available to make it possible to configure this
with symbolic constants. That's 128 in the 460EX/GT case. So I vote for
leaving it as is here.
> > + /*
> > + * Configure PFC (Pin Function Control) registers
> > + * UART0: 4 pins
> > + */
> > + mtsdr(SDR0_PFC1, 0x00040000);
>
> Ditto.
ACK. Adam just copied the hardcoded value from Canyonlands, but it is a good
idea to use a define for this PFCx configuration.
> > + /* Enable PCI host functionality in SDR0_PCI0 */
> > + mtsdr(SDR0_PCI0, 0xe0000000);
>
> Ditto.
ACK.
> > + return 0;
> > +}
>
> Hm... most of this code looks suspiciously similar to what we have in
> "board/amcc/canyonlands/canyonlands.c" - which is not a big surprise,
> given the fact how closely related these two boards are.
>
> Do we really need a separate board directory for arches?
>
> Wouldn't it make more sense to use a common source tree for both,
> like we do in Linux, too?
I'm not so sure here. In Linux it is different. All the 4xx platforms files
were 100% identical. So it really made no sense to have multiple incarnations
there. In U-Boot we have some differences. I'm not sure if it makes sense to
try to move the common code into a separate place and reuse it there. We
would have to introduce even more #ifdef's in the resulting code to make it
work on Canyonlands, Glacier & Arches.
OK, functions that are 100% identical between multiple boards are probably
better moved into such a common directory (perhaps board/amcc/common). The
PCI(e) related functions come to my mind first.
> > +/*
> > + * pci_target_init
> > + *
> > + * The bootstrap configuration provides default settings for the pci
> > + * inbound map (PIM). But the bootstrap config choices are limited and
> > + * may not be sufficient for a given board.
> > + */
> > +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
> > +void pci_target_init(struct pci_controller *hose)
> > +{
> > + /*
> > + * Disable everything
> > + */
> > + out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
> > + out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
> > + out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
> > + out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
> > +
> > + /*
> > + * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
> > + * strapping options to not support sizes such as 128/256 MB.
> > + */
> > + out_le32((void *)PCIX0_PIM0LAL, CFG_SDRAM_BASE);
> > + out_le32((void *)PCIX0_PIM0LAH, 0);
> > + out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
> > + out_le32((void *)PCIX0_BAR0, 0);
> > +
> > + /*
> > + * Program the board's subsystem id/vendor id
> > + */
> > + out_le16((void *)PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
> > + out_le16((void *)PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
> > +
> > + out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
> > +}
> > +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
> > +
> > +#if defined(CONFIG_PCI)
> > +/*
> > + * is_pci_host
> > + *
> > + * This routine is called to determine if a pci scan should be
> > + * performed. With various hardware environments (especially cPCI and
> > + * PPMC) it's insufficient to depend on the state of the arbiter enable
> > + * bit in the strap register, or generic host/adapter assumptions.
> > + *
> > + * Rather than hard-code a bad assumption in the general 440 code, the
> > + * 440 pci code requires the board to decide at runtime.
> > + *
> > + * Return 0 for adapter mode, non-zero for host (monarch) mode.
> > + */
> > +int is_pci_host(struct pci_controller *hose)
> > +{
> > + /* Board is always configured as host. */
> > + return 1;
> > +}
> > +
> > +static struct pci_controller pcie_hose[2] = { {0}, {0} };
> > +
> > +void pcie_setup_hoses(int busno)
> > +{
> > + struct pci_controller *hose;
> > + int i, bus;
> > + int ret = 0;
> > + char *env;
> > + unsigned int delay;
> > + int end;
> > +
> > + /*
> > + * assume we're called after the PCIX hose is initialized, which takes
> > + * bus ID 0 and therefore start numbering PCIe's from 1.
> > + */
> > + bus = busno;
> > +
> > +#if defined(CONFIG_RAPIDIO)
> > + end = 0;
> > +#else
> > + end = 1;
> > +#endif
> > +
> > + for (i = 0; i <= end; i++) {
> > +
> > + if (is_end_point(i))
> > + ret = ppc4xx_init_pcie_endport(i);
> > + else
> > + ret = ppc4xx_init_pcie_rootport(i);
> > + if (ret) {
> > + printf("PCIE%d: initialization as %s failed\n", i,
> > + is_end_point(i) ? "endpoint" : "root-complex");
> > + continue;
> > + }
> > +
> > + hose = &pcie_hose[i];
> > + hose->first_busno = bus;
> > + hose->last_busno = bus;
> > + hose->current_busno = bus;
> > +
> > + /* setup mem resource */
> > + pci_set_region(hose->regions + 0,
> > + CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
> > + CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
> > + CFG_PCIE_MEMSIZE,
> > + PCI_REGION_MEM);
> > + hose->region_count = 1;
> > + pci_register_hose(hose);
> > +
> > + if (is_end_point(i)) {
> > + ppc4xx_setup_pcie_endpoint(hose, i);
> > + /*
> > + * Reson for no scanning is endpoint can not generate
> > + * upstream configuration accesses.
> > + */
> > + } else {
> > + ppc4xx_setup_pcie_rootpoint(hose, i);
> > + env = getenv("pciscandelay");
> > + if (env != NULL) {
> > + delay = simple_strtoul(env, NULL, 10);
> > + if (delay > 5)
> > + printf("Warning, expect noticable "
> > + "delay before PCIe scan due "
> > + "to 'pciscandelay' value!\n");
> > + mdelay(delay * 1000);
> > + }
> > +
> > + /*
> > + * Config access can only go down stream
> > + */
> > + hose->last_busno = pci_hose_scan(hose);
> > + bus = hose->last_busno + 1;
> > + }
> > + }
> > +}
> > +#endif /* CONFIG_PCI */
>
> All this looks liek verbatim copies of the canyonlands code.
No, not 100% I'm afraid. There are subtile differences here with respect to
RAPIDIO and the Canyonlands/Glacier distinction in the Canyonlands version.
> Similar for the rest of the code.
>
> I think we should avoid such an extensive code duplication.
Sure, it is always good to not duplicate code. But if the code is not 100%
identical then I'm unsure what's better. Using more common board code has the
following advantages and disadvantages:
+ Less code duplication
+ Easier to maintain
- Resulting code is "uglier" by using more #ifdef's
- Makes it harder for custom board ports, since the code needed is
scattered in more directories
Not sure where to go here. Wolfgang, your call.
Best regards,
Stefan
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH 1/3] ppc4xx: Initial support of the AMCC dual PPC460GT Arches reference board.
2008-09-25 9:09 ` Stefan Roese
@ 2008-09-25 9:48 ` Wolfgang Denk
0 siblings, 0 replies; 5+ messages in thread
From: Wolfgang Denk @ 2008-09-25 9:48 UTC (permalink / raw)
To: u-boot
Dear Stefan Roese,
In message <200809251109.49798.sr@denx.de> you wrote:
>
> > Wouldn't it make more sense to use a common source tree for both,
> > like we do in Linux, too?
>
> I'm not so sure here. In Linux it is different. All the 4xx platforms files
> were 100% identical. So it really made no sense to have multiple incarnations
> there. In U-Boot we have some differences. I'm not sure if it makes sense to
> try to move the common code into a separate place and reuse it there. We
> would have to introduce even more #ifdef's in the resulting code to make it
> work on Canyonlands, Glacier & Arches.
I think it definitely makes sense at least to extract common or at
least very similar code.
> OK, functions that are 100% identical between multiple boards are probably
> better moved into such a common directory (perhaps board/amcc/common). The
> PCI(e) related functions come to my mind first.
Not only that - already now the Arches code contains improvements
(like changing hard-coded numbers into much easier readbale symbolic
constants) that would make sense to go to Canyonlands and Glacier,
too, but as is the existing code does not benefit from the new
patches, i. e. the improvments get lost and the copied code diverges.
> > All this looks liek verbatim copies of the canyonlands code.
>
> No, not 100% I'm afraid. There are subtile differences here with respect to
> RAPIDIO and the Canyonlands/Glacier distinction in the Canyonlands version.
Ineed. But the differences arre minimal compared to the amount of
copied code.
> Sure, it is always good to not duplicate code. But if the code is not 100%
> identical then I'm unsure what's better. Using more common board code has the
> following advantages and disadvantages:
>
> + Less code duplication
> + Easier to maintain
This entry alone is worth the effort. We have already too many pieces
of rotting code.
> - Resulting code is "uglier" by using more #ifdef's
This may or may not be the case. We have developed quite a few methods
to avoid #ifdef's. And we already support Canyonlands and Glacier in
one file, so why not add Arches?
> - Makes it harder for custom board ports, since the code needed is
> scattered in more directories
On contrary: if we factor out common code now, it will be much easier
for following custom ports to see which parts need to be adapted.
> Not sure where to go here. Wolfgang, your call.
I think the advantages outweight the additional effort.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The only way to get rid of a temptation is to yield to it.
- Oscar Wilde
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2008-09-25 9:48 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2008-09-24 8:11 [U-Boot] [PATCH 1/3] ppc4xx: Initial support of the AMCC dual PPC460GT Arches reference board Adam Graham
2008-09-24 12:09 ` Wolfgang Denk
2008-09-25 9:09 ` Stefan Roese
2008-09-25 9:48 ` Wolfgang Denk
2008-09-25 8:41 ` Stefan Roese
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