[U-Boot] [PATCH 1/1] ppc4xx: Reset and relock memory DLL after SDRAM_CLKTR change

[U-Boot] [PATCH 1/1] ppc4xx: Reset and relock memory DLL after SDRAM_CLKTR change

[Adam Graham]

After changing SDRAM_CLKTR phase value rerun the memory preload initialization sequence (INITPLR) to reset and relock the memory DLL.  Changing the SDRAM_CLKTR memory clock phase coarse timing adjustment effects the phase relationship of the internal, to the PPC chip, and external, to the PPC chip, versions of MEMCLK_OUT.

Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
---
 cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c |   21 +++++++++++++++++++++
 1 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
index 83b9883..47ab39b 100644
--- a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
+++ b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
@@ -174,6 +174,23 @@ static inline void ecc_clear_status_reg(void)
 #endif
 }
 
+/*
+ * Reset and relock memory DLL after SDRAM_CLKTR change
+ */
+static inline void relock_memory_DLL(void)
+{
+	u32 reg;
+
+	mtsdram(SDRAM_MCOPT2, SDRAM_MCOPT2_IPTR_EXECUTE);
+
+	do {
+		mfsdram(SDRAM_MCSTAT, reg);
+	} while (!(reg & SDRAM_MCSTAT_MIC_COMP));
+
+	mfsdram(SDRAM_MCOPT2, reg);
+	mtsdram(SDRAM_MCOPT2, reg | SDRAM_MCOPT2_DCEN_ENABLE);
+}
+
 static int ecc_check_status_reg(void)
 {
 	u32 ecc_status;
@@ -981,6 +998,8 @@ u32 DQS_autocalibration(void)
 
 		mtsdram(SDRAM_CLKTR, clkp << 30);
 
+		relock_memory_DLL();
+
 		putc('\b');
 		putc(slash[loopi++ % 8]);
 
@@ -1170,6 +1189,8 @@ u32 DQS_autocalibration(void)
 
 		mtsdram(SDRAM_CLKTR, tcal.clocks.clktr << 30);
 
+		relock_memory_DLL();
+
 		mfsdram(SDRAM_RQDC, rqdc_reg);
 		rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
 		mtsdram(SDRAM_RQDC, rqdc_reg |
-- 
1.5.5

[U-Boot] [PATCH 1/1] ppc4xx: Reset and relock memory DLL after SDRAM_CLKTR change

[Wolfgang Denk]

Dear Adam Graham,

In message <1222995701-7810-1-git-send-email-agraham@amcc.com> you wrote:
> After changing SDRAM_CLKTR phase value rerun the memory preload initialization sequence (INITPLR) to reset and relock the memory DLL.  Changing the SDRAM_CLKTR memory clock phase coarse timing adjustment effects the phase relationship of the internal, to the PPC chip, and external, to the PPC chip, versions of MEMCLK_OUT.

Line too long.


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Keep your head and your heart going in the right  direction  and  you
will not have to worry about your feet.

[U-Boot] [PATCH 1/1] ppc4xx: Reset and relock memory DLL after SDRAM_CLKTR change

[Stefan Roese]

Adam,

On Saturday 04 October 2008, Wolfgang Denk wrote:
> > After changing SDRAM_CLKTR phase value rerun the memory preload
> > initialization sequence (INITPLR) to reset and relock the memory DLL. 
> > Changing the SDRAM_CLKTR memory clock phase coarse timing adjustment
> > effects the phase relationship of the internal, to the PPC chip, and
> > external, to the PPC chip, versions of MEMCLK_OUT.
>
> Line too long.

Yes, please change your setup to wrap around 70 chars per line in the commit 
text. Please resend and I'll add this fix quickly so that it makes it into 
the next release.

Thanks.

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================