[U-Boot] [PATCH 1/4] Fix the NAND size overflow issue.

[U-Boot] [PATCH 1/4] Fix the NAND size overflow issue.

[Jason Jin]

When the NAND size is or large than 4G, the size will overflow,
The adjustment in this patch try to fix this.

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
---
 drivers/mtd/nand/nand.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c
index ebd2acd..71a0e4b 100644
--- a/drivers/mtd/nand/nand.c
+++ b/drivers/mtd/nand/nand.c
@@ -63,11 +63,11 @@ void nand_init(void)
 	unsigned int size = 0;
 	for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) {
 		nand_init_chip(&nand_info[i], &nand_chip[i], base_address[i]);
-		size += nand_info[i].size;
+		size += nand_info[i].size / 1024;
 		if (nand_curr_device == -1)
 			nand_curr_device = i;
 	}
-	printf("%u MiB\n", size / (1024 * 1024));
+	printf("%u MiB\n", size / 1024);
 
 #ifdef CFG_NAND_SELECT_DEVICE
 	/*
-- 
1.5.4

[U-Boot] [PATCH 2/4] Make the fsl_elbc_nand driver work for both 83xx and 85xx

[Jason Jin]

This patch try to make the fsl_elbc_nand driver work for
both 83xx and 85xx boards.
Move the FMR Macros from 83xx.h to fsl_lbc.h and
redefine the elbc register structure in the driver.

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
---
 drivers/mtd/nand/fsl_elbc_nand.c |   63 ++++++++++++++++++++++++----
 include/asm-ppc/fsl_lbc.h        |   85 ++++++++++++++++++++++++++++++++++++++
 include/mpc83xx.h                |   85 --------------------------------------
 3 files changed, 140 insertions(+), 93 deletions(-)

diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 4351824..b12c540 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -52,6 +52,50 @@
 
 #define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
 
+/*
+ * Local Bus Controller Registers.
+ */
+typedef struct lbus_bank {
+	u32 br;			/* Base Register */
+	u32 or;			/* Option Register */
+} lbus_bank_t;
+
+typedef struct fsl_lbus {
+	lbus_bank_t bank[8];
+	u8 res0[0x28];
+	u32 mar;		/* UPM Address Register */
+	u8 res1[0x4];
+	u32 mamr;		/* UPMA Mode Register */
+	u32 mbmr;		/* UPMB Mode Register */
+	u32 mcmr;		/* UPMC Mode Register */
+	u8 res2[0x8];
+	u32 mrtpr;		/* Memory Refresh Timer Prescaler Register */
+	u32 mdr;		/* UPM Data Register */
+	u8 res3[0x4];
+	u32 lsor;		/* Special Operation Initiation Register */
+	u32 lsdmr;		/* SDRAM Mode Register */
+	u8 res4[0x8];
+	u32 lurt;		/* UPM Refresh Timer */
+	u32 lsrt;		/* SDRAM Refresh Timer */
+	u8 res5[0x8];
+	u32 ltesr;		/* Transfer Error Status Register */
+	u32 ltedr;		/* Transfer Error Disable Register */
+	u32 lteir;		/* Transfer Error Interrupt Register */
+	u32 lteatr;		/* Transfer Error Attributes Register */
+	u32 ltear;		/* Transfer Error Address Register */
+	u8 res6[0xC];
+	u32 lbcr;		/* Configuration Register */
+	u32 lcrr;		/* Clock Ratio Register */
+	u8 res7[0x8];
+	u32 fmr;		/* Flash Mode Register */
+	u32 fir;		/* Flash Instruction Register */
+	u32 fcr;		/* Flash Command Register */
+	u32 fbar;		/* Flash Block Addr Register */
+	u32 fpar;		/* Flash Page Addr Register */
+	u32 fbcr;		/* Flash Byte Count Register */
+	u8 res8[0xF08];
+}fsl_lbus_t;
+
 struct fsl_elbc_ctrl;
 
 /* mtd information per set */
@@ -75,7 +119,7 @@ struct fsl_elbc_ctrl {
 	struct fsl_elbc_mtd *chips[MAX_BANKS];
 
 	/* device info */
-	lbus83xx_t *regs;
+	fsl_lbus_t *regs;
 	u8 __iomem *addr;        /* Address of assigned FCM buffer        */
 	unsigned int page;       /* Last page written to / read from      */
 	unsigned int read_bytes; /* Number of bytes read during command   */
@@ -171,7 +215,7 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 	struct nand_chip *chip = mtd->priv;
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	lbus83xx_t *lbc = ctrl->regs;
+	fsl_lbus_t *lbc = ctrl->regs;
 	int buf_num;
 
 	ctrl->page = page_addr;
@@ -211,7 +255,7 @@ static int fsl_elbc_run_command(struct mtd_info *mtd)
 	struct nand_chip *chip = mtd->priv;
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	lbus83xx_t *lbc = ctrl->regs;
+	fsl_lbus_t *lbc = ctrl->regs;
 	long long end_tick;
 	u32 ltesr;
 
@@ -261,7 +305,7 @@ static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
 {
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	lbus83xx_t *lbc = ctrl->regs;
+	fsl_lbus_t *lbc = ctrl->regs;
 
 	if (priv->page_size) {
 		out_be32(&lbc->fir,
@@ -295,7 +339,7 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 	struct nand_chip *chip = mtd->priv;
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	lbus83xx_t *lbc = ctrl->regs;
+	fsl_lbus_t *lbc = ctrl->regs;
 
 	ctrl->use_mdr = 0;
 
@@ -633,7 +677,7 @@ static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 {
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	lbus83xx_t *lbc = ctrl->regs;
+	fsl_lbus_t *lbc = ctrl->regs;
 
 	if (ctrl->status != LTESR_CC)
 		return NAND_STATUS_FAIL;
@@ -693,13 +737,16 @@ static struct fsl_elbc_ctrl *elbc_ctrl;
 
 static void fsl_elbc_ctrl_init(void)
 {
-	immap_t *im = (immap_t *)CFG_IMMR;
-
 	elbc_ctrl = kzalloc(sizeof(*elbc_ctrl), GFP_KERNEL);
 	if (!elbc_ctrl)
 		return;
 
+#ifdef CONFIG_MPC85xx
+	elbc_ctrl->regs = (void *)CFG_MPC85xx_LBC_ADDR;
+#else
+	immap_t *im = (immap_t *)CFG_IMMR;
 	elbc_ctrl->regs = &im->lbus;
+#endif
 
 	/* clear event registers */
 	out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK);
diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h
index ea49ddc..b5b2cbd 100644
--- a/include/asm-ppc/fsl_lbc.h
+++ b/include/asm-ppc/fsl_lbc.h
@@ -307,4 +307,89 @@
 #define LTEDR_RAWA	0x00400000 /* Read-after-write-atomic error checking disable	*/
 #define LTEDR_CSD	0x00080000 /* Chip select error checking disable		*/
 
+/* FMR - Flash Mode Register
+ */
+#define FMR_CWTO		0x0000F000
+#define FMR_CWTO_SHIFT		12
+#define FMR_BOOT		0x00000800
+#define FMR_ECCM		0x00000100
+#define FMR_AL			0x00000030
+#define FMR_AL_SHIFT		4
+#define FMR_OP			0x00000003
+#define FMR_OP_SHIFT		0
+
+/* FIR - Flash Instruction Register
+ */
+#define FIR_OP0			0xF0000000
+#define FIR_OP0_SHIFT		28
+#define FIR_OP1			0x0F000000
+#define FIR_OP1_SHIFT		24
+#define FIR_OP2			0x00F00000
+#define FIR_OP2_SHIFT		20
+#define FIR_OP3			0x000F0000
+#define FIR_OP3_SHIFT		16
+#define FIR_OP4			0x0000F000
+#define FIR_OP4_SHIFT		12
+#define FIR_OP5			0x00000F00
+#define FIR_OP5_SHIFT		8
+#define FIR_OP6			0x000000F0
+#define FIR_OP6_SHIFT		4
+#define FIR_OP7			0x0000000F
+#define FIR_OP7_SHIFT		0
+#define FIR_OP_NOP		0x0 /* No operation and end of sequence */
+#define FIR_OP_CA		0x1 /* Issue current column address */
+#define FIR_OP_PA		0x2 /* Issue current block+page address */
+#define FIR_OP_UA		0x3 /* Issue user defined address */
+#define FIR_OP_CM0		0x4 /* Issue command from FCR[CMD0] */
+#define FIR_OP_CM1		0x5 /* Issue command from FCR[CMD1] */
+#define FIR_OP_CM2		0x6 /* Issue command from FCR[CMD2] */
+#define FIR_OP_CM3		0x7 /* Issue command from FCR[CMD3] */
+#define FIR_OP_WB		0x8 /* Write FBCR bytes from FCM buffer */
+#define FIR_OP_WS		0x9 /* Write 1 or 2 bytes from MDR[AS] */
+#define FIR_OP_RB		0xA /* Read FBCR bytes to FCM buffer */
+#define FIR_OP_RS		0xB /* Read 1 or 2 bytes to MDR[AS] */
+#define FIR_OP_CW0		0xC /* Wait then issue FCR[CMD0] */
+#define FIR_OP_CW1		0xD /* Wait then issue FCR[CMD1] */
+#define FIR_OP_RBW		0xE /* Wait then read FBCR bytes */
+#define FIR_OP_RSW		0xF /* Wait then read 1 or 2 bytes */
+
+/* FCR - Flash Command Register
+ */
+#define FCR_CMD0		0xFF000000
+#define FCR_CMD0_SHIFT		24
+#define FCR_CMD1		0x00FF0000
+#define FCR_CMD1_SHIFT		16
+#define FCR_CMD2		0x0000FF00
+#define FCR_CMD2_SHIFT		8
+#define FCR_CMD3		0x000000FF
+#define FCR_CMD3_SHIFT		0
+
+/* FBAR - Flash Block Address Register
+ */
+#define FBAR_BLK		0x00FFFFFF
+
+/* FPAR - Flash Page Address Register
+ */
+#define FPAR_SP_PI		0x00007C00
+#define FPAR_SP_PI_SHIFT	10
+#define FPAR_SP_MS		0x00000200
+#define FPAR_SP_CI		0x000001FF
+#define FPAR_SP_CI_SHIFT	0
+#define FPAR_LP_PI		0x0003F000
+#define FPAR_LP_PI_SHIFT	12
+#define FPAR_LP_MS		0x00000800
+#define FPAR_LP_CI		0x000007FF
+#define FPAR_LP_CI_SHIFT	0
+
+/* LTESR - Transfer Error Status Register
+ */
+#define LTESR_BM		0x80000000
+#define LTESR_FCT		0x40000000
+#define LTESR_PAR		0x20000000
+#define LTESR_WP		0x04000000
+#define LTESR_ATMW		0x00800000
+#define LTESR_ATMR		0x00400000
+#define LTESR_CS		0x00080000
+#define LTESR_CC		0x00000001
+
 #endif /* __ASM_PPC_FSL_LBC_H */
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 5d82bb4..e3cf84d 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -1145,91 +1145,6 @@
  */
 #define PMCCR1_POWER_OFF		0x00000020
 
-/* FMR - Flash Mode Register
- */
-#define FMR_CWTO		0x0000F000
-#define FMR_CWTO_SHIFT		12
-#define FMR_BOOT		0x00000800
-#define FMR_ECCM		0x00000100
-#define FMR_AL			0x00000030
-#define FMR_AL_SHIFT		4
-#define FMR_OP			0x00000003
-#define FMR_OP_SHIFT		0
-
-/* FIR - Flash Instruction Register
- */
-#define FIR_OP0			0xF0000000
-#define FIR_OP0_SHIFT		28
-#define FIR_OP1			0x0F000000
-#define FIR_OP1_SHIFT		24
-#define FIR_OP2			0x00F00000
-#define FIR_OP2_SHIFT		20
-#define FIR_OP3			0x000F0000
-#define FIR_OP3_SHIFT		16
-#define FIR_OP4			0x0000F000
-#define FIR_OP4_SHIFT		12
-#define FIR_OP5			0x00000F00
-#define FIR_OP5_SHIFT		8
-#define FIR_OP6			0x000000F0
-#define FIR_OP6_SHIFT		4
-#define FIR_OP7			0x0000000F
-#define FIR_OP7_SHIFT		0
-#define FIR_OP_NOP		0x0 /* No operation and end of sequence */
-#define FIR_OP_CA		0x1 /* Issue current column address */
-#define FIR_OP_PA		0x2 /* Issue current block+page address */
-#define FIR_OP_UA		0x3 /* Issue user defined address */
-#define FIR_OP_CM0		0x4 /* Issue command from FCR[CMD0] */
-#define FIR_OP_CM1		0x5 /* Issue command from FCR[CMD1] */
-#define FIR_OP_CM2		0x6 /* Issue command from FCR[CMD2] */
-#define FIR_OP_CM3		0x7 /* Issue command from FCR[CMD3] */
-#define FIR_OP_WB		0x8 /* Write FBCR bytes from FCM buffer */
-#define FIR_OP_WS		0x9 /* Write 1 or 2 bytes from MDR[AS] */
-#define FIR_OP_RB		0xA /* Read FBCR bytes to FCM buffer */
-#define FIR_OP_RS		0xB /* Read 1 or 2 bytes to MDR[AS] */
-#define FIR_OP_CW0		0xC /* Wait then issue FCR[CMD0] */
-#define FIR_OP_CW1		0xD /* Wait then issue FCR[CMD1] */
-#define FIR_OP_RBW		0xE /* Wait then read FBCR bytes */
-#define FIR_OP_RSW		0xF /* Wait then read 1 or 2 bytes */
-
-/* FCR - Flash Command Register
- */
-#define FCR_CMD0		0xFF000000
-#define FCR_CMD0_SHIFT		24
-#define FCR_CMD1		0x00FF0000
-#define FCR_CMD1_SHIFT		16
-#define FCR_CMD2		0x0000FF00
-#define FCR_CMD2_SHIFT		8
-#define FCR_CMD3		0x000000FF
-#define FCR_CMD3_SHIFT		0
-
-/* FBAR - Flash Block Address Register
- */
-#define FBAR_BLK		0x00FFFFFF
-
-/* FPAR - Flash Page Address Register
- */
-#define FPAR_SP_PI		0x00007C00
-#define FPAR_SP_PI_SHIFT	10
-#define FPAR_SP_MS		0x00000200
-#define FPAR_SP_CI		0x000001FF
-#define FPAR_SP_CI_SHIFT	0
-#define FPAR_LP_PI		0x0003F000
-#define FPAR_LP_PI_SHIFT	12
-#define FPAR_LP_MS		0x00000800
-#define FPAR_LP_CI		0x000007FF
-#define FPAR_LP_CI_SHIFT	0
-
-/* LTESR - Transfer Error Status Register
- */
-#define LTESR_BM		0x80000000
-#define LTESR_FCT		0x40000000
-#define LTESR_PAR		0x20000000
-#define LTESR_WP		0x04000000
-#define LTESR_ATMW		0x00800000
-#define LTESR_ATMR		0x00400000
-#define LTESR_CS		0x00080000
-#define LTESR_CC		0x00000001
-
 /* DDRCDR - DDR Control Driver Register
  */
 #define DDRCDR_DHC_EN		0x80000000
-- 
1.5.4

[U-Boot] [PATCH 3/4] Enable NAND support for MPC8536DS board

[Jason Jin]

Define NAND support the 8536DS board. Add mem space and corresponding
law/tlb entries for it.

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
---
 board/freescale/mpc8536ds/law.c |    1 +
 board/freescale/mpc8536ds/tlb.c |    4 +++
 include/configs/MPC8536DS.h     |   52 ++++++++++++++++++++++++++++++++++++++-
 3 files changed, 56 insertions(+), 1 deletions(-)

diff --git a/board/freescale/mpc8536ds/law.c b/board/freescale/mpc8536ds/law.c
index cdf5215..84b23a3 100644
--- a/board/freescale/mpc8536ds/law.c
+++ b/board/freescale/mpc8536ds/law.c
@@ -38,6 +38,7 @@ struct law_entry law_table[] = {
 	SET_LAW(CFG_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
 	SET_LAW(CFG_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
 	SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+	SET_LAW(CFG_NAND_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c
index 28a9fa8..55e5702 100644
--- a/board/freescale/mpc8536ds/tlb.c
+++ b/board/freescale/mpc8536ds/tlb.c
@@ -66,6 +66,10 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, CFG_PCI1_IO_PHYS, CFG_PCI1_IO_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_256K, 1),
+
+	SET_TLB_ENTRY(1, CFG_NAND_BASE, CFG_NAND_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_16M, 1),
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 17cc934..4487a9e 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -162,8 +162,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * 0xXXXX_XXXX	0xXXXX_XXXX	SRAM			YZ M Cacheable
  *
  * Localbus non-cacheable
- * 0xe000_0000	0xe80f_ffff	Promjet/free		128M non-cacheable
+ * 0xe000_0000	0xe7ff_ffff	Promjet/free		128M non-cacheable
  * 0xe800_0000	0xefff_ffff	FLASH			128M non-cacheable
+ * 0xf000_0000	0xf0ff_ffff	NAND			16M non-cacheable
  * 0xffdf_0000	0xffdf_7fff	PIXIS			32K non-cacheable TLB0
  * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
  * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
@@ -250,6 +251,55 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
 #define CFG_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
 
+#define CFG_NAND_BASE           0xf0000000
+#define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE, CFG_NAND_BASE + 0x40000, \
+				CFG_NAND_BASE + 0x80000, CFG_NAND_BASE + 0xC0000}
+#define CFG_MAX_NAND_DEVICE	4
+#define NAND_MAX_CHIPS		1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND	1
+#define CONFIG_NAND_FSL_ELBC	1
+#define CFG_NAND_BLOCK_SIZE	(128 * 1024)
+
+/* NAND flash config */
+#define CFG_NAND_BR_PRELIM      ( CFG_NAND_BASE \
+				| (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+				| BR_PS_8               /* Port Size = 8 bit */ \
+				| BR_MS_FCM             /* MSEL = FCM */ \
+				| BR_V)                 /* valid */
+#define CFG_NAND_OR_PRELIM      ( 0xFFFC0000            /* length 256K */ \
+				| OR_FCM_PGS            /*Large Page*/ \
+				| OR_FCM_CSCT \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR)
+
+#define CFG_BR2_PRELIM          CFG_NAND_BR_PRELIM  /* NAND Base Address */
+#define CFG_OR2_PRELIM          CFG_NAND_OR_PRELIM  /* NAND Options */
+
+#define CFG_BR4_PRELIM          ((CFG_NAND_BASE + 0x40000)\
+				| (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+				| BR_PS_8               /* Port Size = 8 bit */ \
+				| BR_MS_FCM             /* MSEL = FCM */ \
+				| BR_V)                 /* valid */
+#define CFG_OR4_PRELIM          CFG_NAND_OR_PRELIM	/* NAND Options */
+
+#define CFG_BR5_PRELIM          ((CFG_NAND_BASE + 0x80000)\
+				| (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+				| BR_PS_8               /* Port Size = 8 bit */ \
+				| BR_MS_FCM             /* MSEL = FCM */ \
+				| BR_V)                 /* valid */
+#define CFG_OR5_PRELIM          CFG_NAND_OR_PRELIM	/* NAND Options */
+
+#define CFG_BR6_PRELIM          ((CFG_NAND_BASE + 0xC0000)\
+				| (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+				| BR_PS_8               /* Port Size = 8 bit */ \
+				| BR_MS_FCM             /* MSEL = FCM */ \
+				| BR_V)                 /* valid */
+#define CFG_OR6_PRELIM          CFG_NAND_OR_PRELIM	/* NAND Options */
+
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
  * shorted - index 1
-- 
1.5.4

[U-Boot] [PATCH 4/4] Enable NAND support for MPC8572DS board.

[Jason Jin]

Define NAND support the 8572DS board. Add mem space and corresponding
law/tlb entries for it.

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
---
 board/freescale/mpc8572ds/law.c |    1 +
 board/freescale/mpc8572ds/tlb.c |    5 ++++
 include/configs/MPC8572DS.h     |   51 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 57 insertions(+), 0 deletions(-)

diff --git a/board/freescale/mpc8572ds/law.c b/board/freescale/mpc8572ds/law.c
index d69b593..5094de7 100644
--- a/board/freescale/mpc8572ds/law.c
+++ b/board/freescale/mpc8572ds/law.c
@@ -36,6 +36,7 @@ struct law_entry law_table[] = {
 	SET_LAW(CFG_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
 	SET_LAW(CFG_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
 	SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+	SET_LAW(CFG_NAND_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c
index 965356a..df9dc50 100644
--- a/board/freescale/mpc8572ds/tlb.c
+++ b/board/freescale/mpc8572ds/tlb.c
@@ -80,6 +80,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, CFG_PCIE3_IO_PHYS, CFG_PCIE3_IO_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 6, BOOKE_PAGESZ_256K, 1),
+
+	/* *I*G - NAND */
+	SET_TLB_ENTRY(1, CFG_NAND_BASE, CFG_NAND_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_16M, 1),
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index b0094f3..ba305ff 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -166,6 +166,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * Localbus non-cacheable
  * 0xe000_0000	0xe80f_ffff	Promjet/free		128M non-cacheable
  * 0xe800_0000	0xefff_ffff	FLASH			128M non-cacheable
+ * 0xf000_0000	0xf0ff_ffff	NAND			16M non-cacheable
  * 0xffdf_0000	0xffdf_7fff	PIXIS			32K non-cacheable TLB0
  * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
  * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
@@ -252,6 +253,56 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
 #define CFG_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
 
+#define CFG_NAND_BASE           0xf0000000
+#define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE, CFG_NAND_BASE + 0x40000, \
+				CFG_NAND_BASE + 0x80000, CFG_NAND_BASE + 0xC0000}
+#define CFG_MAX_NAND_DEVICE	4
+#define NAND_MAX_CHIPS		1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND	1
+#define CONFIG_NAND_FSL_ELBC	1
+#define CFG_NAND_BLOCK_SIZE	(128 * 1024)
+
+/* NAND flash config */
+#define CFG_NAND_BR_PRELIM      (CFG_NAND_BASE \
+				| (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+				| BR_PS_8               /* Port Size = 8 bit */ \
+				| BR_MS_FCM             /* MSEL = FCM */ \
+				| BR_V)                 /* valid */
+#define CFG_NAND_OR_PRELIM      (0xFFFC0000            /* length 256K */ \
+				| OR_FCM_PGS            /*Large Page*/ \
+				| OR_FCM_CSCT \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR)
+
+#define CFG_BR2_PRELIM          CFG_NAND_BR_PRELIM  /* NAND Base Address */
+#define CFG_OR2_PRELIM          CFG_NAND_OR_PRELIM  /* NAND Options */
+
+#define CFG_BR4_PRELIM          ((CFG_NAND_BASE + 0x40000)\
+				| (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+				| BR_PS_8               /* Port Size = 8 bit */ \
+				| BR_MS_FCM             /* MSEL = FCM */ \
+				| BR_V)                 /* valid */
+#define CFG_OR4_PRELIM          CFG_NAND_OR_PRELIM	/* NAND Options */
+
+#define CFG_BR5_PRELIM          ((CFG_NAND_BASE + 0x80000)\
+				| (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+				| BR_PS_8               /* Port Size = 8 bit */ \
+				| BR_MS_FCM             /* MSEL = FCM */ \
+				| BR_V)                 /* valid */
+#define CFG_OR5_PRELIM          CFG_NAND_OR_PRELIM	/* NAND Options */
+
+#define CFG_BR6_PRELIM          ((CFG_NAND_BASE + 0xC0000)\
+				| (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+				| BR_PS_8               /* Port Size = 8 bit */ \
+				| BR_MS_FCM             /* MSEL = FCM */ \
+				| BR_V)                 /* valid */
+#define CFG_OR6_PRELIM          CFG_NAND_OR_PRELIM	/* NAND Options */
+
+
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
  * shorted - index 1
-- 
1.5.4

[U-Boot] [PATCH 2/4] Make the fsl_elbc_nand driver work for both 83xx and 85xx

[Scott Wood]

On Fri, Sep 19, 2008 at 05:32:50PM +0800, Jason Jin wrote:
> +/*
> + * Local Bus Controller Registers.
> + */
> +typedef struct lbus_bank {
> +	u32 br;			/* Base Register */
> +	u32 or;			/* Option Register */
> +} lbus_bank_t;
> +
> +typedef struct fsl_lbus {
> +	lbus_bank_t bank[8];
> +	u8 res0[0x28];
> +	u32 mar;		/* UPM Address Register */
> +	u8 res1[0x4];
> +	u32 mamr;		/* UPMA Mode Register */
> +	u32 mbmr;		/* UPMB Mode Register */
> +	u32 mcmr;		/* UPMC Mode Register */
> +	u8 res2[0x8];
> +	u32 mrtpr;		/* Memory Refresh Timer Prescaler Register */
> +	u32 mdr;		/* UPM Data Register */
> +	u8 res3[0x4];
> +	u32 lsor;		/* Special Operation Initiation Register */
> +	u32 lsdmr;		/* SDRAM Mode Register */
> +	u8 res4[0x8];
> +	u32 lurt;		/* UPM Refresh Timer */
> +	u32 lsrt;		/* SDRAM Refresh Timer */
> +	u8 res5[0x8];
> +	u32 ltesr;		/* Transfer Error Status Register */
> +	u32 ltedr;		/* Transfer Error Disable Register */
> +	u32 lteir;		/* Transfer Error Interrupt Register */
> +	u32 lteatr;		/* Transfer Error Attributes Register */
> +	u32 ltear;		/* Transfer Error Address Register */
> +	u8 res6[0xC];
> +	u32 lbcr;		/* Configuration Register */
> +	u32 lcrr;		/* Clock Ratio Register */
> +	u8 res7[0x8];
> +	u32 fmr;		/* Flash Mode Register */
> +	u32 fir;		/* Flash Instruction Register */
> +	u32 fcr;		/* Flash Command Register */
> +	u32 fbar;		/* Flash Block Addr Register */
> +	u32 fpar;		/* Flash Page Addr Register */
> +	u32 fbcr;		/* Flash Byte Count Register */
> +	u8 res8[0xF08];
> +}fsl_lbus_t;

Space after brace.

Can we put this in a header file that is shared by immap_83xx.h,
immap_85xx.h, etc., rather than duplicating it here?

>  static void fsl_elbc_ctrl_init(void)
>  {
> -	immap_t *im = (immap_t *)CFG_IMMR;
> -
>  	elbc_ctrl = kzalloc(sizeof(*elbc_ctrl), GFP_KERNEL);
>  	if (!elbc_ctrl)
>  		return;
>  
> +#ifdef CONFIG_MPC85xx
> +	elbc_ctrl->regs = (void *)CFG_MPC85xx_LBC_ADDR;
> +#else
> +	immap_t *im = (immap_t *)CFG_IMMR;
>  	elbc_ctrl->regs = &im->lbus;
> +#endif

Did you try building this on 83xx?  You'll get a type conflict warning
because you duplicated the struct.

-Scott

[U-Boot] [PATCH 2/4] Make the fsl_elbc_nand driver work for both 83xxand 85xx

[Jin Zhengxiong-R64188]

> -----Original Message-----
> From: Wood Scott-B07421 
> Sent: Wednesday, October 08, 2008 12:33 AM
> To: Jin Zhengxiong-R64188
> Cc: u-boot at lists.denx.de
> Subject: Re: [PATCH 2/4] Make the fsl_elbc_nand driver work 
> for both 83xxand 85xx
> 
> On Fri, Sep 19, 2008 at 05:32:50PM +0800, Jason Jin wrote:
> > +/*
> > + * Local Bus Controller Registers.
> > + */
> > +typedef struct lbus_bank {
> > +	u32 br;			/* Base Register */
> > +	u32 or;			/* Option Register */
> > +} lbus_bank_t;
> > +
> > +typedef struct fsl_lbus {
> > +	lbus_bank_t bank[8];
> > +	u8 res0[0x28];
> > +	u32 mar;		/* UPM Address Register */
> > +	u8 res1[0x4];
> > +	u32 mamr;		/* UPMA Mode Register */
> > +	u32 mbmr;		/* UPMB Mode Register */
> > +	u32 mcmr;		/* UPMC Mode Register */
> > +	u8 res2[0x8];
> > +	u32 mrtpr;		/* Memory Refresh Timer 
> Prescaler Register */
> > +	u32 mdr;		/* UPM Data Register */
> > +	u8 res3[0x4];
> > +	u32 lsor;		/* Special Operation Initiation 
> Register */
> > +	u32 lsdmr;		/* SDRAM Mode Register */
> > +	u8 res4[0x8];
> > +	u32 lurt;		/* UPM Refresh Timer */
> > +	u32 lsrt;		/* SDRAM Refresh Timer */
> > +	u8 res5[0x8];
> > +	u32 ltesr;		/* Transfer Error Status Register */
> > +	u32 ltedr;		/* Transfer Error Disable Register */
> > +	u32 lteir;		/* Transfer Error Interrupt Register */
> > +	u32 lteatr;		/* Transfer Error Attributes Register */
> > +	u32 ltear;		/* Transfer Error Address Register */
> > +	u8 res6[0xC];
> > +	u32 lbcr;		/* Configuration Register */
> > +	u32 lcrr;		/* Clock Ratio Register */
> > +	u8 res7[0x8];
> > +	u32 fmr;		/* Flash Mode Register */
> > +	u32 fir;		/* Flash Instruction Register */
> > +	u32 fcr;		/* Flash Command Register */
> > +	u32 fbar;		/* Flash Block Addr Register */
> > +	u32 fpar;		/* Flash Page Addr Register */
> > +	u32 fbcr;		/* Flash Byte Count Register */
> > +	u8 res8[0xF08];
> > +}fsl_lbus_t;
> 
> Space after brace.
> 
> Can we put this in a header file that is shared by 
> immap_83xx.h, immap_85xx.h, etc., rather than duplicating it here?
> 
Thanks.
I was trying to avoid too much changes to the code, which maybe result
in other functions
can not work. Actually, As the different immap definition, to completly
avoid the duplicating, we need to merge the lbc immap for 85xx/83xx and
change the related code.

There is already a fsl_lbc.h file in include/asm but it is included by
some .S file and can not move the structure into it. How about define a
immap_fsl_lbc.h file for the structure? 

> >  static void fsl_elbc_ctrl_init(void)
> >  {
> > -	immap_t *im = (immap_t *)CFG_IMMR;
> > -
> >  	elbc_ctrl = kzalloc(sizeof(*elbc_ctrl), GFP_KERNEL);
> >  	if (!elbc_ctrl)
> >  		return;
> >  
> > +#ifdef CONFIG_MPC85xx
> > +	elbc_ctrl->regs = (void *)CFG_MPC85xx_LBC_ADDR; #else
> > +	immap_t *im = (immap_t *)CFG_IMMR;
> >  	elbc_ctrl->regs = &im->lbus;
> > +#endif
> 
> Did you try building this on 83xx?  You'll get a type 
> conflict warning because you duplicated the struct.

Thanks, If we still define the structure in the file, we need to change
the structure name.

Jason

[U-Boot] [PATCH 2/4] Make the fsl_elbc_nand driver work for both 83xxand 85xx

[Anton Vorontsov]

On Wed, Oct 08, 2008 at 05:45:01PM +0800, Jin Zhengxiong-R64188 wrote:
[...]
> Thanks.
> I was trying to avoid too much changes to the code, which maybe result
> in other functions
> can not work. Actually, As the different immap definition, to completly
> avoid the duplicating, we need to merge the lbc immap for 85xx/83xx and
> change the related code.
> 
> There is already a fsl_lbc.h file in include/asm but it is included by
> some .S file and can not move the structure into it.

You can surround it with #ifndef __ASSEMBLY__

-- 
Anton Vorontsov
email: cbouatmailru at gmail.com
irc://irc.freenode.net/bd2

[U-Boot] [PATCH 1/4] Fix the NAND size overflow issue.

[Jens Gehrlein]

Hi Jason,

> -----Original Message-----
> From: u-boot-bounces at lists.denx.de
> [mailto:u-boot-bounces at lists.denx.de]On Behalf Of Jason Jin
> Sent: Friday, September 19, 2008 11:33 AM
> To: scottwood at freescale.com
> Cc: u-boot at lists.denx.de; Jason Jin
> Subject: [U-Boot] [PATCH 1/4] Fix the NAND size overflow issue.
> 
> 
> When the NAND size is or large than 4G, the size will overflow,
> The adjustment in this patch try to fix this.
> 
> Signed-off-by: Jason Jin <Jason.jin@freescale.com>
> ---
>  drivers/mtd/nand/nand.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c
> index ebd2acd..71a0e4b 100644
> --- a/drivers/mtd/nand/nand.c
> +++ b/drivers/mtd/nand/nand.c
> @@ -63,11 +63,11 @@ void nand_init(void)
>  	unsigned int size = 0;
>  	for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) {
>  		nand_init_chip(&nand_info[i], &nand_chip[i], 
> base_address[i]);
> -		size += nand_info[i].size;
> +		size += nand_info[i].size / 1024;
>  		if (nand_curr_device == -1)
>  			nand_curr_device = i;
>  	}
> -	printf("%u MiB\n", size / (1024 * 1024));
      ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
According to this line I suppose, the value of nand_info[i].size
is in Bytes. So, if the NAND chip is >= 4 GiB this variable
has already been overflowed, when nand_init_chip returns.
Indeed, I didn't check the source code of the NAND driver. Am I
wrong or did you modify the driver?

Kind Regards,
Jens

[U-Boot] [PATCH 1/4] Fix the NAND size overflow issue.

[Jin Zhengxiong-R64188]

 

> -----Original Message-----
> From: Jens Gehrlein [mailto:Jens.Gehrlein at tqs.de] 
> Sent: Friday, September 19, 2008 6:05 PM
> To: Jin Zhengxiong-R64188; Wood Scott-B07421
> Cc: u-boot at lists.denx.de
> Subject: RE: [U-Boot] [PATCH 1/4] Fix the NAND size overflow issue.
> 
> Hi Jason,
> 
> > -----Original Message-----
> > From: u-boot-bounces at lists.denx.de
> > [mailto:u-boot-bounces at lists.denx.de]On Behalf Of Jason Jin
> > Sent: Friday, September 19, 2008 11:33 AM
> > To: scottwood at freescale.com
> > Cc: u-boot at lists.denx.de; Jason Jin
> > Subject: [U-Boot] [PATCH 1/4] Fix the NAND size overflow issue.
> > 
> > 
> > When the NAND size is or large than 4G, the size will overflow, The 
> > adjustment in this patch try to fix this.
> > 
> > Signed-off-by: Jason Jin <Jason.jin@freescale.com>
> > ---
> >  drivers/mtd/nand/nand.c |    4 ++--
> >  1 files changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/mtd/nand/nand.c 
> b/drivers/mtd/nand/nand.c index 
> > ebd2acd..71a0e4b 100644
> > --- a/drivers/mtd/nand/nand.c
> > +++ b/drivers/mtd/nand/nand.c
> > @@ -63,11 +63,11 @@ void nand_init(void)
> >  	unsigned int size = 0;
> >  	for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) {
> >  		nand_init_chip(&nand_info[i], &nand_chip[i], 
> base_address[i]);
> > -		size += nand_info[i].size;
> > +		size += nand_info[i].size / 1024;
> >  		if (nand_curr_device == -1)
> >  			nand_curr_device = i;
> >  	}
> > -	printf("%u MiB\n", size / (1024 * 1024));
>       ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> According to this line I suppose, the value of 
> nand_info[i].size is in Bytes. So, if the NAND chip is >= 4 
> GiB this variable has already been overflowed, when 
> nand_init_chip returns.
> Indeed, I didn't check the source code of the NAND driver. Am 
> I wrong or did you modify the driver?
> 
Hi, Jens,
You are right, the nand_info[i].size is in Bytes. and this patch just 
can fix those chips with memory cell less than 4GBytes.
The  nand_info[i].size is widly used in u-boot, If change it to MByte, 
lots of tests need to do.

Thanks
Jaosn 

[U-Boot] [PATCH 1/4] Fix the NAND size overflow issue.

[Wolfgang Denk]

Dear Jason Jin,

In message <1221816772-23220-1-git-send-email-Jason.jin@freescale.com> you wrote:
> When the NAND size is or large than 4G, the size will overflow,
> The adjustment in this patch try to fix this.
> 
> Signed-off-by: Jason Jin <Jason.jin@freescale.com>
> ---
>  drivers/mtd/nand/nand.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c
> index ebd2acd..71a0e4b 100644
> --- a/drivers/mtd/nand/nand.c
> +++ b/drivers/mtd/nand/nand.c
> @@ -63,11 +63,11 @@ void nand_init(void)
>  	unsigned int size = 0;
>  	for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) {
>  		nand_init_chip(&nand_info[i], &nand_chip[i], base_address[i]);
> -		size += nand_info[i].size;
> +		size += nand_info[i].size / 1024;
>  		if (nand_curr_device == -1)
>  			nand_curr_device = i;
>  	}
> -	printf("%u MiB\n", size / (1024 * 1024));
> +	printf("%u MiB\n", size / 1024);

I think the comment is misleading.

Assuming we have a single NAND device that is bigger than 4 GiB, then
the overflow would actually happen earlier, i. e.  when  storing  the
size in nand_info[].size, as nand_info[].size is an "u_int32_t".

So the only situation your patch can fix is when  there  are  several
NAND  devices,  each  of  them smaller than 4 GiB, but the total size
exceeds this limit.

Applied after changing the comment.

Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
I think it's a new feature. Don't tell anyone it was an accident. :-)
  -- Larry Wall on s/foo/bar/eieio in <10911@jpl-devvax.JPL.NASA.GOV>