From: Stefan Roese <sr@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] 440spe MQ initialization
Date: Fri, 17 Oct 2008 11:42:40 +0200 [thread overview]
Message-ID: <200810171142.40636.sr@denx.de> (raw)
In-Reply-To: <20081016231014.97657807D6B9@gemini.denx.de>
Hi Wolfgang,
On Friday 17 October 2008, Wolfgang Denk wrote:
> > Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC
> > values. This fixes the occasional 440SPe hard locking issues when the
> > 440SPe's dedicated DMA engines are used (e.g. by the h/w accelerated RAID
> > driver).
> >
> > Previously the appropriate initialization had been made in Linux, by the
> > ppc440spe ADMA driver, which is wrong because modifying the MQ
> > configuration registers after normal operation has begun is not supported
> > and could have unpredictable results.
> >
> > Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
> > ---
> > cpu/ppc4xx/44x_spd_ddr2.c | 10 ++++++----
> > include/asm-ppc/ppc4xx-sdram.h | 5 +++++
> > 2 files changed, 11 insertions(+), 4 deletions(-)
>
> I must admit that I lost track in the discussion following this
> posting what the real state of affairs is now. Do we need to change
> anything in U-Boot, or not, and why not?
I also lost track of whats really needed, I'm afraid. That's why I asked about
this a few weeks ago. Here an extract from the last mail:
On Thursday 25 September 2008, Prodyut Hazarika wrote:
> > So please let me know if Yuri's original MQ patch should be applied and
> > if there is another PLB arbiter patch that should be applied too.
>
> Yuri's patch does the following
> - set RLPM (read passing limit) bits in MQ register to 1,
> - set WRCL (MCIF cycle limit) in MQ registers to 1.
> In my testing, as far as I can remember, these values were set to 1 by
> default. I had tested with Canyonlands, Kilauea, Katmai and Glacier boards.
> So unless Yuri found that these values were not default values in some
> processor, Yuri's patch should be applied.
So it seems that the current code relies on some already preset (default)
values in those registers. I don't really like this. I'll try to provide a
patch that configures those registers completely in a short while.
It would be great if Yuri could test this on a target to see if we are still
missing something.
Best regards,
Stefan
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
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next prev parent reply other threads:[~2008-10-17 9:42 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-09-23 8:37 [U-Boot] [PATCH] 440spe MQ initialization Yuri Tikhonov
2008-09-23 9:22 ` Stefan Roese
2008-09-23 9:36 ` Yuri Tikhonov
2008-09-23 9:43 ` Stefan Roese
2008-09-23 13:31 ` Olga Buchonina
2008-09-23 15:25 ` Prodyut Hazarika
2008-09-23 15:35 ` Yuri Tikhonov
2008-09-23 15:37 ` Prodyut Hazarika
2008-09-23 15:45 ` Yuri Tikhonov
2008-09-25 7:42 ` Stefan Roese
2008-09-25 13:17 ` Prodyut Hazarika
2008-09-23 15:31 ` Prodyut Hazarika
2008-10-16 23:10 ` Wolfgang Denk
2008-10-17 9:42 ` Stefan Roese [this message]
2008-10-17 10:15 ` Wolfgang Denk
2008-10-17 10:47 ` Stefan Roese
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