[U-Boot] new board SDRAM conf

[U-Boot] new board SDRAM conf

[조기성]

Hi!, 

I?m using ppc440Ep and using u-boot1.3.3

 I?m using u-boot1.1.3 with Yosemite configuration.

When I boot with Yosemite conf , it stops SDRAM:256 , it? shows cpu, pci
conf

My New Board configuration is only different SDRAM Size and Flash Size.

 

Where can I modify my Yosemite configuration. 

Init.S and Yosemite.h

 

Best Regards,

J

 

 

###### Yosemite Cofiguration #####################

FLASH (CS0)

64MEGA Boot Flash

 

SDRAM

bank 0- 128MB

bank 1- 128MB

 

 

!!!###### My Board #####################

FLASH (CS0)

8MEGA Boot Flash

 

SDRAM

bank 0- 128MB

bank 1- NONE

 

 

 

[U-Boot] new board SDRAM conf

[Stefan Roese]

On Monday 03 November 2008, ??? wrote:
> I?m using ppc440Ep and using u-boot1.3.3
>
>  I?m using u-boot1.1.3 with Yosemite configuration.

Please use the latest version from the DENX git repository.

> When I boot with Yosemite conf , it stops SDRAM:256 , it? shows cpu, pci
> conf

So it most likely crashed upon relocation into SDRAM. So its an SDRAM 
configuration problem.

> My New Board configuration is only different SDRAM Size and Flash Size.
>
>
> Where can I modify my Yosemite configuration.
>
> Init.S and Yosemite.h

Yosemite uses a board specific SDRAM init routine. I suggest that you use the 
common DDR2 init code by enabling it in your board config header 
(include/configs/board.h):

#define CONFIG_SDRAM_BANK0      1       /* init onboard DDR SDRAM bank 0*/

You can also define CONFIG_SYS_SDRAM_TABLE if you have an uncommon SDRAM 
configuration. What's the difference of your SDRAM configuration? 

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] new board SDRAM conf

[조기성]

Dear stefan.

I Made my board config header, and using yosemite's init.S & u-boot.lds, mft.c(Yosemite.c)
Only change config header , but it's not working . 
 
1. First The difference of my SDRAM configuration is 
***  (PPC440EP supported four external DDR_SDRAM Banks.) ***
But Our used only external DDR_SDRAM Bank_0(BANKSEL_0) on the New design Board.

2. Second my config header is 
Include/configs/mft.h
________________________________________________________________________________________
#define CONFIG_440EP		1	/* Specific PPC440EP support	*/
#define CONFIG_HOSTNAME		mft

#define CONFIG_440		1	/* ... PPC440 family		*/
#define CONFIG_4xx		1	/* ... PPC4xx family		*/
#define CONFIG_SYS_CLK_FREQ	66666666    /* external freq to pll	*/

#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/
#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
#define CONFIG_BOARD_RESET	1	/* call board_reset()		*/

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
#if 1 //steven
#define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)
#else
#define CFG_MONITOR_BASE	TEXT_BASE
#define CFG_SDRAM_BASE	        0x00000000	    /* _must_ be 0	*/
#define CFG_FLASH_BASE	        0xfc000000	    /* start of FLASH	*

...
/*-----------------------------------------------------------------------
 * DDR SDRAM
 *----------------------------------------------------------------------*/
#undef CONFIG_SPD_EEPROM	       /* Don't use SPD EEPROM for setup    */
#if 0 //steven
#define CFG_KBYTES_SDRAM        (128 * 1024)    /* 128MB		    */
#else
#define CFG_KBYTES_SDRAM        (64 * 1024)    /* 128MB		    */
#endif
#if 1 //steven
#define CFG_SDRAM_BANKS	        (2)
#else
#define CFG_SDRAM_BANKS	        (1)
#endif

define CONFIG_SDRAM_BANK0      1
_________________________________________________________________________________________



The difference of your SDRAM configuration?
>>> 


Best Regards.
Steven

-----Original Message-----
From: Stefan Roese [mailto:sr at denx.de] 
Sent: Monday, November 03, 2008 4:47 PM
To: u-boot at lists.denx.de; k9 at tibetsystem.com
Subject: Re: [U-Boot] new board SDRAM conf

On Monday 03 November 2008, ??? wrote:
> I?m using ppc440Ep and using u-boot1.3.3
>
>  I?m using u-boot1.1.3 with Yosemite configuration.

Please use the latest version from the DENX git repository.

> When I boot with Yosemite conf , it stops SDRAM:256 , it? shows cpu, pci
> conf

So it most likely crashed upon relocation into SDRAM. So its an SDRAM 
configuration problem.

> My New Board configuration is only different SDRAM Size and Flash Size.
>
>
> Where can I modify my Yosemite configuration.
>
> Init.S and Yosemite.h

Yosemite uses a board specific SDRAM init routine. I suggest that you use the 
common DDR2 init code by enabling it in your board config header 
(include/configs/board.h):

#define CONFIG_SDRAM_BANK0      1       /* init onboard DDR SDRAM bank 0*/

You can also define CONFIG_SYS_SDRAM_TABLE if you have an uncommon SDRAM 
configuration. What's the difference of your SDRAM configuration? 

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] new board SDRAM conf

[Stefan Roese]

Hi Steven,

On Monday 03 November 2008, ??? wrote:
> I Made my board config header, and using yosemite's init.S & u-boot.lds,
> mft.c(Yosemite.c) Only change config header , but it's not working .

You should create your own board port for this custom 440EP board.

> 1. First The difference of my SDRAM configuration is
> ***  (PPC440EP supported four external DDR_SDRAM Banks.) ***
> But Our used only external DDR_SDRAM Bank_0(BANKSEL_0) on the New design
> Board.

Yes. I already described how you should handle this DDR initialization in my 
last mail. Use the common code (cpu/ppc4xx/sdram.c). You probably need to 
change the CONFIG_SYS_SDRAM_TABLE for your board. Take a look at the p3p440.h 
header as an example.

BTW: SDRAM configuration is a complex matter. You definitely need to take a 
look at the PPC users manual and the SDRAM datasheet for this.

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] new board SDRAM conf

[조기성]

Hi, thanks in your replay.


I create  My own board port(MFT board) . create configuration header and init.S
But In the sdram.c(sdram_init->get_ram_size is 4 thus )func is failed , sdram is not founded . 
I think init.S is something wrong or CFG_MONITOR_BASE is  wrong ... . 

maybe you can point me to the right direction.

It's my board init.S

_____________________________________________________________________________________________________
tlbtab:
    tlbtab_start

    /*
     * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
     * speed up boot process. It is patched after relocation to enable SA_I
     */
    tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)

    /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
    tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )

    tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
    tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
    tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )

    /* PCI */
    tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
    tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
    tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
    tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )

    /* USB 2.0 Device */
    tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )

    tlbtab_en
_____________________________________________________________________________________________________

My SDRAM is  128MB mode 3, 13x10(4) 
And use external DDR_SDRAM Bank_0(BANKSEL_0) 



It's my board configuration header. 

_____________________________________________________________________________________________________
Include/configs/mft.h 
#define CONFIG_440EP		1	    /* Specifc GP support	*/
#define CONFIG_440		1	    /* ... PPC440 family	*/
#define CONFIG_4xx		1	    /* ... PPC4xx family	*/
#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
#define CONFIG_MISC_INIT_R	1	    /* Call misc_init_r		*/
#define CONFIG_SYS_CLK_FREQ	66666666    /* external freq to pll	*
#define CFG_FLASH_BASE	    	0xfc000000	    /* start of FLASH		*/
#define CFG_MONITOR_BASE    	CFG_FLASH_BASE	    /* start of monitor		*/

/*-----------------------------------------------------------------------
 * Initial RAM & stack pointer (placed in internal SRAM)
 *----------------------------------------------------------------------*/
#define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
#define CFG_INIT_RAM_ADDR	0x70000000  /* Initial RAM address	*/
#define CFG_ISRAM_BASE	 	CFG_INIT_RAM_ADDR	    /* internal SRAM		*/
#define CFG_INIT_RAM_END	(4 << 10)	    /* End of used area in RAM	*/
//#define CFG_GBL_DATA_SIZE	256	    /* num bytes initial data	*/
#define CFG_GBL_DATA_SIZE	128    /* num bytes initial data	*/

#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon*/
#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc*/

/*-----------------------------------------------------------------------
 * DDR SDRAM
 *----------------------------------------------------------------------*/
#undef CONFIG_SPD_EEPROM		/* Don't use SPD EEPROM for setup	*/
#define CONFIG_SDRAM_BANK0	1	/* init onboard DDR SDRAM bank 0*/
#define	CFG_SDRAM0_TR0		0x410A4012
#undef CONFIG_SDRAM_ECC		/* enable ECC support		*/

#if 1
#define CFG_SDRAM_TABLE	{ \
		{(128 << 20), 13, 0x000A4001}, /* 128MB mode 3, 13x10(4)*/ \
		{(128 << 20), 12, 0x000A2001}, /* 128MB mode 2, 13x10(4)*/ \
		{(64 << 20),  13, 0x00084001}, /* 64MB mode 3, 13x9(4)	*/ \
		{(64 << 20),  12, 0x00082001}, } /* 64MB mode 2, 13x9(4)	*


/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 *----------------------------------------------------------------------*/
#define CFG_FLASH0		0xFF800000
#define CFG_FLASH1		0xFF000000
#define CFG_FLASH2		0xFE800000
#define CFG_FLASH3		0xFE000000
#define CFG_USB			0xF0000000

/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
//#define CFG_EBC_PB0AP		0x03050200
#define CFG_EBC_PB0AP		0x03017300
#define CFG_EBC_PB0CR		(CFG_FLASH0 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit *

_____________________________________________________________________________________________________




Best Regards.
Steven.

-----Original Message-----
From: Stefan Roese [mailto:sr at denx.de] 
Sent: Monday, November 03, 2008 7:11 PM
To: u-boot at lists.denx.de; k9@tibetsystem.com
Subject: Re: [U-Boot] new board SDRAM conf

Hi Steven,

On Monday 03 November 2008, ??? wrote:
> I Made my board config header, and using yosemite's init.S & u-boot.lds,
> mft.c(Yosemite.c) Only change config header , but it's not working .

You should create your own board port for this custom 440EP board.

> 1. First The difference of my SDRAM configuration is
> ***  (PPC440EP supported four external DDR_SDRAM Banks.) ***
> But Our used only external DDR_SDRAM Bank_0(BANKSEL_0) on the New design
> Board.

Yes. I already described how you should handle this DDR initialization in my 
last mail. Use the common code (cpu/ppc4xx/sdram.c). You probably need to 
change the CONFIG_SYS_SDRAM_TABLE for your board. Take a look at the p3p440.h 
header as an example.

BTW: SDRAM configuration is a complex matter. You definitely need to take a 
look at the PPC users manual and the SDRAM datasheet for this.

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] new board SDRAM conf

[Stefan Roese]

On Monday 03 November 2008, ??? wrote:
> I create  My own board port(MFT board) . create configuration header and
> init.S But In the sdram.c(sdram_init->get_ram_size is 4 thus )func is
> failed , sdram is not founded . I think init.S is something wrong or
> CFG_MONITOR_BASE is  wrong ... .
>
> maybe you can point me to the right direction.
>
> It's my board init.S

Your init.S is not optimal but at least not the reason for the problem. You 
are programming a 256MB TLB entry for SDRAM. This is more than enough for 
your 128MB. You should fix this at some time but it not the problem right 
now. CFG_MONITOR_BASE is also most likely not the problem.

<snip>

> My SDRAM is  128MB mode 3, 13x10(4)
> And use external DDR_SDRAM Bank_0(BANKSEL_0)

OK.

<snip>

> /*-----------------------------------------------------------------------
>  * DDR SDRAM
>  *----------------------------------------------------------------------*/
> #undef CONFIG_SPD_EEPROM		/* Don't use SPD EEPROM for setup	*/
> #define CONFIG_SDRAM_BANK0	1	/* init onboard DDR SDRAM bank 0*/
> #define	CFG_SDRAM0_TR0		0x410A4012
> #undef CONFIG_SDRAM_ECC		/* enable ECC support		*/
>
> #if 1
> #define CFG_SDRAM_TABLE	{ \
> 		{(128 << 20), 13, 0x000A4001}, /* 128MB mode 3, 13x10(4)*/ \
> 		{(128 << 20), 12, 0x000A2001}, /* 128MB mode 2, 13x10(4)*/ \
> 		{(64 << 20),  13, 0x00084001}, /* 64MB mode 3, 13x9(4)	*/ \
> 		{(64 << 20),  12, 0x00082001}, } /* 64MB mode 2, 13x9(4)	*

Why do you define so many entries in this table? One (128MB mode 3) should be 
enough for you. If get_ram_size() doesn't return 128MB in this init function 
then you need to check whether you have a problems with the timings. Use a 
debugger (or test routines) to see if some bits fail etc.

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office@denx.de
=====================================================================

[U-Boot] new board SDRAM conf

[조기성]

Hi Stefan.
I solved SDRAM problems for your help, when I use CFG_DRAM_TEST , it passed

My bdi2000's configuration  is blows
WDCR	0x10	0x00000020	;Select SDRAM0_CFG0
WDCR	0x11	0x34000000	;CFG0: 32bit, PMU disable
WDCR	0x11	0x84000000	;CFG1: enable SDRA

When I Use BID2000, accessing  SDRAM with Verify, mm command, It works fine .
 I think SDRAM0_CFG first is CFG0, and second is CFG1.

But in board/amcc/mft.c I used  marked code, It's confused me. 
Long int sdram_init()
{
	
	//mtsdram (mem_cfg0, 0x34000000); /* confused me */
	//mtsdram (mem_cfg1, 0x84000000);
	mtsdram (mem_cfg1, 0x34000000);/* it works fine */
	mtsdram (mem_cfg0, 0x84000000);
}

I have another problem. 
 cpu/ppc4XX/start.S -> trab_init function has exception error blows LOG MESSAGE. 
When I debug trap_init , use blr code it succefully returned. 
maybe you can point me to the right direction.

trap_init:
	lwz	r7, GOT(_start_of_vectors)
	lwz	r8, GOT(_end_of_vectors)

	li	r9, 0x100		/* reset vector always at 0x100 */

	cmplw	0, r7, r8
	bgelr				/* return if r7>=r8 - just in case */

	mflr	r4			/* save link register		*/
1:
	lwz	r0, 0(r7)
	stw	r0, 0(r9)
	addi	r7, r7, 4
	addi	r9, r9, 4
	cmplw	0, r7, r8
	bne	1b

 /*  blr  (in this use blr it works Steven) */

Best Regards.
Steven.

______________________________LOG MESSAGE_____________________________________________________ 
U-Boot 1.3.3 (Nov  4 2008 - 18:19:01)

CPU:   AMCC PowerPC 440EP Rev. C at 333.333 MHz (PLB=133, OPB=66, EBC=33 MHz)
       Bootstrap Option E - Boot ROM Location EBC (16 bits)
       Internal PCI arbiter enabled, PCI async ext clock used
       32 kB I-Cache 32 kB D-Cache
Board: MFT(Multi Function Tester) - AMCC PPC440EP Evaluation Board
I2C:   ready
DTT:   1 FAILED INIT
DRAM:  128 MB
[init_func_ram]K9 board_add_ram leave
[board_init_f]enter
[board_init_f:465]
[board_init_f:468]
Top of RAM usable for U-Boot at: 08000000
Reserving 593k for U-Boot at: 07f6b000
Reserving 136k for malloc() at: 07f49000
Reserving 144 Bytes for Board Info at: 07f48f70
Reserving 56 Bytes for Global Data at: 07f48f38
Stack Pointer at: 07f48f18
[board.c:639]
New Stack Pointer is: 07f48f18
[board_init_f:657]addr_sp:0x7f48f18, id:0x7f48f38, addr:0x7f6b000
[board_init_r:679]enter
Now running in RAM - U-Boot at: 07f6b000
[board_init_r:706]before watchdog_reset
[board_init_r:709]after watchdog
[board_init_r:772]
[board_init_r:790]
Bus Fault @ 0x07f6d7c0, fixup 0x00000000
Machine Check Exception.
Caused by (from msr): regs 07f48df8 Data Read PLB Error
Data Write PLB Error
Machine Check exception is imprecise
NIP: 07F6D7C0 XER: 00000000 LR: 07F6D7C0 REGS: 07f48df8 TRAP: 0200 DEAR: CE3EFACB
MSR: 00021000 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 00

GPR00: 07F6D358 07F48EE8 07F48F38 07F6B000 07F6E6F8 00000001 00000001 07F6D7C0 
GPR08: 00000600 00002098 01FCA055 00000000 07F48CF8 27000800 07FB2100 07FEB000 
GPR16: 10010000 06110000 00A94200 00638800 24009000 CB010000 00000000 FFFB3B8C 
GPR24: FFFB2A30 07F48F38 07F6B000 07F6B000 07F9EB8C 07F9DA20 07FB21B4 07F48F70 
Call backtrace: 
07F6E6F0 07F6D734 
machine check

__________________________________________________________________________________________

Include/configs/mft.h
/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
#define CONFIG_440EP		1	    /* Specifc EP support	*/
#define CONFIG_440		1	    /* ... PPC440 family	*/
#define CONFIG_4xx		1	    /* ... PPC4xx family	*/
#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
#define CONFIG_MISC_INIT_R	1	    /* Call misc_init_r		*/
#define CONFIG_SYS_CLK_FREQ	66666666    /* external freq to pll	*/

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
#define CFG_SDRAM_BASE	    0x00000000	    /* _must_ be 0		*
#define CFG_FLASH_BASE	    	0xfc000000	    /* start of FLASH		*/
#define CFG_MONITOR_BASE	TEXT_BASE	
//#define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)
#define CFG_PCI_MEMBASE	    	0xa0000000	    /* mapped pci memory	*/
#define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
#define CFG_PCI_MEMBASE2        CFG_PCI_MEMBASE1 + 0x10000000
#define CFG_PCI_MEMBASE3        CFG_PCI_MEMBASE2 + 0x10000000
#define CFG_PERIPHERAL_BASE 	0xef600000	    /* internal peripherals	*/
#define CFG_PCI_BASE	    	0xe0000000	    /* internal PCI regs	*/

#define CFG_USB_DEVICE          0x50000000
#define CFG_NVRAM_BASE_ADDR     0x80000000
#define CFG_BCSR_BASE	        (CFG_NVRAM_BASE_ADDR | 0x2000)
#define CFG_BOOT_BASE_ADDR      0xf0000000
/*-----------------------------------------------------------------------
 * Initial RAM & stack pointer (placed in internal SRAM)
 *----------------------------------------------------------------------*/
#define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
#define CFG_INIT_RAM_ADDR	0x70000000  /* Initial RAM address	*/
#define CFG_ISRAM_BASE	 	CFG_INIT_RAM_ADDR	    /* internal SRAM		*/
#define CFG_INIT_RAM_END	(4 << 10)	    /* End of used area in RAM	*/
#define CFG_GBL_DATA_SIZE	256	    /* num bytes initial data	*/

#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon*/
#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc*/


/*-----------------------------------------------------------------------
 * DDR SDRAM
 *----------------------------------------------------------------------*/
#undef CONFIG_SPD_EEPROM		/* Don't use SPD EEPROM for setup	*/
//#define CONFIG_SDRAM_BANK0	1	/* init onboard DDR SDRAM bank 0*/
//#define	CFG_SDRAM0_TR0		0x410A4012
#undef CONFIG_SDRAM_ECC		/* enable ECC support		*/

#if 1 // for sdram test 
#define CFG_DRAM_TEST
#define CFG_KBYTES_SDRAM        (128 * 1024)
#endif

[U-Boot] new board SDRAM conf

[Stefan Roese]

Hi Steven,

On Tuesday 04 November 2008, ??? wrote:
> I solved SDRAM problems for your help, when I use CFG_DRAM_TEST , it passed
>
> My bdi2000's configuration  is blows
> WDCR	0x10	0x00000020	;Select SDRAM0_CFG0
> WDCR	0x11	0x34000000	;CFG0: 32bit, PMU disable
> WDCR	0x11	0x84000000	;CFG1: enable SDRA
>
> When I Use BID2000, accessing  SDRAM with Verify, mm command, It works fine
> . I think SDRAM0_CFG first is CFG0, and second is CFG1.
>
> But in board/amcc/mft.c I used  marked code, It's confused me.
> Long int sdram_init()
> {
>
> 	//mtsdram (mem_cfg0, 0x34000000); /* confused me */
> 	//mtsdram (mem_cfg1, 0x84000000);
> 	mtsdram (mem_cfg1, 0x34000000);/* it works fine */
> 	mtsdram (mem_cfg0, 0x84000000);
> }

Not sure if I understand what you are trying to tell me? Did you find a 
problem in the common code? Or is it a problem with your BDI config script?

> I have another problem.
>  cpu/ppc4XX/start.S -> trab_init function has exception error blows LOG
> MESSAGE. When I debug trap_init , use blr code it succefully returned.
> maybe you can point me to the right direction.
>
> trap_init:
> 	lwz	r7, GOT(_start_of_vectors)
> 	lwz	r8, GOT(_end_of_vectors)
>
> 	li	r9, 0x100		/* reset vector always at 0x100 */
>
> 	cmplw	0, r7, r8
> 	bgelr				/* return if r7>=r8 - just in case */
>
> 	mflr	r4			/* save link register		*/
> 1:
> 	lwz	r0, 0(r7)
> 	stw	r0, 0(r9)
> 	addi	r7, r7, 4
> 	addi	r9, r9, 4
> 	cmplw	0, r7, r8
> 	bne	1b
>
>  /*  blr  (in this use blr it works Steven) */

So when you add this "blr" here you can boot successfully to the U-Boot 
prompt? And without it you get the exceptions printed below? That's strange. 
It works on all other known 4xx platforms without problem as far as I know.

Make sure to start "fresh" from the BDI by using "reset run".

Best regards,
Stefan

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