[U-Boot] PPC440EP UART 4port enble

[U-Boot] PPC440EP UART 4port enble

[조기성]

Hi. 
We have designed a new PPC440EP yosemite based board.
But we are using UART 4port tx,rx( 2pin UART0, 1, 2, 3)
But current It only works 2port(UART0, UART1).
I read user manual then changed  u-boot's GPIO bit flag blows.
But it's now working, How can I do that?

Thanks in advance


int board_early_init_f(void)
{
	
...
	/*UART1 */
	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
	out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000)


#if 1 //kscho, UART2, 3(0 based UART) enable
	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x20000000); 
	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000)
	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
#else
	//gpio_config(34, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1);
	//gpio_config(35, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1);
	//gpio_config(36, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1);

	printf("GPIO1_TCR 0x%lx\n", in32(GPIO1_TCR));
	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x24); /* 0010 01 */
	printf("### GPIO1_TCR 0x%lx\n", in32(GPIO1_TCR));
	//out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x820); /* 0000 0100  0001 */
	printf("GPIO1_OSRL 0x%lx\n", in32(GPIO1_OSRL));
	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0xC30); /* 0000 1100 0011 */
	printf("### GPIO1_OSRL 0x%lx\n", in32(GPIO1_OSRL));
	printf("GPIO1_TSRL 0x%lx\n", in32(GPIO1_TSRL));
	out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00000ff0); 
	printf("### GPIO1_TSRL 0x%lx\n", in32(GPIO1_TSRL));
	printf("GPIO1_ISR3L 0x%lx\n", in32(GPIO1_ISR3L));
	out32(GPIO1_ISR3L, in32(GPIO1_ISR3L) | 0x00000280); /* 0000 0001
0100 */
	printf("### GPIO1_ISR3L 0x%lx\n", in32(GPIO1_ISR3L));
#endi

...
	/*------------------------------------------------------------------
--
	 * Setup other serial configuration
	 *------------------------------------------------------------------
-*/
	mfsdr(sdr_pci0, reg);
	mtsdr(sdr_pci0, 0x80000000 | reg);	/* PCI arbiter enabled */
	mtsdr(sdr_pfc0, 0x00003e00);	/* Pin function */
	mtsdr(sdr_pfc1, 0x00048000);	/* Pin function: UART0 has 4 pins *
}


Best Regards.
Steven.

---------------------------------------------------------------------
6F Lotte IT Castle II 550-1 Gasan-dong, 
Geumcheon-gu, Seoul, 153-768, Korea
Research Engineer/R&D software Team
Tel: 82-2-890-1657(Direct)
FAX:02-890-1639

[U-Boot] PPC440EP UART 4port enble

[Stefan Roese]

On Tuesday 11 November 2008, ??? wrote:
> We have designed a new PPC440EP yosemite based board.
> But we are using UART 4port tx,rx( 2pin UART0, 1, 2, 3)
> But current It only works 2port(UART0, UART1).
> I read user manual then changed  u-boot's GPIO bit flag blows.
> But it's now working, How can I do that?

I suggest that you switch in your board port to the GPIO multiplexing 
initialization via the CONFIG_SYS_4xx_GPIO_TABLE definition. As an example 
for 440EP take a look at the pcs440ep board port. It's easier and less error 
prone to change the pin configuration in this table.

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] PPC440EP UART 4port enble

[조기성]

Stefan,
Thank you for the feedback 

I have another question. 
UART 0,1,2,3 works fine.
UART3 TX works good, but UART RX is not working. 

TX data is success, but RX is not working . 
maybe you can point me to the right direction.

I use pcs440ep.h 's CONFIG_SYS_4xx_GPIO_TABLE , 

Best Regards. 
Steven. 

/* GPIO Core 1 */ \ 
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO32 USB2D_OPMODE0 */ \ 
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO33 USB2D_OPMODE1 */ \ 
{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ 
{GPIO1_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ 
{GPIO1_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO36 UART0_8PIN_CTS_N UART3_SIN*/ \ 
{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO37 UART0_RTS_N */ \ 
{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ 
{GPIO1_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO39 UART0_RI_N UART1_SIN */ \

-----Original Message-----
From: Stefan Roese [mailto:sr at denx.de] 
Sent: Tuesday, November 11, 2008 4:24 PM
To: u-boot at lists.denx.de; k9 at tibetsystem.com
Subject: Re: [U-Boot] PPC440EP UART 4port enble

On Tuesday 11 November 2008, ??? wrote:
> We have designed a new PPC440EP yosemite based board.
> But we are using UART 4port tx,rx( 2pin UART0, 1, 2, 3)
> But current It only works 2port(UART0, UART1).
> I read user manual then changed  u-boot's GPIO bit flag blows.
> But it's now working, How can I do that?

I suggest that you switch in your board port to the GPIO multiplexing 
initialization via the CONFIG_SYS_4xx_GPIO_TABLE definition. As an example 
for 440EP take a look at the pcs440ep board port. It's easier and less error 
prone to change the pin configuration in this table.

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] PPC440EP UART 4port enble

[Stefan Roese]

Steven,

On Tuesday 11 November 2008, ??? wrote:
> Thank you for the feedback
>
> I have another question.
> UART 0,1,2,3 works fine.
> UART3 TX works good, but UART RX is not working.
>
> TX data is success, but RX is not working .
> maybe you can point me to the right direction.

No real idea, sorry. I would double-check the GPIO multiplexing configuration 
with the latest 440EP users manual. Perhaps the comments in the 
CONFIG_SYS_4xx_GPIO_TABLE are incorrect.

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================