[U-Boot] [PATCH v3] nand: Fix cache and memory inconsistent issue

[U-Boot] [PATCH v3] nand: Fix cache and memory inconsistent issue

[Dave Liu]

we load the secondary stage u-boot image from NAND to
system memory by nand_load, but we did not flush d-cache
to memory, not invalidate i-cache before we jump to RAM.
when the system is cache enable and the TLB/page attribute
of system memory is cacheable, it will cause issue.

- 83xx family is using the d-cache lock, so all of d-cache
  access is cache-inhibited. so you can't see the issue.
- 85xx family is using d-cache, i-cache enable, partial
  cache lock. you will see the issue.

The patch fix the cache issue.

Signed-off-by: Dave Liu <daveliu@freescale.com>
---
Stefan,

I'm not familiar with ppc4xx, could you workout one
patch for nand_boot.c?

Thanks,
Dave

 nand_spl/board/freescale/mpc8313erdb/Makefile |    6 +++++-
 nand_spl/nand_boot_fsl_elbc.c                 |    5 +++++
 2 files changed, 10 insertions(+), 1 deletions(-)

diff --git a/nand_spl/board/freescale/mpc8313erdb/Makefile b/nand_spl/board/freescale/mpc8313erdb/Makefile
index 3da1b1f..1a8f6ff 100644
--- a/nand_spl/board/freescale/mpc8313erdb/Makefile
+++ b/nand_spl/board/freescale/mpc8313erdb/Makefile
@@ -34,7 +34,8 @@ AFLAGS	+= -DCONFIG_NAND_SPL
 CFLAGS	+= -DCONFIG_NAND_SPL
 
 SOBJS	= start.o ticks.o
-COBJS	= nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o nand_init.o time.o
+COBJS	= nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o nand_init.o \
+	  time.o cache.o
 
 SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
@@ -79,6 +80,9 @@ $(obj)ns16550.c:
 $(obj)nand_init.c:
 	ln -sf $(SRCTREE)/cpu/mpc83xx/nand_init.c $(obj)nand_init.c
 
+$(obj)cache.c:
+	ln -sf $(SRCTREE)/lib_ppc/cache.c $(obj)cache.c
+
 $(obj)time.c:
 	ln -sf $(SRCTREE)/lib_ppc/time.c $(obj)time.c
 
diff --git a/nand_spl/nand_boot_fsl_elbc.c b/nand_spl/nand_boot_fsl_elbc.c
index 4a961ea..0d0c44e 100644
--- a/nand_spl/nand_boot_fsl_elbc.c
+++ b/nand_spl/nand_boot_fsl_elbc.c
@@ -143,6 +143,11 @@ void nand_boot(void)
 	 * Jump to U-Boot image
 	 */
 	puts("transfering control\n");
+	/*
+	 * Clean d-cache and invalidate i-cache, to
+	 * make sure that no stale data is executed.
+	 */
+	flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
 	uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
 	uboot();
 }
-- 
1.5.4

[U-Boot] [PATCH v3] nand: Fix cache and memory inconsistent issue

[Stefan Roese]

On Tuesday 02 December 2008, Dave Liu wrote:
> we load the secondary stage u-boot image from NAND to
> system memory by nand_load, but we did not flush d-cache
> to memory, not invalidate i-cache before we jump to RAM.
> when the system is cache enable and the TLB/page attribute
> of system memory is cacheable, it will cause issue.
>
> - 83xx family is using the d-cache lock, so all of d-cache
>   access is cache-inhibited. so you can't see the issue.
> - 85xx family is using d-cache, i-cache enable, partial
>   cache lock. you will see the issue.
>
> The patch fix the cache issue.
>
> Signed-off-by: Dave Liu <daveliu@freescale.com>
> ---
> Stefan,
>
> I'm not familiar with ppc4xx, could you workout one
> patch for nand_boot.c?

All 4xx platforms using nand_boot.c run with D-Cache disabled at that time. So 
it's currently not needed here.

Best regards,
Stefan

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Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH v3] nand: Fix cache and memory inconsistent issue

[Scott Wood]

On Tue, Dec 02, 2008 at 11:48:51AM +0800, Dave Liu wrote:
> we load the secondary stage u-boot image from NAND to
> system memory by nand_load, but we did not flush d-cache
> to memory, not invalidate i-cache before we jump to RAM.
> when the system is cache enable and the TLB/page attribute
> of system memory is cacheable, it will cause issue.
> 
> - 83xx family is using the d-cache lock, so all of d-cache
>   access is cache-inhibited. so you can't see the issue.
> - 85xx family is using d-cache, i-cache enable, partial
>   cache lock. you will see the issue.
> 
> The patch fix the cache issue.
> 
> Signed-off-by: Dave Liu <daveliu@freescale.com>

Applied to u-boot-nand-flash/next

-Scott