From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefan Roese Date: Tue, 2 Dec 2008 06:49:23 +0100 Subject: [U-Boot] [PATCH v3] nand: Fix cache and memory inconsistent issue In-Reply-To: <1228189731-5515-1-git-send-email-daveliu@freescale.com> References: <1228189731-5515-1-git-send-email-daveliu@freescale.com> Message-ID: <200812020649.23518.sr@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Tuesday 02 December 2008, Dave Liu wrote: > we load the secondary stage u-boot image from NAND to > system memory by nand_load, but we did not flush d-cache > to memory, not invalidate i-cache before we jump to RAM. > when the system is cache enable and the TLB/page attribute > of system memory is cacheable, it will cause issue. > > - 83xx family is using the d-cache lock, so all of d-cache > access is cache-inhibited. so you can't see the issue. > - 85xx family is using d-cache, i-cache enable, partial > cache lock. you will see the issue. > > The patch fix the cache issue. > > Signed-off-by: Dave Liu > --- > Stefan, > > I'm not familiar with ppc4xx, could you workout one > patch for nand_boot.c? All 4xx platforms using nand_boot.c run with D-Cache disabled at that time. So it's currently not needed here. Best regards, Stefan ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de =====================================================================