From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Sun, 4 Jan 2009 08:51:19 +0100
Subject: [U-Boot] [PATCH] IXP425: make cmd_go handle caches
	correctly	Part 1/1
In-Reply-To: <gi9cfv$224$1@ger.gmane.org>
References: <49384710.DwdG58IaB1mKOO9U%stefan.althoefer@web.de>
	<20081215231824.EE9F8832E8A1@gemini.denx.de>
	<gi9cfv$224$1@ger.gmane.org>
Message-ID: <20090104075119.GF6960@game.jcrosoft.org>
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> 
> diff --git a/cpu/ixp/cpu.c b/cpu/ixp/cpu.c
> index 27872fb..9035d98 100644
> --- a/cpu/ixp/cpu.c
> +++ b/cpu/ixp/cpu.c
> @@ -171,6 +171,22 @@ int icache_status (void)
>  	return (i & 0x1000);
>  }
> 
> +void icache_invalidate (void)
> +{
> +	register u32 i;
why do you need it?
> +
> +	/* FIXME: Required to check if icache is enabled before we do this? */
> +
> +	/* invalidate I-cache (i is ignored)*/
> +	i = 0;
> +	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
> +
> +	/* cpwait */
> +	asm ("mrc  p15,0,%0,c2,c0,0;\
> +	    mov  %0,%0;\
> +	    sub  pc,pc,#4" : : "r" (i) );
> +}
> +
>  /* we will never enable dcache, because we have to setup MMU first */
>  void dcache_enable (void)
>  {
> @@ -187,6 +203,11 @@ int dcache_status (void)
>  	return 0;					/* always off */
>  }
> 
> +void dcache_flush (void)
> +{
> +	return;
> +}
> +
>  /* FIXME */
>  /*
>  void pci_init(void)
> @@ -195,6 +216,17 @@ void pci_init(void)
>  }
>  */
> 
general arm function need to be in the lib_arm
> +/* With IXP (and ARM generally) we need to handle caches to avoid
> +   stale data. */
> +unsigned long do_go_exec (ulong (*entry)(int, char *[]), int argc, char *argv[])
> +{
> +	dcache_flush ();
> +	icache_invalidate ();
> +
> +	return entry (argc, argv);
> +}
> +
Best Regards,
J.