[U-Boot] 460GT PCIe configuration

[Stefan Roese <sr@denx.de>]

On Tuesday 13 January 2009, vb wrote:
> I am trying to troubleshoot a weird PCIe problem on a PPC460GT based
> target, and it is getting curiouser and curiouser.
>
> There is a tlb overlap I mentioned in an earlier email; on top of that
> there are some things happening in cpu/ppc4xx/4xx_pcie.c which I also
> find hard to understand:
>
> there is a static function pcie_get_base(), which returns a value as in
>
> address = pcie_get_base(hose, devfn)
>
> there are two instances of this, in both cases `address' is never used.

Good catch. pcie_get_base() can be removed. This is probably a remnant from an 
older driver version.

> The CONFIG_SYS_PCIE0_XCFGBASE constant (and its counterparts for other
> PCIe ports) is defined and used in the code, and gets a TLB entry
> assigned, but I can't find a place where it is programmed into the CPU
> - how does it know where this section is?!

Again you seem to be correct here. I can't find a place where this area is 
programmed. I don't have the time to dig into this right now, so it would be 
great if you could work on this a little deeper. I suggest to look at the 
Linux 4xx PCI driver (arch/powerpc/sysdev/ppc4xx_pci.c) as reference.

> I have several different targets with different PCIe components, but
> all using the same base CPU subsystem design, and on some of them PCIe
> components misbehave, namely, PCIe memory read transactions fail with
> a machine check after a timeout, even though the PCIe side of things
> is fine (when looking with a protocol analyzer).

Is this all 460EX? Or some other 4xx? What are the PCIe endpoints you are 
using? Do you see the same problems on Canyonlands as well?

Best regards,
Stefan

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