[U-Boot] [PATCH] Add bank configuration to FSL spd_sdram.c

[Jerry Van Baren <gvb.uboot@gmail.com>]

The routine assumed 4 bank SDRAMs, enhance to configure for 4 or 8
bank SDRAMs.

Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
---

I haven't made much headway on adapting the cpu/mpc8xxxx/ddr routines
to the 83xx (8360).  It has some 85xx (86xx) assumptions in that needs
to be pulled out.

Meanwhile, the cpu/mpc83xx/spd_sdram.c routine /almost/ worked for me.
It turns out my DIMM stick has 8 banks which was being ignored (hard-coded
for 4 banks).  The enhancement below fixed that for me.

It would be Really Good to get this verified and in the pending release.

Best regards,
gvb

 cpu/mpc83xx/spd_sdram.c |    8 +++++---
 1 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index df116aa..df1ccae 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -220,7 +220,8 @@ long int spd_sdram()
 	ddr->cs_config[0] = ( 1 << 31
 			    | (odt_rd_cfg << 20)
 			    | (odt_wr_cfg << 16)
-			    | (spd.nrow_addr - 12) << 8
+			    | ((spd.nbanks == 8 ? 1 : 0) << 14)
+			    | ((spd.nrow_addr - 12) << 8)
 			    | (spd.ncol_addr - 8) );
 	debug("\n");
 	debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
@@ -232,8 +233,9 @@ long int spd_sdram()
 		ddr->cs_config[1] = ( 1<<31
 				    | (odt_rd_cfg << 20)
 				    | (odt_wr_cfg << 16)
-				    | (spd.nrow_addr-12) << 8
-				    | (spd.ncol_addr-8) );
+				    | ((spd.nbanks == 8 ? 1 : 0) << 14)
+				    | ((spd.nrow_addr - 12) << 8)
+				    | (spd.ncol_addr - 8) );
 		debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
 		debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
 	}
-- 
1.5.6.5