From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Fri, 17 Apr 2009 07:33:15 +0200
Subject: [U-Boot] [PATCH 1/3] OMAP3:NAND: Change the NAND
	timing	assignment
In-Reply-To: <1239655683-16490-2-git-send-email-nm@ti.com>
References: <1239655683-16490-1-git-send-email-nm@ti.com>
	<1239655683-16490-2-git-send-email-nm@ti.com>
Message-ID: <20090417053315.GF31923@game.jcrosoft.org>
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To: u-boot@lists.denx.de

On 15:48 Mon 13 Apr     , Nishanth Menon wrote:
> NAND timing is defaulted to Micron NAND. To support
> varied boards, this is not scalable.
> This patch introduces compile time option to select
> the timing to select at the same time allows
> platforms to build with custom timing params
> 
> Signed-off-by: Nishanth Menon <nm@ti.com>
> ---
>  cpu/arm_cortexa8/omap3/mem.c     |   12 ++++++------
>  include/asm-arm/arch-omap3/mem.h |   38 +++++++++++++++++++++++---------------
>  include/configs/omap3_beagle.h   |    1 +
>  include/configs/omap3_overo.h    |    1 +
>  include/configs/omap3_pandora.h  |    1 +
>  include/configs/omap3_zoom1.h    |    1 +
>  6 files changed, 33 insertions(+), 21 deletions(-)
> 
> diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c
> index 3cc22c4..14cd87d 100644
> --- a/cpu/arm_cortexa8/omap3/mem.c
> +++ b/cpu/arm_cortexa8/omap3/mem.c
> @@ -43,12 +43,12 @@ volatile unsigned int boot_flash_env_addr;
>  
>  #if defined(CONFIG_CMD_NAND)
>  static u32 gpmc_m_nand[GPMC_MAX_REG] = {
> -	M_NAND_GPMC_CONFIG1,
> -	M_NAND_GPMC_CONFIG2,
> -	M_NAND_GPMC_CONFIG3,
> -	M_NAND_GPMC_CONFIG4,
> -	M_NAND_GPMC_CONFIG5,
> -	M_NAND_GPMC_CONFIG6, 0
> +	NAND_GPMC_CONFIG1,
> +	NAND_GPMC_CONFIG2,
> +	NAND_GPMC_CONFIG3,
> +	NAND_GPMC_CONFIG4,
> +	NAND_GPMC_CONFIG5,
> +	NAND_GPMC_CONFIG6, 0
>  };
>  
>  gpmc_csx_t *nand_cs_base;
> diff --git a/include/asm-arm/arch-omap3/mem.h b/include/asm-arm/arch-omap3/mem.h
> index 6f0f90b..622578e 100644
> --- a/include/asm-arm/arch-omap3/mem.h
> +++ b/include/asm-arm/arch-omap3/mem.h
> @@ -137,21 +137,29 @@ typedef enum {
>  #define GPMC_SIZE_32M	0xE
>  #define GPMC_SIZE_16M	0xF
>  
> -#define SMNAND_GPMC_CONFIG1	0x00000800
> -#define SMNAND_GPMC_CONFIG2	0x00141400
> -#define SMNAND_GPMC_CONFIG3	0x00141400
> -#define SMNAND_GPMC_CONFIG4	0x0F010F01
> -#define SMNAND_GPMC_CONFIG5	0x010C1414
> -#define SMNAND_GPMC_CONFIG6	0x1F0F0A80
> -#define SMNAND_GPMC_CONFIG7	0x00000C44
> -
> -#define M_NAND_GPMC_CONFIG1	0x00001800
> -#define M_NAND_GPMC_CONFIG2	0x00141400
> -#define M_NAND_GPMC_CONFIG3	0x00141400
> -#define M_NAND_GPMC_CONFIG4	0x0F010F01
> -#define M_NAND_GPMC_CONFIG5	0x010C1414
> -#define M_NAND_GPMC_CONFIG6	0x1f0f0A80
> -#define M_NAND_GPMC_CONFIG7	0x00000C44
> +/*
> + * Standard OMAP3 NAND device definitions
> + * Define SMNAND_GPMC or M_NAND_GPMC to use the defaults
> + * if your board has a specific timing (such as optimized timing),
> + * define NAND_GPMC_CONFIG1 to 7
> + */
> +#ifdef SMNAND_GPMC
> +#define NAND_GPMC_CONFIG1	0x00000800
> +#define NAND_GPMC_CONFIG2	0x00141400
> +#define NAND_GPMC_CONFIG3	0x00141400
> +#define NAND_GPMC_CONFIG4	0x0F010F01
> +#define NAND_GPMC_CONFIG5	0x010C1414
> +#define NAND_GPMC_CONFIG6	0x1F0F0A80
> +#define NAND_GPMC_CONFIG7	0x00000C44
is it possible to use macro insteas of hardcode value?

Best Regards,
J.