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From: Mike Frysinger <vapier@gentoo.org>
To: u-boot@lists.denx.de
Subject: [U-Boot] MII register display
Date: Wed, 6 May 2009 22:20:28 -0400	[thread overview]
Message-ID: <200905062220.28991.vapier@gentoo.org> (raw)
In-Reply-To: <9e4733910905061906w7a85b706saddc0769ee628860@mail.gmail.com>

On Wednesday 06 May 2009 22:06:46 Jon Smirl wrote:
> On Wed, May 6, 2009 at 10:03 PM, Mike Frysinger <vapier@gentoo.org> wrote:
> > On Wednesday 06 May 2009 21:53:21 Jon Smirl wrote:
> >> On Wed, May 6, 2009 at 2:57 PM, Jon Smirl <jonsmirl@gmail.com> wrote:
> >> > Why is "speed selection = 10 Mbps" when both sides support 100Mb?
> >> > Is uboot decoding this register correctly?
> >> >
> >> > uboot> mii dump 0 0
> >> > 0.     (1000)                 -- PHY control register --
> >> >  (8000:0000) 0.15    =     0    reset
> >> >  (4000:0000) 0.14    =     0    loopback
> >> >  (2040:0000) 0. 6,13 =   b00    speed selection = 10 Mbps
> >>
> >> This b00 here is confusing. b is a valid hex character, I thought this
> >> was reporting the register value as 0xb00.
> >> Instead it appears to be trying to indicate that the two bits are
> >> binary?
> >
> > looks that way.  it's showing bit6 and bit13.
>
> It's in the source that way. It just confused me when trying to figure
> out what is wrong with the new PHY we're having hardware trouble with.

enable debugging in the PHY driver then ... sometimes it outputs something 
that is only obvious when you see explicit statements as to what it's doing
-mike
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  reply	other threads:[~2009-05-07  2:20 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-05-06 18:57 [U-Boot] MII register display Jon Smirl
2009-05-07  1:53 ` Jon Smirl
2009-05-07  2:03   ` Mike Frysinger
2009-05-07  2:06     ` Jon Smirl
2009-05-07  2:20       ` Mike Frysinger [this message]
2009-05-07 11:46   ` Jerry Van Baren

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