[U-Boot] [PATCH] ppc4xx: Fix FDT EBC mappings on Canyonlands

[U-Boot] [PATCH] ppc4xx: Fix FDT EBC mappings on Canyonlands

[Felix Radensky]

This patch fixes 2 problems with FDT EBC mappings on Canyonlands.
First, NAND EBC mapping was missing, making Linux NAND driver
unusable on this board. Second, NOR remapping code assumed that
NOR is always on CS0, however when booting from NAND NOR is on CS3.
---
 board/amcc/canyonlands/canyonlands.c |   38 ++++++++++++++++++++++++++-------
 include/configs/canyonlands.h        |    2 +
 2 files changed, 32 insertions(+), 8 deletions(-)

diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index 2b74689..78c32b0 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -577,20 +577,42 @@ int misc_init_r(void)
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 void ft_board_setup(void *blob, bd_t *bd)
 {
-	u32 val[4];
 	int rc;
+	int i;
+	u32 bxcr;
+	u32 ranges[EBC_NUM_BANKS * 4];
+	u32 *p = ranges;
+	char *ebc_path = "/plb/opb/ebc";
 
 	ft_cpu_setup(blob, bd);
 
+	/*
+	 * Read 4xx EBC bus bridge registers to get mappings of the
+	 * peripheral banks into the OPB/PLB address space
+	 */
+	for (i = 0; i < EBC_NUM_BANKS; i++) {
+		mtdcr(ebccfga, EBC_BXCR(i));
+		bxcr = mfdcr(ebccfgd);
+
+		if ((bxcr & EBC_BXCR_BU_MASK) != EBC_BXCR_BU_NONE) {
+			*p++ = i;
+			*p++ = 0;
+			*p++ = bxcr & EBC_BXCR_BAS_MASK;
+			*p++ = EBC_BXCR_BANK_SIZE(bxcr);
+		}
+	}
+
 	/* Fixup NOR mapping */
-	val[0] = 0;				/* chip select number */
-	val[1] = 0;				/* always 0 */
-	val[2] = CONFIG_SYS_FLASH_BASE_PHYS_L;		/* we fixed up this address */
-	val[3] = gd->bd->bi_flashsize;
-	rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
-				  val, sizeof(val), 1);
+	i = CONFIG_SYS_NOR_CS * 4;	
+	ranges[i++] = CONFIG_SYS_NOR_CS;	/* chip select number */
+	ranges[i++] = 0;			/* always 0 */
+	ranges[i++] = CONFIG_SYS_FLASH_BASE_PHYS_L;	/* we fixed up this address */
+	ranges[i++] = gd->bd->bi_flashsize;
+
+	rc = fdt_find_and_setprop(blob, ebc_path, "ranges", ranges,
+				  (p - ranges) * sizeof(u32), 1);
 	if (rc) {
-		printf("Unable to update property NOR mapping, err=%s\n",
+		printf("Unable to update property EBC mapping, err=%s\n",
 		       fdt_strerror(rc));
 	}
 
diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index d814012..48c5198 100644
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -132,9 +132,11 @@
  */
 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define	CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
+#define CONFIG_SYS_NOR_CS		0	/* NOR chip connected to CSx */
 #define CONFIG_SYS_NAND_CS		3	/* NAND chip connected to CSx */
 #else
 #define	CONFIG_ENV_IS_IN_NAND	1	/* use NAND for environment vars  */
+#define CONFIG_SYS_NOR_CS		3	/* NOR chip connected to CSx */
 #define CONFIG_SYS_NAND_CS		0	/* NAND chip connected to CSx */
 #define CONFIG_ENV_IS_EMBEDDED	1	/* use embedded environment */
 #endif
-- 
1.5.4.3

[U-Boot] [PATCH] ppc4xx: Fix FDT EBC mappings on Canyonlands

[Stefan Roese]

Hi Felix,

On Monday 22 June 2009 13:08:17 Felix Radensky wrote:
> This patch fixes 2 problems with FDT EBC mappings on Canyonlands.
> First, NAND EBC mapping was missing, making Linux NAND driver
> unusable on this board. Second, NOR remapping code assumed that
> NOR is always on CS0, however when booting from NAND NOR is on CS3.
> ---
>  board/amcc/canyonlands/canyonlands.c |   38
> ++++++++++++++++++++++++++------- include/configs/canyonlands.h        |   
> 2 +
>  2 files changed, 32 insertions(+), 8 deletions(-)
>
> diff --git a/board/amcc/canyonlands/canyonlands.c
> b/board/amcc/canyonlands/canyonlands.c index 2b74689..78c32b0 100644
> --- a/board/amcc/canyonlands/canyonlands.c
> +++ b/board/amcc/canyonlands/canyonlands.c
> @@ -577,20 +577,42 @@ int misc_init_r(void)
>  #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
>  void ft_board_setup(void *blob, bd_t *bd)
>  {
> -	u32 val[4];
>  	int rc;
> +	int i;
> +	u32 bxcr;
> +	u32 ranges[EBC_NUM_BANKS * 4];
> +	u32 *p = ranges;
> +	char *ebc_path = "/plb/opb/ebc";
>
>  	ft_cpu_setup(blob, bd);
>
> +	/*
> +	 * Read 4xx EBC bus bridge registers to get mappings of the
> +	 * peripheral banks into the OPB/PLB address space
> +	 */
> +	for (i = 0; i < EBC_NUM_BANKS; i++) {
> +		mtdcr(ebccfga, EBC_BXCR(i));
> +		bxcr = mfdcr(ebccfgd);
> +
> +		if ((bxcr & EBC_BXCR_BU_MASK) != EBC_BXCR_BU_NONE) {
> +			*p++ = i;
> +			*p++ = 0;
> +			*p++ = bxcr & EBC_BXCR_BAS_MASK;
> +			*p++ = EBC_BXCR_BANK_SIZE(bxcr);
> +		}
> +	}

This is a copy from cpu/ppc4xx/fdt.c. I suggest you just call 
__ft_board_setup() and just additionally fixup the canyonlands specifics to 
not duplicate this code.

Thanks.

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH] ppc4xx: Fix FDT EBC mappings on Canyonlands

[Felix Radensky]

This patch fixes 2 problems with FDT EBC mappings on Canyonlands.
First, NAND EBC mapping was missing, making Linux NAND driver
unusable on this board. Second, NOR remapping code assumed that
NOR is always on CS0, however when booting from NAND NOR is on CS3.
---
 board/amcc/canyonlands/canyonlands.c |    6 ++++--
 include/configs/canyonlands.h        |    2 ++
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index 2b74689..cfc1023 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -575,15 +575,17 @@ int misc_init_r(void)
 #endif	/* !defined(CONFIG_ARCHES) */
 
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+extern void __ft_board_setup(void *blob, bd_t *bd);
+
 void ft_board_setup(void *blob, bd_t *bd)
 {
 	u32 val[4];
 	int rc;
 
-	ft_cpu_setup(blob, bd);
+	__ft_board_setup(blob, bd);
 
 	/* Fixup NOR mapping */
-	val[0] = 0;				/* chip select number */
+	val[0] = CONFIG_SYS_NOR_CS;		/* chip select number */
 	val[1] = 0;				/* always 0 */
 	val[2] = CONFIG_SYS_FLASH_BASE_PHYS_L;		/* we fixed up this address */
 	val[3] = gd->bd->bi_flashsize;
diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index d814012..48c5198 100644
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -132,9 +132,11 @@
  */
 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define	CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
+#define CONFIG_SYS_NOR_CS		0	/* NOR chip connected to CSx */
 #define CONFIG_SYS_NAND_CS		3	/* NAND chip connected to CSx */
 #else
 #define	CONFIG_ENV_IS_IN_NAND	1	/* use NAND for environment vars  */
+#define CONFIG_SYS_NOR_CS		3	/* NOR chip connected to CSx */
 #define CONFIG_SYS_NAND_CS		0	/* NAND chip connected to CSx */
 #define CONFIG_ENV_IS_EMBEDDED	1	/* use embedded environment */
 #endif
-- 
1.5.4.3

[U-Boot] [PATCH] ppc4xx: Fix FDT EBC mappings on Canyonlands

[Stefan Roese]

On Monday 22 June 2009 14:30:42 Felix Radensky wrote:
> This patch fixes 2 problems with FDT EBC mappings on Canyonlands.
> First, NAND EBC mapping was missing, making Linux NAND driver
> unusable on this board. Second, NOR remapping code assumed that
> NOR is always on CS0, however when booting from NAND NOR is on CS3.
> ---

You forgot you signed-off-by line here. I added it manually and pushed it into 
the u-boot-ppc4xx/master repo.

Thanks.

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================