[U-Boot] [PATCH 2/2 v5] KB9202: Add NAND support

[Matthias Kaehlcke <matthias@kaehlcke.net>]

Add NAND support for the KwikByte KB9202

Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>

---

El Tue, Jun 23, 2009 at 04:19:40PM -0500 Scott Wood ha dit:

> I get conflicts in kb9202.h.  Is this against an arch tree, or does it
> need to be respun?

The previous patches were against v2009-03, as i had problems
building the current git head for the kb9202 when i started working on
the patch. Did you apply the first patch of this series when you got
the conflict? This patch is based on the current HEAD.

Changes regarding v4:
 * put KB9202 entry in the Makefile at the correct position
 (alphabetical order)
 * removed superfluous clear of NAND_BUSWIDTH_16 flag
 * fixed line length/broken indentation

 drivers/mtd/nand/Makefile                    |    1 +
 drivers/mtd/nand/kb9202_nand.c               |  150 ++++++++++++++++++++++++++
 include/asm-arm/arch-at91rm9200/AT91RM9200.h |    2 +
 include/configs/kb9202.h                     |   11 ++-
 4 files changed, 163 insertions(+), 1 deletions(-)
 create mode 100644 drivers/mtd/nand/kb9202_nand.c

diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 71dd5b9..d2bd558 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -40,6 +40,7 @@ COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
 COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
 COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
 COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
+COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o
 COBJS-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
 COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o
 COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.c
diff --git a/drivers/mtd/nand/kb9202_nand.c b/drivers/mtd/nand/kb9202_nand.c
new file mode 100644
index 0000000..b8f46fa
--- /dev/null
+++ b/drivers/mtd/nand/kb9202_nand.c
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2006
+ * KwikByte <kb9200_dev@kwikbyte.com>
+ *
+ * (C) Copyright 2009
+ * Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/AT91RM9200.h>
+#include <asm/arch/hardware.h>
+
+#include <nand.h>
+
+/*
+ *      hardware specific access to control-lines
+ */
+
+#define MASK_ALE        (1 << 22)       /* our ALE is A22 */
+#define MASK_CLE        (1 << 21)       /* our CLE is A21 */
+
+#define KB9202_NAND_NCE (1 << 28) /* EN* on D28 */
+#define KB9202_NAND_BUSY (1 << 29) /* RB* on D29 */
+
+#define KB9202_SMC2_NWS (1 << 2)
+#define KB9202_SMC2_TDF (1 << 8)
+#define KB9202_SMC2_RWSETUP (1 << 24)
+#define KB9202_SMC2_RWHOLD (1 << 29)
+
+/*
+ *	Board-specific function to access device control signals
+ */
+static void kb9202_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+	struct nand_chip *this = mtd->priv;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+
+		/* clear ALE and CLE bits */
+		IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+
+		if (ctrl & NAND_CLE)
+			IO_ADDR_W |= MASK_CLE;
+
+		if (ctrl & NAND_ALE)
+			IO_ADDR_W |= MASK_ALE;
+
+		this->IO_ADDR_W = (void *) IO_ADDR_W;
+
+		if (ctrl & NAND_NCE)
+			writel(KB9202_NAND_NCE, AT91C_PIOC_CODR);
+		else
+			writel(KB9202_NAND_NCE, AT91C_PIOC_SODR);
+	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
+}
+
+
+/*
+ * Board-specific function to access the device ready signal.
+ */
+static int kb9202_nand_ready(struct mtd_info *mtd)
+{
+	return readl(AT91C_PIOC_PDSR) & KB9202_NAND_BUSY;
+}
+
+
+/*
+ * Board-specific NAND init.  Copied from include/linux/mtd/nand.h for reference.
+ *
+ * struct nand_chip - NAND Private Flash Chip Data
+ * @IO_ADDR_R:		[BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
+ * @IO_ADDR_W:		[BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
+ * @hwcontrol:		[BOARDSPECIFIC] hardwarespecific function for accesing control-lines
+ * @dev_ready:		[BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
+ *			If set to NULL no access to ready/busy is available and the ready/busy information
+ *			is read from the chip status register
+ * @enable_hwecc:	[BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only
+ *			be provided if a hardware ECC is available
+ * @eccmode:		[BOARDSPECIFIC] mode of ecc, see defines
+ * @chip_delay:		[BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
+ * @options:		[BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
+ *			special functionality. See the defines for further explanation
+*/
+/*
+ * This routine initializes controller and GPIOs.
+ */
+int board_nand_init(struct nand_chip *nand)
+{
+	unsigned int value;
+
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->cmd_ctrl = kb9202_nand_hwcontrol;
+	nand->dev_ready = kb9202_nand_ready;
+
+	/* in case running outside of bootloader */
+	writel(1 << AT91C_ID_PIOC, AT91C_PMC_PCER);
+
+	/* setup nand flash access (allow ample margin) */
+	/* 4 wait states, 1 setup, 1 hold, 1 float for 8-bit device */
+	writel(AT91C_SMC2_WSEN | KB9202_SMC2_NWS | KB9202_SMC2_TDF |
+		AT91C_SMC2_DBW_8 | KB9202_SMC2_RWSETUP | KB9202_SMC2_RWHOLD,
+		AT91C_SMC_CSR3);
+
+	/* enable internal NAND controller */
+	value = readl(AT91C_EBI_CSA);
+	value |= AT91C_EBI_CS3A_SMC_SmartMedia;
+	writel(value, AT91C_EBI_CSA);
+
+	/* enable SMOE/SMWE */
+	writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_ASR);
+	writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_PDR);
+	writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_OER);
+
+	/* set NCE to high */
+	writel(KB9202_NAND_NCE, AT91C_PIOC_SODR);
+
+	/* disable output on pin connected to the busy line of the NAND */
+	writel(KB9202_NAND_BUSY, AT91C_PIOC_ODR);
+
+	/* enable the PIO to control NCE and BUSY */
+	writel(KB9202_NAND_NCE | KB9202_NAND_BUSY, AT91C_PIOC_PER);
+
+	/* enable output for NCE */
+	writel(KB9202_NAND_NCE, AT91C_PIOC_OER);
+
+	return (0);
+}
diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h
index 00bae1c..aaab2c2 100644
--- a/include/asm-arm/arch-at91rm9200/AT91RM9200.h
+++ b/include/asm-arm/arch-at91rm9200/AT91RM9200.h
@@ -737,6 +737,7 @@ typedef struct _AT91S_PDC
 #define AT91C_SMC2_ACSS_STANDARD	((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted@the end. */
 #define AT91C_SMC2_DBW_8	((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */
 #define AT91C_SMC2_WSEN		((unsigned int) 0x1 <<  7) /* (SMC2) Wait State Enable */
+#define AT91C_PIOC_OER		((AT91_REG *)	0xFFFFF810) /* (PIOC) PIO Output Enable Register */
 #define AT91C_PIOC_ASR		((AT91_REG *)	0xFFFFF870) /* (PIOC) Select A Register */
 #define AT91C_PIOC_SODR		((AT91_REG *)	0xFFFFF830) /* (PIOC) Set Output Data Register */
 #define AT91C_PIOC_CODR		((AT91_REG *)	0xFFFFF834) /* (PIOC) Clear Output Data Register */
@@ -780,6 +781,7 @@ typedef struct _AT91S_PDC
 #define AT91C_PIOB_PER		((AT91_REG *)	0xFFFFF600) /* (PIOB) PIO Enable Register */
 #define AT91C_PIOB_ODR		((AT91_REG *)	0xFFFFF614) /* (PIOB) Output Disable Registerr */
 #define AT91C_PIOB_PDSR		((AT91_REG *)	0xFFFFF63C) /* (PIOB) Pin Data Status Register */
+#define AT91C_SMC_CSR3		((AT91_REG *)	0xFFFFFF7C) /* (SMC) Chip Select Register 3 */
 
 #else
 /* flash */
diff --git a/include/configs/kb9202.h b/include/configs/kb9202.h
index 8651e53..c51845e 100644
--- a/include/configs/kb9202.h
+++ b/include/configs/kb9202.h
@@ -62,6 +62,12 @@
 #ifdef CONFIG_KB9202B
 #define	CONFIG_BOOTARGS	"console=ttyS0,115200 noinitrd root=/dev/mtdblock0 rootfstype=jffs2 mem=64M"
 #define	CONFIG_BOOTCOMMAND	"bootm 0x10000000"
+#define CONFIG_NAND_KB9202
+#define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CONFIG_JFFS2_NAND
+#define CONFIG_JFFS2_CMDLINE
 #endif
 
 
@@ -71,7 +77,7 @@
 /*
  * Size of malloc() pool
  */
-#define CONFIG_SYS_MALLOC_LEN	(128*1024)
+#define CONFIG_SYS_MALLOC_LEN (1024*1024)
 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 #define CONFIG_BAUDRATE 115200
@@ -112,6 +118,9 @@
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
+#ifdef CONFIG_KB9202B
+#define CONFIG_CMD_NAND
+#endif
 #define CONFIG_CMD_JFFS2
 
 #undef CONFIG_CMD_BDI

-- 
Matthias Kaehlcke
Embedded Linux Engineer
Barcelona


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