[U-Boot] [PATCH] ppc440SPe: PCIe PLL lock error

[U-Boot] [PATCH] ppc440SPe: PCIe PLL lock error

[Rupjyoti Sarmah]

u-boot reports a PCIE PLL lock error at boot time on Yucca
board, and left PCIe nonfunctional. This is fixed by making u-boot
function ppc4xx_init_pcie() to wait 300 uS after negating reset before
the first check of PLL lock.

This fix touches only one file 4xx_pcie.c

Signed off by  Rupjyoti Sarmah < rsarmah@amcc.com > from Applied Micro

------------------------------------------------------------------------
---------------------
diff --git a/a/u-boot-2009.06/cpu/ppc4xx/4xx_pcie.c
b/b/u-boot-2009.06/cpu/ppc4xx/4xx_pcie.c
old mode 100644
new mode 100755
index 07fbb0e..ce95abc
--- a/a/u-boot-2009.06/cpu/ppc4xx/4xx_pcie.c
+++ b/b/u-boot-2009.06/cpu/ppc4xx/4xx_pcie.c
@@ -369,33 +369,40 @@ static int check_error(void)
  */
 int ppc4xx_init_pcie(void)
 {
-	int time_out = 20;
+	int time_out = 20;	/* PCIe PLL lock retry count */
 
 	/* Set PLL clock receiver to LVPECL */
 	SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
 
 	if (check_error())
+	{
+		printf("ERROR: ppc4xx_init_pcie(): PCIe setting
reference clock receiver failed: PESDR0_PLLLCT1 = (0x%08x)\n",
+		       SDR_READ(PESDR0_PLLLCT1));
 		return -1;
+	}
 
+	/* Did resistance calibration work? */
 	if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
 	{
-		printf("PCIE: PESDR_PLLCT2 resistance calibration failed
(0x%08x)\n",
+		printf("ERROR: ppc4xx_init_pcie(): PCIe resistance
calibration failed (bit 15=0): PESDR0_PLLLCT2 = (0x%08x)\n",
 		       SDR_READ(PESDR0_PLLLCT2));
 		return -1;
 	}
-	/* De-assert reset of PCIe PLL, wait for lock */
+
+	/* Take PCIe PLL out of reset, wait for lock */
 	SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 <<
24));
-	udelay(3);
+	udelay(300);	/* 300 uS is maximum time lock should take, per
440SPe user's manual */
 
 	while (time_out) {
-		if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
+		if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
/* Read PLL lock status register PLLLCTS in user's manual */
 			time_out--;
-			udelay(1);
+			udelay(20);	/* Wait 20 uS more if needed */
 		} else
 			break;
 	}
 	if (!time_out) {
-		printf("PCIE: VCO output not locked\n");
+		printf("ERROR: ppc4xx_init_pcie(): PCIe - PCIe PLL VCO
output not locked to reference clock (bit 3=0): PESDR0_PLLLCTS =
(0x%08x)\n",
+			SDR_READ(PESDR0_PLLLCT3));
 		return -1;
 	}
 	return 0;
@@ -1169,3 +1176,4 @@ int ppc4xx_setup_pcie_endpoint(struct
pci_controller *hose, int port)
 	return 0;
 }
 #endif /* CONFIG_440SPE && CONFIG_PCI */
+

[U-Boot] [PATCH] ppc440SPe: PCIe PLL lock error

[Stefan Roese]

Hi Rup,

On Friday 24 July 2009 08:01:14 Rupjyoti Sarmah wrote:
> u-boot reports a PCIE PLL lock error at boot time on Yucca
> board, and left PCIe nonfunctional. This is fixed by making u-boot
> function ppc4xx_init_pcie() to wait 300 uS after negating reset before
> the first check of PLL lock.
>
> This fix touches only one file 4xx_pcie.c

Please drop this last line. You don't have to mentions this.

> Signed off by  Rupjyoti Sarmah < rsarmah@amcc.com > from Applied Micro
>
> ------------------------------------------------------------------------
> ---------------------
> diff --git a/a/u-boot-2009.06/cpu/ppc4xx/4xx_pcie.c
> b/b/u-boot-2009.06/cpu/ppc4xx/4xx_pcie.c
> old mode 100644
> new mode 100755

No. Please don't change file modes.

> index 07fbb0e..ce95abc
> --- a/a/u-boot-2009.06/cpu/ppc4xx/4xx_pcie.c
> +++ b/b/u-boot-2009.06/cpu/ppc4xx/4xx_pcie.c
> @@ -369,33 +369,40 @@ static int check_error(void)
>   */
>  int ppc4xx_init_pcie(void)
>  {
> -	int time_out = 20;
> +	int time_out = 20;	/* PCIe PLL lock retry count */
>
>  	/* Set PLL clock receiver to LVPECL */
>  	SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
>
>  	if (check_error())
> +	{

Incorrect coding-style. This should be:

  	if (check_error()) {

> +		printf("ERROR: ppc4xx_init_pcie(): PCIe setting
> reference clock receiver failed: PESDR0_PLLLCT1 = (0x%08x)\n",

Your patch is line wrapped. So it can't be applied. Also I suggest to use the 
__func__ macro and don't hardcode the function name:

		printf("ERROR: %s(): PCIe setting ...", __func__, ...);

> +		       SDR_READ(PESDR0_PLLLCT1));
>  		return -1;
> +	}
>
> +	/* Did resistance calibration work? */
>  	if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
>  	{
> -		printf("PCIE: PESDR_PLLCT2 resistance calibration failed
> (0x%08x)\n",
> +		printf("ERROR: ppc4xx_init_pcie(): PCIe resistance
> calibration failed (bit 15=0): PESDR0_PLLLCT2 = (0x%08x)\n",
>  		       SDR_READ(PESDR0_PLLLCT2));
>  		return -1;
>  	}
> -	/* De-assert reset of PCIe PLL, wait for lock */
> +
> +	/* Take PCIe PLL out of reset, wait for lock */
>  	SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 <<
> 24));
> -	udelay(3);
> +	udelay(300);	/* 300 uS is maximum time lock should take, per
> 440SPe user's manual */
>
>  	while (time_out) {
> -		if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
> +		if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
> /* Read PLL lock status register PLLLCTS in user's manual */
>  			time_out--;
> -			udelay(1);
> +			udelay(20);	/* Wait 20 uS more if needed */
>  		} else
>  			break;
>  	}
>  	if (!time_out) {
> -		printf("PCIE: VCO output not locked\n");
> +		printf("ERROR: ppc4xx_init_pcie(): PCIe - PCIe PLL VCO
> output not locked to reference clock (bit 3=0): PESDR0_PLLLCTS =
> (0x%08x)\n",
> +			SDR_READ(PESDR0_PLLLCT3));
>  		return -1;
>  	}
>  	return 0;
> @@ -1169,3 +1176,4 @@ int ppc4xx_setup_pcie_endpoint(struct
> pci_controller *hose, int port)
>  	return 0;
>  }
>  #endif /* CONFIG_440SPE && CONFIG_PCI */
> +

Please don't add empty lines.

Please fix and resubmit. Thanks.

Best regards,
Stefan

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