* [U-Boot] [PATCH 3/7] mpc85xx: Add eLBC NAND support for MPC8569E-MDS boards
@ 2009-08-19 18:37 Anton Vorontsov
2009-09-16 4:17 ` Kumar Gala
0 siblings, 1 reply; 5+ messages in thread
From: Anton Vorontsov @ 2009-08-19 18:37 UTC (permalink / raw)
To: u-boot
Simply add some defines, and adjust TLBe setup to include some
space for eLBC NAND.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
board/freescale/mpc8569mds/tlb.c | 30 +++++++++++-------------------
include/configs/MPC8569MDS.h | 23 +++++++++++++++++++++++
2 files changed, 34 insertions(+), 19 deletions(-)
diff --git a/board/freescale/mpc8569mds/tlb.c b/board/freescale/mpc8569mds/tlb.c
index d3b251e..3b8ee05 100644
--- a/board/freescale/mpc8569mds/tlb.c
+++ b/board/freescale/mpc8569mds/tlb.c
@@ -46,22 +46,24 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 1 Initializations */
/*
- * TLBe 0: 16M Non-cacheable, guarded
- * 0xff000000 16M FLASH (upper half)
+ * TLBe 0: 64M Non-cacheable, guarded
* Out of reset this entry is only 4K.
+ * 0xfc000000 256K NAND FLASH (CS3)
+ * 0xfe000000 32M NOR FLASH (CS0)
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000,
- CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_16M, 1),
+ 0, 0, BOOKE_PAGESZ_64M, 1),
/*
- * TLBe 1: 16M Non-cacheable, guarded
- * 0xfe000000 16M FLASH (lower half)
+ * TLBe 1: 256KB Non-cacheable, guarded
+ * 0xf8000000 32K BCSR
+ * 0xf8008000 32K PIB (CS4)
+ * 0xf8010000 32K PIB (CS5)
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_16M, 1),
+ 0, 1, BOOKE_PAGESZ_256K, 1),
/*
* TLBe 2: 256M Non-cacheable, guarded
@@ -88,16 +90,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_64M, 1),
-
- /*
- * TLBe 5: 256K Non-cacheable, guarded
- * 0xf8000000 32K BCSR
- * 0xf8008000 32K PIB (CS4)
- * 0xf8010000 32K PIB (CS5)
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256K, 1),
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 3d07a5b..17ea3bb 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -181,6 +181,29 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
+/* Chip select 3 - NAND */
+#define CONFIG_SYS_NAND_BASE 0xFC000000
+#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE 1
+#define CONFIG_CMD_NAND 1
+#define CONFIG_NAND_FSL_ELBC 1
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
+ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_PS_8 /* Port Size = 8 bit */ \
+ | BR_MS_FCM /* MSEL = FCM */ \
+ | BR_V) /* valid */
+#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
+ | OR_FCM_CSCT \
+ | OR_FCM_CST \
+ | OR_FCM_CHT \
+ | OR_FCM_SCY_1 \
+ | OR_FCM_TRLX \
+ | OR_FCM_EHTR)
+#define CONFIG_SYS_BR3_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR3_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
/*
* SDRAM on the LocalBus
--
1.6.3.3
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH 3/7] mpc85xx: Add eLBC NAND support for MPC8569E-MDS boards
2009-08-19 18:37 [U-Boot] [PATCH 3/7] mpc85xx: Add eLBC NAND support for MPC8569E-MDS boards Anton Vorontsov
@ 2009-09-16 4:17 ` Kumar Gala
2009-10-12 18:07 ` Anton Vorontsov
0 siblings, 1 reply; 5+ messages in thread
From: Kumar Gala @ 2009-09-16 4:17 UTC (permalink / raw)
To: u-boot
On Aug 19, 2009, at 1:37 PM, Anton Vorontsov wrote:
> Simply add some defines, and adjust TLBe setup to include some
> space for eLBC NAND.
>
> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
> ---
> board/freescale/mpc8569mds/tlb.c | 30 +++++++++++-------------------
> include/configs/MPC8569MDS.h | 23 +++++++++++++++++++++++
> 2 files changed, 34 insertions(+), 19 deletions(-)
>
> diff --git a/board/freescale/mpc8569mds/tlb.c b/board/freescale/
> mpc8569mds/tlb.c
> index d3b251e..3b8ee05 100644
> --- a/board/freescale/mpc8569mds/tlb.c
> +++ b/board/freescale/mpc8569mds/tlb.c
> @@ -46,22 +46,24 @@ struct fsl_e_tlb_entry tlb_table[] = {
>
> /* TLB 1 Initializations */
> /*
> - * TLBe 0: 16M Non-cacheable, guarded
> - * 0xff000000 16M FLASH (upper half)
> + * TLBe 0: 64M Non-cacheable, guarded
> * Out of reset this entry is only 4K.
> + * 0xfc000000 256K NAND FLASH (CS3)
> + * 0xfe000000 32M NOR FLASH (CS0)
> */
> - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000,
> - CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
> + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
> MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, 0, BOOKE_PAGESZ_16M, 1),
> + 0, 0, BOOKE_PAGESZ_64M, 1),
>
> /*
> - * TLBe 1: 16M Non-cacheable, guarded
> - * 0xfe000000 16M FLASH (lower half)
> + * TLBe 1: 256KB Non-cacheable, guarded
> + * 0xf8000000 32K BCSR
> + * 0xf8008000 32K PIB (CS4)
> + * 0xf8010000 32K PIB (CS5)
> */
> - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
> + SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
> MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, 1, BOOKE_PAGESZ_16M, 1),
> + 0, 1, BOOKE_PAGESZ_256K, 1),
>
> /*
> * TLBe 2: 256M Non-cacheable, guarded
> @@ -88,16 +90,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
> SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
> MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> 0, 4, BOOKE_PAGESZ_64M, 1),
> -
> - /*
> - * TLBe 5: 256K Non-cacheable, guarded
> - * 0xf8000000 32K BCSR
> - * 0xf8008000 32K PIB (CS4)
> - * 0xf8010000 32K PIB (CS5)
> - */
> - SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
> - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, 5, BOOKE_PAGESZ_256K, 1),
> };
>
> int num_tlb_entries = ARRAY_SIZE(tlb_table);
> diff --git a/include/configs/MPC8569MDS.h b/include/configs/
> MPC8569MDS.h
> index 3d07a5b..17ea3bb 100644
> --- a/include/configs/MPC8569MDS.h
> +++ b/include/configs/MPC8569MDS.h
> @@ -181,6 +181,29 @@ extern unsigned long get_clock_freq(void);
> #define CONFIG_SYS_FLASH_CFI
> #define CONFIG_SYS_FLASH_EMPTY_INFO
>
> +/* Chip select 3 - NAND */
> +#define CONFIG_SYS_NAND_BASE 0xFC000000
Is it possible to have it at 0xffa00000 so we match other FSL boards?
> +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
> +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
> +#define CONFIG_SYS_MAX_NAND_DEVICE 1
> +#define CONFIG_MTD_NAND_VERIFY_WRITE 1
> +#define CONFIG_CMD_NAND 1
> +#define CONFIG_NAND_FSL_ELBC 1
> +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
> +#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
> + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
> + | BR_PS_8 /* Port Size = 8 bit */ \
> + | BR_MS_FCM /* MSEL = FCM */ \
> + | BR_V) /* valid */
> +#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
> + | OR_FCM_CSCT \
> + | OR_FCM_CST \
> + | OR_FCM_CHT \
> + | OR_FCM_SCY_1 \
> + | OR_FCM_TRLX \
> + | OR_FCM_EHTR)
> +#define CONFIG_SYS_BR3_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base
> Address */
> +#define CONFIG_SYS_OR3_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options
> */
>
> /*
> * SDRAM on the LocalBus
> --
> 1.6.3.3
^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH 3/7] mpc85xx: Add eLBC NAND support for MPC8569E-MDS boards
2009-09-16 4:17 ` Kumar Gala
@ 2009-10-12 18:07 ` Anton Vorontsov
0 siblings, 0 replies; 5+ messages in thread
From: Anton Vorontsov @ 2009-10-12 18:07 UTC (permalink / raw)
To: u-boot
On Tue, Sep 15, 2009 at 11:17:04PM -0500, Kumar Gala wrote:
[...]
> >+/* Chip select 3 - NAND */
> >+#define CONFIG_SYS_NAND_BASE 0xFC000000
>
> Is it possible to have it at 0xffa00000 so we match other FSL boards?
No, not without reshuffling all the mappings. On MPC8569E-MDS NOR
flash starts at 0xfe000000, ends at 0xffffffff (32MB).
Thanks,
--
Anton Vorontsov
email: cbouatmailru at gmail.com
irc://irc.freenode.net/bd2
^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH 3/7] mpc85xx: Add eLBC NAND support for MPC8569E-MDS boards
2009-10-15 13:46 [U-Boot] [PATCH 0/7] Some patches for MPC8569E-MDS Anton Vorontsov
@ 2009-10-15 13:47 ` Anton Vorontsov
2009-10-27 15:10 ` Kumar Gala
0 siblings, 1 reply; 5+ messages in thread
From: Anton Vorontsov @ 2009-10-15 13:47 UTC (permalink / raw)
To: u-boot
Simply add some defines, and adjust TLBe setup to include some
space for eLBC NAND.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
board/freescale/mpc8569mds/tlb.c | 30 +++++++++++-------------------
include/configs/MPC8569MDS.h | 23 +++++++++++++++++++++++
2 files changed, 34 insertions(+), 19 deletions(-)
diff --git a/board/freescale/mpc8569mds/tlb.c b/board/freescale/mpc8569mds/tlb.c
index d3b251e..3b8ee05 100644
--- a/board/freescale/mpc8569mds/tlb.c
+++ b/board/freescale/mpc8569mds/tlb.c
@@ -46,22 +46,24 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 1 Initializations */
/*
- * TLBe 0: 16M Non-cacheable, guarded
- * 0xff000000 16M FLASH (upper half)
+ * TLBe 0: 64M Non-cacheable, guarded
* Out of reset this entry is only 4K.
+ * 0xfc000000 256K NAND FLASH (CS3)
+ * 0xfe000000 32M NOR FLASH (CS0)
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000,
- CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_16M, 1),
+ 0, 0, BOOKE_PAGESZ_64M, 1),
/*
- * TLBe 1: 16M Non-cacheable, guarded
- * 0xfe000000 16M FLASH (lower half)
+ * TLBe 1: 256KB Non-cacheable, guarded
+ * 0xf8000000 32K BCSR
+ * 0xf8008000 32K PIB (CS4)
+ * 0xf8010000 32K PIB (CS5)
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_16M, 1),
+ 0, 1, BOOKE_PAGESZ_256K, 1),
/*
* TLBe 2: 256M Non-cacheable, guarded
@@ -88,16 +90,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_64M, 1),
-
- /*
- * TLBe 5: 256K Non-cacheable, guarded
- * 0xf8000000 32K BCSR
- * 0xf8008000 32K PIB (CS4)
- * 0xf8010000 32K PIB (CS5)
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256K, 1),
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 3d07a5b..17ea3bb 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -181,6 +181,29 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
+/* Chip select 3 - NAND */
+#define CONFIG_SYS_NAND_BASE 0xFC000000
+#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE 1
+#define CONFIG_CMD_NAND 1
+#define CONFIG_NAND_FSL_ELBC 1
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
+ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_PS_8 /* Port Size = 8 bit */ \
+ | BR_MS_FCM /* MSEL = FCM */ \
+ | BR_V) /* valid */
+#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
+ | OR_FCM_CSCT \
+ | OR_FCM_CST \
+ | OR_FCM_CHT \
+ | OR_FCM_SCY_1 \
+ | OR_FCM_TRLX \
+ | OR_FCM_EHTR)
+#define CONFIG_SYS_BR3_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR3_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
/*
* SDRAM on the LocalBus
--
1.6.3.3
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH 3/7] mpc85xx: Add eLBC NAND support for MPC8569E-MDS boards
2009-10-15 13:47 ` [U-Boot] [PATCH 3/7] mpc85xx: Add eLBC NAND support for MPC8569E-MDS boards Anton Vorontsov
@ 2009-10-27 15:10 ` Kumar Gala
0 siblings, 0 replies; 5+ messages in thread
From: Kumar Gala @ 2009-10-27 15:10 UTC (permalink / raw)
To: u-boot
On Oct 15, 2009, at 8:47 AM, Anton Vorontsov wrote:
> Simply add some defines, and adjust TLBe setup to include some
> space for eLBC NAND.
>
> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
> ---
> board/freescale/mpc8569mds/tlb.c | 30 +++++++++++-------------------
> include/configs/MPC8569MDS.h | 23 +++++++++++++++++++++++
> 2 files changed, 34 insertions(+), 19 deletions(-)
applied to 85xx
- k
^ permalink raw reply [flat|nested] 5+ messages in thread
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2009-08-19 18:37 [U-Boot] [PATCH 3/7] mpc85xx: Add eLBC NAND support for MPC8569E-MDS boards Anton Vorontsov
2009-09-16 4:17 ` Kumar Gala
2009-10-12 18:07 ` Anton Vorontsov
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2009-10-15 13:46 [U-Boot] [PATCH 0/7] Some patches for MPC8569E-MDS Anton Vorontsov
2009-10-15 13:47 ` [U-Boot] [PATCH 3/7] mpc85xx: Add eLBC NAND support for MPC8569E-MDS boards Anton Vorontsov
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