[U-Boot] [PATCH] ppc/85xx: Added PCIe support for P1 P2 RDB

[U-Boot] [PATCH] ppc/85xx: Added PCIe support for P1 P2 RDB

[Poonam Aggrwal]

* Added PCIe support for P1 P2 RDB
* Calls the fsl_pci_init_port function to initialize all the PCIe ports
  on the board.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
- applies on git.denx.de/u-boot-mpc85xx.git branch->next
 board/freescale/p1_p2_rdb/Makefile |    1 +
 board/freescale/p1_p2_rdb/pci.c    |  112 ++++++++++++++++++++++++++++++++++++
 include/configs/P1_P2_RDB.h        |    6 ++
 3 files changed, 119 insertions(+), 0 deletions(-)
 create mode 100644 board/freescale/p1_p2_rdb/pci.c

diff --git a/board/freescale/p1_p2_rdb/Makefile b/board/freescale/p1_p2_rdb/Makefile
index 9107263..c366f7c 100644
--- a/board/freescale/p1_p2_rdb/Makefile
+++ b/board/freescale/p1_p2_rdb/Makefile
@@ -27,6 +27,7 @@ LIB	= $(obj)lib$(BOARD).a
 COBJS-y	+= $(BOARD).o
 COBJS-y	+= law.o
 COBJS-y	+= tlb.o
+COBJS-$(CONFIG_PCI)  += pci.o
 COBJS-y	+= ddr.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c
new file mode 100644
index 0000000..3867705
--- /dev/null
+++ b/board/freescale/p1_p2_rdb/pci.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/immap_85xx.h>
+#include <asm/io.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif
+
+#ifdef CONFIG_PCIE2
+static struct pci_controller pcie2_hose;
+#endif
+
+void pci_init_board(void)
+{
+	struct fsl_pci_info pci_info[2];
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	uint devdisr = in_be32(&gur->devdisr);
+	uint io_sel = (in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+	uint host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16;
+	int num = 0;
+	int first_free_busno = 0;
+	int last_busno;
+
+	int pcie_ep, pcie_configured;
+
+	debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
+			devdisr, io_sel, host_agent);
+
+	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
+		printf ("    eTSEC2 is in sgmii mode.\n");
+
+#ifdef CONFIG_PCIE2
+	SET_STD_PCIE_INFO(pci_info[num], 2);
+	pcie_ep = (host_agent == 2) || (host_agent == 4) ||
+		(host_agent == 6) || (host_agent == 0);
+	pcie_configured  = (io_sel == 0xE);
+
+	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+		printf ("\n  PCIE2 connected to Slot 1 as %s (base address %x)",
+			pcie_ep ? "End Point": "Root Complex", pci_info[num].regs);
+		last_busno = fsl_pci_init_port(&pci_info[num],
+					&pcie2_hose, first_free_busno);
+		first_free_busno = last_busno;
+		num++;
+	} else {
+		printf ("    PCIE2: disabled\n");
+	}
+#else
+	set_bits32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
+#endif
+
+#ifdef CONFIG_PCIE1
+	SET_STD_PCIE_INFO(pci_info[num], 1);
+
+	pcie_ep = (host_agent <= 1) || (host_agent == 4) ||
+		(host_agent == 5);
+	pcie_configured  = (io_sel == 0xE);
+
+	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+		printf ("\n  PCIE1 connected to Slot 2 as %s (base address %x)",
+				pcie_ep ? "End Point" : "Root Complex",
+				pci_info[num].regs);
+		last_busno = fsl_pci_init_port(&pci_info[num],
+					&pcie1_hose, first_free_busno);
+		first_free_busno = last_busno;
+		num++;
+	} else {
+		printf ("    PCIE1: disabled\n");
+	}
+#else
+	set_bits32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
+#endif
+}
+
+void ft_pci_board_setup(void *blob)
+{
+#ifdef CONFIG_PCIE2
+	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
+#endif
+#ifdef CONFIG_PCIE1
+	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
+#endif
+}
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index 9591641..6d44d6c 100644
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -35,6 +35,12 @@
 #define CONFIG_E500		1	/* BOOKE e500 family */
 #define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48/P1020/P2020,etc*/
 #define CONFIG_FSL_ELBC		1	/* Enable eLBC Support */
+#define CONFIG_PCI		1	/* Enable PCI/PCIE */
+#define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
-- 
1.5.6.5

[U-Boot] [PATCH] ppc/85xx: Added PCIe support for P1 P2 RDB

[Wolfgang Denk]

Dear Poonam Aggrwal,

In message <1250775054-20418-1-git-send-email-poonam.aggrwal@freescale.com> you wrote:
> * Added PCIe support for P1 P2 RDB
> * Calls the fsl_pci_init_port function to initialize all the PCIe ports
>   on the board.
> 
> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> - applies on git.denx.de/u-boot-mpc85xx.git branch->next
>  board/freescale/p1_p2_rdb/Makefile |    1 +
>  board/freescale/p1_p2_rdb/pci.c    |  112 ++++++++++++++++++++++++++++++++++++
>  include/configs/P1_P2_RDB.h        |    6 ++
>  3 files changed, 119 insertions(+), 0 deletions(-)
>  create mode 100644 board/freescale/p1_p2_rdb/pci.c
> 
> diff --git a/board/freescale/p1_p2_rdb/Makefile b/board/freescale/p1_p2_rdb/Makefile
> index 9107263..c366f7c 100644
> --- a/board/freescale/p1_p2_rdb/Makefile
> +++ b/board/freescale/p1_p2_rdb/Makefile
> @@ -27,6 +27,7 @@ LIB	= $(obj)lib$(BOARD).a
>  COBJS-y	+= $(BOARD).o
>  COBJS-y	+= law.o
>  COBJS-y	+= tlb.o
> +COBJS-$(CONFIG_PCI)  += pci.o
>  COBJS-y	+= ddr.o

Please (make and) keep list sorted.

...
> +void ft_pci_board_setup(void *blob)
> +{
> +#ifdef CONFIG_PCIE2
> +	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);

PCIE2 ... pci1 ... pcie2 ???

> +#endif
> +#ifdef CONFIG_PCIE1
> +	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);

PCIE1 ... pci2 ... pcie1 ???

This looks broken to me?


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
As far as the laws of mathematics refer to reality, they are not cer-
tain, and as far as they are certain, they do not refer  to  reality.
                                                   -- Albert Einstein

[U-Boot] [PATCH] ppc/85xx: Added PCIe support for P1 P2 RDB

[Kumar Gala]

On Aug 20, 2009, at 10:14 AM, Wolfgang Denk wrote:

> Dear Poonam Aggrwal,
>
> In message <1250775054-20418-1-git-send-email-poonam.aggrwal@freescale.com 
> > you wrote:
>> * Added PCIe support for P1 P2 RDB
>> * Calls the fsl_pci_init_port function to initialize all the PCIe  
>> ports
>>  on the board.
>>
>> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
>> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
>> ---
>> - applies on git.denx.de/u-boot-mpc85xx.git branch->next
>> board/freescale/p1_p2_rdb/Makefile |    1 +
>> board/freescale/p1_p2_rdb/pci.c    |  112 ++++++++++++++++++++++++++ 
>> ++++++++++
>> include/configs/P1_P2_RDB.h        |    6 ++
>> 3 files changed, 119 insertions(+), 0 deletions(-)
>> create mode 100644 board/freescale/p1_p2_rdb/pci.c
>>
>> diff --git a/board/freescale/p1_p2_rdb/Makefile b/board/freescale/ 
>> p1_p2_rdb/Makefile
>> index 9107263..c366f7c 100644
>> --- a/board/freescale/p1_p2_rdb/Makefile
>> +++ b/board/freescale/p1_p2_rdb/Makefile
>> @@ -27,6 +27,7 @@ LIB	= $(obj)lib$(BOARD).a
>> COBJS-y	+= $(BOARD).o
>> COBJS-y	+= law.o
>> COBJS-y	+= tlb.o
>> +COBJS-$(CONFIG_PCI)  += pci.o
>> COBJS-y	+= ddr.o
>
> Please (make and) keep list sorted.
>
> ...
>> +void ft_pci_board_setup(void *blob)
>> +{
>> +#ifdef CONFIG_PCIE2
>> +	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
>
> PCIE2 ... pci1 ... pcie2 ???

The device tree has always been more generic and used 'pci' for PCI,  
PCI-X, and PCIe buses.

>
>> +#endif
>> +#ifdef CONFIG_PCIE1
>> +	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
>
> PCIE1 ... pci2 ... pcie1 ???
>
> This looks broken to me?


This is actually correct.. This has to do w/stupid FSL documentation  
and #.  The device tree "orders" PCI buses based on there register  
offset in CCSRBAR.  So 0x9000 is pci1, 0xa000 is pci2.  However FSL  
docs and some internal SoC screwness lists the PCIe controller @ 9000  
as PCIE2 and the one at A000 as PCIE1.

Probably should add a comment in the code about this.

- k

[U-Boot] [PATCH] ppc/85xx: Added PCIe support for P1 P2 RDB

[Wolfgang Denk]

Dear Kumar Gala,

In message <1938B866-A0C2-4152-8085-4BCC4E1A78B9@kernel.crashing.org> you wrote:
> 
> > PCIE1 ... pci2 ... pcie1 ???
> >
> > This looks broken to me?
> 
> 
> This is actually correct.. This has to do w/stupid FSL documentation  
> and #.  The device tree "orders" PCI buses based on there register  
> offset in CCSRBAR.  So 0x9000 is pci1, 0xa000 is pci2.  However FSL  
> docs and some internal SoC screwness lists the PCIe controller @ 9000  
> as PCIE2 and the one at A000 as PCIE1.
> 
> Probably should add a comment in the code about this.

Yes, please. This looks just too much like a copy & paste error.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
There are three ways to get something  done:  do  it  yourself,  hire
someone, or forbid your kids to do it.