[U-Boot] [PATCH v3] mpc83xx: update LCRR register handling

[Kim Phillips <kim.phillips@freescale.com>]

On Thu, 27 Aug 2009 08:20:35 +0200
Heiko Schocher <hs@denx.de> wrote:

> MPC8379E RM says (10-34):
> Once LCRR[CLKDIV] is written, the register should be read, and then
> an isync should be executed.
> So update this in code.
> Also define a LCRR mask for processors, which uses not all bits
> in the LCRR register (as for example mpc832x did).
> 
> Signed-off-by: Heiko Schocher <hs@denx.de>
> ---
> changes since v1:
> - added comment from DaveLiu. moved LCRR setting to
>   cpu_init_r()
> 
> changes since v2:
>   - added comment from Kim Phillips
>     changed LCRR_MASK to 0x7fffffff
>     use clrsetbits()

Heiko - let's go with the SCCR approach of setting bits in the LCRR,
and have board config files only specify values for fields they're
modifying from the reset value for their processor (this can be
extended to 85xx-world).

Kim