[U-Boot] PPC440GX: DDR ECC init time.

[Stefan Roese <sr@denx.de>]

Hi Wouter,

On Friday 04 September 2009 14:34:49 Wouter Eckhardt wrote:
> I'm making quite good progress porting U-Boot (2009.03) to my custom
> PPC440GX board.

2009.03 is already "old". I suggest you use the 2009.09 release.

> Right now I'm trying to solve a little problem I have
> with board start-up time when I enable ECC on DDR RAM. The board
> literally takes minutes to initialize RAM. I'm guessing this is due to
> the fact that ecc_init() fills the entire RAM (the comments already
> suggest some performance enhancements can be implemented).

d-cache is the solution.
 
> I've tried solving this by shortly enabling the D cache before writing
> RAM and disabling the D cache afterwards, using the function
> change_tlb(). However, if I enable the D cache using change_tlb() and
> supply it with the same parameters ecc_init() receives, I get an
> exception when change_tlb() invalidates the cache.

Did you flush the caches? You need to be careful here, when changing TLB 
attributes.

Which DDR2 init code are you using btw? A specific custom code with fixed 
settings? Or the 4xx common SPD code? I suggest you take a look at the common 
DDR2 code (44x_spd_ddr2.c). ECC handling is done there already with caches 
enabled. This should give you an idea.

Cheers,
Stefan

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