From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefan Roese Date: Fri, 4 Sep 2009 14:50:32 +0200 Subject: [U-Boot] PPC440GX: DDR ECC init time. In-Reply-To: <4CD35CD1F8085945B597F80EEC8942130348D9E6@exc01.bk.prodrive.nl> References: <4CD35CD1F8085945B597F80EEC8942130348D9E6@exc01.bk.prodrive.nl> Message-ID: <200909041450.32056.sr@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Wouter, On Friday 04 September 2009 14:34:49 Wouter Eckhardt wrote: > I'm making quite good progress porting U-Boot (2009.03) to my custom > PPC440GX board. 2009.03 is already "old". I suggest you use the 2009.09 release. > Right now I'm trying to solve a little problem I have > with board start-up time when I enable ECC on DDR RAM. The board > literally takes minutes to initialize RAM. I'm guessing this is due to > the fact that ecc_init() fills the entire RAM (the comments already > suggest some performance enhancements can be implemented). d-cache is the solution. > I've tried solving this by shortly enabling the D cache before writing > RAM and disabling the D cache afterwards, using the function > change_tlb(). However, if I enable the D cache using change_tlb() and > supply it with the same parameters ecc_init() receives, I get an > exception when change_tlb() invalidates the cache. Did you flush the caches? You need to be careful here, when changing TLB attributes. Which DDR2 init code are you using btw? A specific custom code with fixed settings? Or the 4xx common SPD code? I suggest you take a look at the common DDR2 code (44x_spd_ddr2.c). ECC handling is done there already with caches enabled. This should give you an idea. Cheers, Stefan -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de