[U-Boot] [PATCH] ppc4xx: Add SDRAM detection for PMC440 boards

Stefan Roese
2009-09-29T15:44:24Z

On Tuesday 29 September 2009 17:30:38 Matthias Fuchs wrote:
> This patch adds support to detect the amount of DDR2 SDRAM
> on PMC440 modules. Detection is done by probing through
> a list of available and supported hardware configurations
> from 256MB to 1GByte.

I assume its the other way around? From 1GB to 256MB.

> The static TLB entry is replaced by dynamically created entries.

Some further comment below.

> Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
> ---
> board/esd/pmc440/init.S | 13 +++----
> board/esd/pmc440/sdram.c | 83
> ++++++++++++++++++++++++++++++++------------- include/configs/PMC440.h |
> 1 -
> 3 files changed, 64 insertions(+), 33 deletions(-)
>
> diff --git a/board/esd/pmc440/init.S b/board/esd/pmc440/init.S
> index 26a8282..da5bd8d 100644
> --- a/board/esd/pmc440/init.S
> +++ b/board/esd/pmc440/init.S
> @@ -23,7 +23,7 @@
> #include <asm-ppc/mmu.h>
> #include <config.h>
>
> -/*************************************************************************
> * +/*
> * TLB TABLE
> *
> * This table is used by the cpu boot code to setup the initial tlb
> @@ -32,7 +32,7 @@
> *
> * Pointer to the table is returned in r1
> *
> -
> *************************************************************************/
> + */
> .section .bootpg,"ax"
> .globl tlbtab
>
> @@ -49,12 +49,9 @@ tlbtab:
> tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K,
> CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G ) #endif
>
> - /* TLB-entry for DDR SDRAM (Up to 2GB) */
> -#ifdef CONFIG_4xx_DCACHE
> - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0,
> AC_R|AC_W|AC_X|SA_G) -#else
> - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0,
> AC_R|AC_W|AC_X|SA_G|SA_I ) -#endif
> + /* TLB entries for DDR2 SDRAM are generated dynamically */
> +
> + /* TLB-entry for DDR SDRAM are created dynamically from initdram() */

Twice nearly the same comment. Please remove one.

>
> #ifdef CONFIG_SYS_INIT_RAM_DCACHE
> /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
> diff --git a/board/esd/pmc440/sdram.c b/board/esd/pmc440/sdram.c
> index bb46ecc..826050c 100644
> --- a/board/esd/pmc440/sdram.c
> +++ b/board/esd/pmc440/sdram.c
> @@ -1,4 +1,7 @@
> /*
> + * (C) Copyright 2009
> + * Matthias Fuchs, esd gmbh, matthias.fuchs at esd.eu
> + *
> * (C) Copyright 2006
> * Sylvie Gohl, AMCC/IBM, gohl.sylvie at fr.ibm.com
> * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol at fr.ibm.com
> @@ -31,33 +34,30 @@
> #include <common.h>
> #include <asm/processor.h>
> #include <asm/io.h>
> +#include <asm/mmu.h>
> #include <ppc440.h>
>
> extern int denali_wait_for_dlllock(void);
> extern void denali_core_search_data_eye(void);
>
> +struct sdram_conf_s {
> + ulong size;
> + int rows;
> + int banks;
> +};
>
> -#if defined(CONFIG_NAND_SPL)
> -/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
> - * for the 4k NAND boot image so define bus_frequency to 133MHz here
> - * which is save for the refresh counter setup.
> - */
> -#define get_bus_freq(val) 133000000
> -#endif
> +struct sdram_conf_s sdram_conf[] = {
> + {(1024 << 20), 14, 8}, /* 1GByte: 4x2GBit, 14x10, 8 banks */
> + {(512 << 20), 13, 8}, /* 512MByte: 4x1GBit, 13x10, 8 banks */
> + {(256 << 20), 13, 4}, /* 256MByte: 4x512MBit, 13x10, 4 banks */
> +};
>
> -/*************************************************************************
> - *
> +/*
> * initdram -- 440EPx's DDR controller is a DENALI Core
> - *
> - ************************************************************************/
> -phys_size_t initdram (int board_type)
> + */
> +int initdram_by_rb(int rows, int banks)
> {
> -#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
> -#if !defined(CONFIG_NAND_SPL)
> ulong speed = get_bus_freq(0);
> -#else
> - ulong speed = 133333333; /* 133MHz is on the safe side */
> -#endif
>
> mtsdram(DDR0_02, 0x00000000);
>
> @@ -89,21 +89,25 @@ phys_size_t initdram (int board_type)
> mtsdram(DDR0_27, 0x0000682B);
> mtsdram(DDR0_28, 0x00000000);
> mtsdram(DDR0_31, 0x00000000);
> - mtsdram(DDR0_42, 0x01000006);
> - mtsdram(DDR0_43, 0x030A0200);
> +
> + mtsdram(DDR0_42,
> + DDR0_42_ADDR_PINS_DECODE(14 - rows) |
> + 0x00000006);
> + mtsdram(DDR0_43,
> + DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0) |
> + 0x030A0200);
> +
> mtsdram(DDR0_44, 0x00000003);
> mtsdram(DDR0_02, 0x00000001);
>
> denali_wait_for_dlllock();
> -#endif /* #ifndef CONFIG_NAND_U_BOOT */
>
> #ifdef CONFIG_DDR_DATA_EYE
> - /* -----------------------------------------------------------+
> + /*
> * Perform data eye search if requested.
> - * ----------------------------------------------------------*/
> + */
> denali_core_search_data_eye();
> #endif
> -
> /*
> * Clear possible errors resulting from data-eye-search.
> * If not done, then we could get an interrupt later on when
> @@ -111,5 +115,36 @@ phys_size_t initdram (int board_type)
> */
> set_mcsr(get_mcsr());
>
> - return (CONFIG_SYS_MBYTES_SDRAM << 20);
> + return 0;
> +}
> +
> +
> +phys_size_t initdram (int board_type)

Please remove the space before "(".

Thanks.

Cheers,
Stefan

--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de