From mboxrd@z Thu Jan  1 00:00:00 1970
From: Simon Kagstrom <simon.kagstrom@netinsight.net>
Date: Mon, 19 Oct 2009 08:32:00 +0200
Subject: [U-Boot] [PATCH] sheevaplug: correct SDRAM address control
 register value
In-Reply-To: <1255712955-27760-1-git-send-email-mark.asselstine@windriver.com>
References: <1255712955-27760-1-git-send-email-mark.asselstine@windriver.com>
Message-ID: <20091019083200.409c0629@marrow.netinsight.se>
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On Fri, 16 Oct 2009 13:09:15 -0400
Mark Asselstine <mark.asselstine@windriver.com> wrote:

> The SheevaPlug DevKit is shipped with 4x8 by 1Gb DDR devices in
> two banks for a total of 512MB of RAM. Based on this configuration
> the existing values for SDRAM address control register are incorrect

> -DATA 0xFFD01410 0x00000099	#  DDR Address Control
> -# bit1-0:   01, Cs0width=x16
> -# bit3-2:   10, Cs0size=512Mb
> -# bit5-4:   01, Cs1width=x16
> -# bit7-6:   10, Cs1size=512Mb
> +DATA 0xFFD01410 0x000000cc	#  DDR Address Control
> +# bit1-0:   00, Cs0width=reserved
> +# bit3-2:   11, Cs0size=1Gb
> +# bit5-4:   00, Cs1width=reserved
> +# bit7-6:   11, Cs1size=1Gb

I did the same change for OpenRD before, and bit 1-0 and 5-4 are not
really reserved (it's fixed in a later version of the Marvell
documentation), so the comments should be

# bit1-0:   00, Cs0width=x8
# bit3-2:   11, Cs0size=1Gb
# bit5-4:   00, Cs1width=x8
# bit7-6:   11, Cs1size=1Gb

Nice catch!

// Simon