[U-Boot] [PATCH V5 1/4] add TI DA8xx support: DA8xx includes

[U-Boot] [PATCH V5 1/4] add TI DA8xx support: DA8xx includes

[Nick Thompson]

Provides initial support for TI OMAP-L1x/DA8xx SoC devices.
See http://www.ti.com

The DA8xx devices are similar to DaVinci devices but have a differing
memory map and updated peripheral versions.

Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
Applies to u-boot-ti

 include/asm-arm/arch-davinci/hardware.h |  237 +++++++++++++++++++++++++++++++
 include/asm-arm/arch-davinci/i2c_defs.h |    5 +
 2 files changed, 242 insertions(+), 0 deletions(-)

diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h
index acf12ea..81cc8ab 100644
--- a/include/asm-arm/arch-davinci/hardware.h
+++ b/include/asm-arm/arch-davinci/hardware.h
@@ -49,6 +49,8 @@ typedef volatile unsigned int *	dv_reg_p;
  * on other DaVinci chips.  Double check them before you try
  * using the addresses ... or PSC module identifiers, etc.
  */
+#ifndef CONFIG_SOC_DA8XX
+
 #define DAVINCI_DMA_3PCC_BASE			(0x01c00000)
 #define DAVINCI_DMA_3PTC0_BASE			(0x01c10000)
 #define DAVINCI_DMA_3PTC1_BASE			(0x01c10400)
@@ -116,10 +118,46 @@ typedef volatile unsigned int *	dv_reg_p;
 
 #endif
 
+#else /* CONFIG_SOC_DA8XX */
+
+#define DAVINCI_UART0_BASE			0x01c42000
+#define DAVINCI_UART1_BASE			0x01d0c000
+#define DAVINCI_UART2_BASE			0x01d0d000
+#define DAVINCI_I2C0_BASE			0x01c22000
+#define DAVINCI_I2C1_BASE			0x01e28000
+#define DAVINCI_TIMER0_BASE			0x01c20000
+#define DAVINCI_TIMER1_BASE			0x01c21000
+#define DAVINCI_WDOG_BASE			0x01c21000
+#define DAVINCI_PLL_CNTRL0_BASE			0x01c11000
+#define DAVINCI_PSC0_BASE			0x01c10000
+#define DAVINCI_PSC1_BASE			0x01e27000
+#define DAVINCI_SPI0_BASE			0x01c41000
+#define DAVINCI_USB_OTG_BASE			0x01e00000
+#define DAVINCI_SPI1_BASE			0x01e12000
+#define DAVINCI_GPIO_BASE			0x01e26000
+#define DAVINCI_EMAC_CNTRL_REGS_BASE		0x01e23000
+#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE	0x01e22000
+#define DAVINCI_EMAC_WRAPPER_RAM_BASE		0x01e20000
+#define DAVINCI_MDIO_CNTRL_REGS_BASE		0x01e24000
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x68000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE	0x40000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE	0x60000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE	0x62000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE	0x64000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE	0x66000000
+#define DAVINCI_DDR_EMIF_CTRL_BASE		0xb0000000
+#define DAVINCI_DDR_EMIF_DATA_BASE		0xc0000000
+#define DAVINCI_INTC_BASE			0xfffee000
+#define DAVINCI_BOOTCFG_BASE			0x01c14000
+
+#endif /* CONFIG_SOC_DA8XX */
+
 /* Power and Sleep Controller (PSC) Domains */
 #define DAVINCI_GPSC_ARMDOMAIN		0
 #define DAVINCI_GPSC_DSPDOMAIN		1
 
+#ifndef CONFIG_SOC_DA8XX
+
 #define DAVINCI_LPSC_VPSSMSTR		0
 #define DAVINCI_LPSC_VPSSSLV		1
 #define DAVINCI_LPSC_TPCC		2
@@ -166,6 +204,52 @@ typedef volatile unsigned int *	dv_reg_p;
 #define DAVINCI_DM646X_LPSC_UART0	26
 #define DAVINCI_DM646X_LPSC_I2C		31
 
+#else /* CONFIG_SOC_DA8XX */
+
+enum davinci_lpsc_ids {
+	DAVINCI_LPSC_TPCC = 0,
+	DAVINCI_LPSC_TPTC0,
+	DAVINCI_LPSC_TPTC1,
+	DAVINCI_LPSC_AEMIF,
+	DAVINCI_LPSC_SPI0,
+	DAVINCI_LPSC_MMC_SD,
+	DAVINCI_LPSC_AINTC,
+	DAVINCI_LPSC_ARM_RAM_ROM,
+	DAVINCI_LPSC_SECCTL_KEYMGR,
+	DAVINCI_LPSC_UART0,
+	DAVINCI_LPSC_SCR0,
+	DAVINCI_LPSC_SCR1,
+	DAVINCI_LPSC_SCR2,
+	DAVINCI_LPSC_DMAX,
+	DAVINCI_LPSC_ARM,
+	DAVINCI_LPSC_GEM,
+	/* for LPSCs in PSC1, offset from 32 for differentiation */
+	DAVINCI_LPSC_PSC1_BASE = 32,
+	DAVINCI_LPSC_USB11,
+	DAVINCI_LPSC_USB20,
+	DAVINCI_LPSC_GPIO,
+	DAVINCI_LPSC_UHPI,
+	DAVINCI_LPSC_EMAC,
+	DAVINCI_LPSC_DDR_EMIF,
+	DAVINCI_LPSC_McASP0,
+	DAVINCI_LPSC_McASP1,
+	DAVINCI_LPSC_McASP2,
+	DAVINCI_LPSC_SPI1,
+	DAVINCI_LPSC_I2C1,
+	DAVINCI_LPSC_UART1,
+	DAVINCI_LPSC_UART2,
+	DAVINCI_LPSC_LCDC,
+	DAVINCI_LPSC_ePWM,
+	DAVINCI_LPSC_eCAP,
+	DAVINCI_LPSC_eQEP,
+	DAVINCI_LPSC_SCR_P0,
+	DAVINCI_LPSC_SCR_P1,
+	DAVINCI_LPSC_CR_P3,
+	DAVINCI_LPSC_L3_CBA_RAM
+};
+
+#endif /* CONFIG_SOC_DA8XX */
+
 void lpsc_on(unsigned int id);
 void dsp_on(void);
 
@@ -174,6 +258,8 @@ void davinci_enable_emac(void);
 void davinci_enable_i2c(void);
 void davinci_errata_workarounds(void);
 
+#ifndef CONFIG_SOC_DA8XX
+
 /* Some PSC defines */
 #define PSC_CHP_SHRTSW			(0x01c40038)
 #define PSC_GBLCTL			(0x01c41010)
@@ -194,6 +280,39 @@ void davinci_errata_workarounds(void);
 
 #define PSC_SILVER_BULLET		(0x01c41a20)
 
+#else /* CONFIG_SOC_DA8XX */
+
+#define PSC_PSC0_MODULE_ID_CNT		16
+#define PSC_PSC1_MODULE_ID_CNT		32
+
+struct davinci_psc_regs {
+	dv_reg	revid;
+	dv_reg	rsvd0[71];
+	dv_reg	ptcmd;
+	dv_reg	rsvd1;
+	dv_reg	ptstat;
+	dv_reg	rsvd2[437];
+	union {
+		struct {
+			dv_reg	mdstat[PSC_PSC0_MODULE_ID_CNT];
+			dv_reg	rsvd3[112];
+			dv_reg	mdctl[PSC_PSC0_MODULE_ID_CNT];
+		} psc0;
+		struct {
+			dv_reg	mdstat[PSC_PSC1_MODULE_ID_CNT];
+			dv_reg	rsvd3[96];
+			dv_reg	mdctl[PSC_PSC1_MODULE_ID_CNT];
+		} psc1;
+	};
+};
+
+#define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE)
+#define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE)
+
+#endif /* CONFIG_SOC_DA8XX */
+
+#ifndef CONFIG_SOC_DA8XX
+
 /* Miscellania... */
 #define VBPR				(0x20000020)
 
@@ -206,4 +325,122 @@ void davinci_errata_workarounds(void);
 #define PINMUX3				0x01c4000c
 #define PINMUX4				0x01c40010
 
+#else /* CONFIG_SOC_DA8XX */
+
+struct davinci_pllc_regs {
+	dv_reg	revid;
+	dv_reg	rsvd1[56];
+	dv_reg	rstype;
+	dv_reg	rsvd2[6];
+	dv_reg	pllctl;
+	dv_reg	ocsel;
+	dv_reg	rsvd3[2];
+	dv_reg	pllm;
+	dv_reg	prediv;
+	dv_reg	plldiv1;
+	dv_reg	plldiv2;
+	dv_reg	plldiv3;
+	dv_reg	oscdiv;
+	dv_reg	postdiv;
+	dv_reg	rsvd4[3];
+	dv_reg	pllcmd;
+	dv_reg	pllstat;
+	dv_reg	alnctl;
+	dv_reg	dchange;
+	dv_reg	cken;
+	dv_reg	ckstat;
+	dv_reg	systat;
+	dv_reg	rsvd5[3];
+	dv_reg	plldiv4;
+	dv_reg	plldiv5;
+	dv_reg	plldiv6;
+	dv_reg	plldiv7;
+	dv_reg	rsvd6[32];
+	dv_reg	emucnt0;
+	dv_reg	emucnt1;
+};
+
+#define davinci_pllc_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
+#define DAVINCI_PLLC_DIV_MASK	0x1f
+
+/* Clock IDs */
+enum davinci_clk_ids {
+	DAVINCI_SPI0_CLKID = 2,
+	DAVINCI_UART2_CLKID = 2,
+	DAVINCI_MDIO_CLKID = 4,
+	DAVINCI_ARM_CLKID = 6,
+	DAVINCI_PLLM_CLKID = 0xff,
+	DAVINCI_PLLC_CLKID = 0x100,
+	DAVINCI_AUXCLK_CLKID = 0x101
+};
+
+int clk_get(enum davinci_clk_ids id);
+
+/* Boot config */
+struct davinci_syscfg_regs {
+	dv_reg	revid;
+	dv_reg	rsvd[71];
+	dv_reg	pinmux[20];
+	dv_reg	suspsrc;
+	dv_reg	chipsig;
+	dv_reg	chipsig_clr;
+	dv_reg	cfgchip0;
+	dv_reg	cfgchip1;
+	dv_reg	cfgchip2;
+	dv_reg	cfgchip3;
+	dv_reg	cfgchip4;
+};
+
+#define davinci_syscfg_regs \
+	((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE)
+
+/* Emulation suspend bits */
+#define DAVINCI_SYSCFG_SUSPSRC_EMAC		(1 << 5)
+#define DAVINCI_SYSCFG_SUSPSRC_I2C		(1 << 16)
+#define DAVINCI_SYSCFG_SUSPSRC_SPI0		(1 << 21)
+#define DAVINCI_SYSCFG_SUSPSRC_UART2		(1 << 20)
+#define DAVINCI_SYSCFG_SUSPSRC_TIMER0		(1 << 27)
+
+/* Interrupt controller */
+struct davinci_aintc_regs {
+	dv_reg	revid;
+	dv_reg	cr;
+	dv_reg	dummy0[2];
+	dv_reg	ger;
+	dv_reg	dummy1[219];
+	dv_reg	ecr1;
+	dv_reg	ecr2;
+	dv_reg	ecr3;
+	dv_reg	dummy2[1117];
+	dv_reg	hier;
+};
+
+#define davinci_aintc_regs ((struct davinci_aintc_regs *)DAVINCI_INTC_BASE)
+
+struct davinci_uart_ctrl_regs {
+	dv_reg	revid1;
+	dv_reg	revid2;
+	dv_reg	pwremu_mgmt;
+	dv_reg	mdr;
+};
+
+#define DAVINCI_UART_CTRL_BASE 0x28
+#define DAVINCI_UART0_CTRL_ADDR (DAVINCI_UART0_BASE + DAVINCI_UART_CTRL_BASE)
+#define DAVINCI_UART1_CTRL_ADDR (DAVINCI_UART1_BASE + DAVINCI_UART_CTRL_BASE)
+#define DAVINCI_UART2_CTRL_ADDR (DAVINCI_UART2_BASE + DAVINCI_UART_CTRL_BASE)
+
+#define davinci_uart0_ctrl_regs \
+	((struct davinci_uart_ctrl_regs *)DAVINCI_UART0_CTRL_ADDR)
+#define davinci_uart1_ctrl_regs \
+	((struct davinci_uart_ctrl_regs *)DAVINCI_UART1_CTRL_ADDR)
+#define davinci_uart2_ctrl_regs \
+	((struct davinci_uart_ctrl_regs *)DAVINCI_UART2_CTRL_ADDR)
+
+/* UART PWREMU_MGMT definitions */
+#define DAVINCI_UART_PWREMU_MGMT_FREE	(1 << 0)
+#define DAVINCI_UART_PWREMU_MGMT_URRST	(1 << 13)
+#define DAVINCI_UART_PWREMU_MGMT_UTRST	(1 << 14)
+
+#endif /* CONFIG_SOC_DA8XX */
+
 #endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-davinci/i2c_defs.h b/include/asm-arm/arch-davinci/i2c_defs.h
index 2e902e1..24cd268 100644
--- a/include/asm-arm/arch-davinci/i2c_defs.h
+++ b/include/asm-arm/arch-davinci/i2c_defs.h
@@ -28,7 +28,11 @@
 #define I2C_WRITE		0
 #define I2C_READ		1
 
+#ifndef CONFIG_SOC_DA8XX
 #define I2C_BASE		0x01c21000
+#else
+#define I2C_BASE		0x01c22000
+#endif
 
 #define	I2C_OA			(I2C_BASE + 0x00)
 #define I2C_IE			(I2C_BASE + 0x04)
@@ -88,6 +92,7 @@
 #define I2C_CON_XA	(1 << 8)	/* Expand address */
 #define I2C_CON_STP	(1 << 11)	/* Stop condition (master mode only) */
 #define I2C_CON_STT	(1 << 13)	/* Start condition (master mode only) */
+#define I2C_CON_FREE	(1 << 14)	/* Free run on emulation */
 
 #define I2C_TIMEOUT	0xffff0000	/* Timeout mask for poll_i2c_irq() */
 

[U-Boot] [PATCH V5 1/4] add TI DA8xx support: DA8xx includes

[Paulraj, Sandeep]

> 
> Provides initial support for TI OMAP-L1x/DA8xx SoC devices.
> See http://www.ti.com
> 
> The DA8xx devices are similar to DaVinci devices but have a differing
> memory map and updated peripheral versions.
> 
> Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
> ---
> Applies to u-boot-ti
> 
>  include/asm-arm/arch-davinci/hardware.h |  237
> +++++++++++++++++++++++++++++++
>  include/asm-arm/arch-davinci/i2c_defs.h |    5 +
>  2 files changed, 242 insertions(+), 0 deletions(-)



Pushed to u-boot-ti/master

http://git.denx.de/?p=u-boot/u-boot-ti.git;a=commit;h=32c39e2da8483093dea29858a234ab2ec54e75bd

modified the patch header a little.

Thanks,
Sandeep

[U-Boot] [PATCH V5 1/4] add TI DA8xx support: DA8xx includes

[Wolfgang Denk]

Dear Nick Thompson,

In message <4AF9823C.8090803@gefanuc.com> you wrote:
> Provides initial support for TI OMAP-L1x/DA8xx SoC devices.
> See http://www.ti.com
> 
> The DA8xx devices are similar to DaVinci devices but have a differing
> memory map and updated peripheral versions.
> 
> Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
...
> +enum davinci_lpsc_ids {
> +	DAVINCI_LPSC_TPCC = 0,
> +	DAVINCI_LPSC_TPTC0,
> +	DAVINCI_LPSC_TPTC1,
> +	DAVINCI_LPSC_AEMIF,
> +	DAVINCI_LPSC_SPI0,
> +	DAVINCI_LPSC_MMC_SD,
> +	DAVINCI_LPSC_AINTC,
> +	DAVINCI_LPSC_ARM_RAM_ROM,
> +	DAVINCI_LPSC_SECCTL_KEYMGR,
> +	DAVINCI_LPSC_UART0,
> +	DAVINCI_LPSC_SCR0,
> +	DAVINCI_LPSC_SCR1,
> +	DAVINCI_LPSC_SCR2,
> +	DAVINCI_LPSC_DMAX,
> +	DAVINCI_LPSC_ARM,
> +	DAVINCI_LPSC_GEM,
> +	/* for LPSCs in PSC1, offset from 32 for differentiation */
> +	DAVINCI_LPSC_PSC1_BASE = 32,
> +	DAVINCI_LPSC_USB11,
> +	DAVINCI_LPSC_USB20,
> +	DAVINCI_LPSC_GPIO,
> +	DAVINCI_LPSC_UHPI,
> +	DAVINCI_LPSC_EMAC,
> +	DAVINCI_LPSC_DDR_EMIF,
> +	DAVINCI_LPSC_McASP0,
> +	DAVINCI_LPSC_McASP1,
> +	DAVINCI_LPSC_McASP2,
> +	DAVINCI_LPSC_SPI1,
> +	DAVINCI_LPSC_I2C1,
> +	DAVINCI_LPSC_UART1,
> +	DAVINCI_LPSC_UART2,
> +	DAVINCI_LPSC_LCDC,
> +	DAVINCI_LPSC_ePWM,
> +	DAVINCI_LPSC_eCAP,
> +	DAVINCI_LPSC_eQEP,
> +	DAVINCI_LPSC_SCR_P0,
> +	DAVINCI_LPSC_SCR_P1,
> +	DAVINCI_LPSC_CR_P3,
> +	DAVINCI_LPSC_L3_CBA_RAM
> +};

Variable names must be lower case. Please fix.

Also, it is good tradition to ad a comma to the last entry, too.


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Given a choice between two theories, take the one which is funnier.

[U-Boot] [PATCH V5 1/4] add TI DA8xx support: DA8xx includes

[Wolfgang Denk]

Dear "Paulraj, Sandeep",

In message <0554BEF07D437848AF01B9C9B5F0BC5D93F2F002@dlee01.ent.ti.com> you wrote:
> 
> > 
> > Provides initial support for TI OMAP-L1x/DA8xx SoC devices.
> > See http://www.ti.com
> > 
> > The DA8xx devices are similar to DaVinci devices but have a differing
> > memory map and updated peripheral versions.
> > 
> > Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
> > Signed-off-by: Sekhar Nori <nsekhar@ti.com>
> > ---
> > Applies to u-boot-ti
> > 
> >  include/asm-arm/arch-davinci/hardware.h |  237
> > +++++++++++++++++++++++++++++++
> >  include/asm-arm/arch-davinci/i2c_defs.h |    5 +
> >  2 files changed, 242 insertions(+), 0 deletions(-)
> 
> 
> 
> Pushed to u-boot-ti/master
> 
> http://git.denx.de/?p=u-boot/u-boot-ti.git;a=commit;h=32c39e2da8483093dea29858a234ab2ec54e75bd
> 
> modified the patch header a little.

Argh...

Please do not push stuff to the master branch of the poublic
repository so quickly. Please allow for a few days reviewing first.

I just NAKed this patch.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"I think they're going to take all this money that we  spend  now  on
war and death --"                   "And make them spend it on life."
	-- Edith Keeler and Kirk, "The City on the Edge of Forever",
	   stardate unknown.

[U-Boot] [PATCH V5 1/4] add TI DA8xx support: DA8xx includes

[Paulraj, Sandeep]

> Dear "Paulraj, Sandeep",
> 
> In message <0554BEF07D437848AF01B9C9B5F0BC5D93F2F002@dlee01.ent.ti.com>
> you wrote:
> >
> > >
> > > Provides initial support for TI OMAP-L1x/DA8xx SoC devices.
> > > See http://www.ti.com
> > >
> > > The DA8xx devices are similar to DaVinci devices but have a differing
> > > memory map and updated peripheral versions.
> > >
> > > Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
> > > Signed-off-by: Sekhar Nori <nsekhar@ti.com>
> > > ---
> > > Applies to u-boot-ti
> > >
> > >  include/asm-arm/arch-davinci/hardware.h |  237
> > > +++++++++++++++++++++++++++++++
> > >  include/asm-arm/arch-davinci/i2c_defs.h |    5 +
> > >  2 files changed, 242 insertions(+), 0 deletions(-)
> >
> >
> >
> > Pushed to u-boot-ti/master
> >
> > http://git.denx.de/?p=u-boot/u-boot-
> ti.git;a=commit;h=32c39e2da8483093dea29858a234ab2ec54e75bd
> >
> > modified the patch header a little.
> 
> Argh...
> 
> Please do not push stuff to the master branch of the poublic
> repository so quickly. Please allow for a few days reviewing first.
> 
> I just NAKed this patch.

Fine no issues with the NAK.

But this set is being discussed for a fortnight. There's a v5 in the patch header.

> 
> Best regards,
> 
> Wolfgang Denk
> 
> --
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
> "I think they're going to take all this money that we  spend  now  on
> war and death --"                   "And make them spend it on life."
> 	-- Edith Keeler and Kirk, "The City on the Edge of Forever",
> 	   stardate unknown.

[U-Boot] [PATCH V5 1/4] add TI DA8xx support: DA8xx includes

[Nick Thompson]

On 17/11/09 23:10, Wolfgang Denk wrote:
> Dear "Paulraj, Sandeep",
> 
> In message <0554BEF07D437848AF01B9C9B5F0BC5D93F2F002@dlee01.ent.ti.com> you wrote:
>>
>>>
>>> Provides initial support for TI OMAP-L1x/DA8xx SoC devices.
>>> See http://www.ti.com
>>>
>>> The DA8xx devices are similar to DaVinci devices but have a differing
>>> memory map and updated peripheral versions.
>>>
>>> Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
>>> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
>>> ---
>>> Applies to u-boot-ti
>>>
>>>  include/asm-arm/arch-davinci/hardware.h |  237
>>> +++++++++++++++++++++++++++++++
>>>  include/asm-arm/arch-davinci/i2c_defs.h |    5 +
>>>  2 files changed, 242 insertions(+), 0 deletions(-)
>>
>>
>>
>> Pushed to u-boot-ti/master
>>
>> http://git.denx.de/?p=u-boot/u-boot-ti.git;a=commit;h=32c39e2da8483093dea29858a234ab2ec54e75bd
>>
>> modified the patch header a little.
> 
> Argh...
> 
> Please do not push stuff to the master branch of the poublic
> repository so quickly. Please allow for a few days reviewing first.
> 
> I just NAKed this patch.

Wolfgang,

I'm happy to submit a new patch to lowercase these enums if you
think that would be a good idea. It might be inviting trouble,
but I'm not aware of any outstanding patches that rely on these
values directly.

I'm not thinking of process here, but we can catch if before it
propagates anywhere.

Nick.

[U-Boot] [PATCH V5 1/4] add TI DA8xx support: DA8xx includes

[Scott Wood]

On Wed, Nov 18, 2009 at 12:09:46AM +0100, Wolfgang Denk wrote:
> In message <4AF9823C.8090803@gefanuc.com> you wrote:
> > Provides initial support for TI OMAP-L1x/DA8xx SoC devices.
> > See http://www.ti.com
> > 
> > The DA8xx devices are similar to DaVinci devices but have a differing
> > memory map and updated peripheral versions.
> > 
> > Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
> > Signed-off-by: Sekhar Nori <nsekhar@ti.com>
> ...
> > +enum davinci_lpsc_ids {
> > +	DAVINCI_LPSC_TPCC = 0,
> > +	DAVINCI_LPSC_TPTC0,
> > +	DAVINCI_LPSC_TPTC1,
> > +	DAVINCI_LPSC_AEMIF,
> > +	DAVINCI_LPSC_SPI0,
> > +	DAVINCI_LPSC_MMC_SD,
[snip]
> > +	DAVINCI_LPSC_eQEP,
> > +	DAVINCI_LPSC_SCR_P0,
> > +	DAVINCI_LPSC_SCR_P1,
> > +	DAVINCI_LPSC_CR_P3,
> > +	DAVINCI_LPSC_L3_CBA_RAM
> > +};
> 
> Variable names must be lower case. Please fix.

I suspect the compiler would take issue if you tried to vary those
constants...

-Scott

[U-Boot] [PATCH V5 1/4] add TI DA8xx support: DA8xx includes

[Wolfgang Denk]

Dear Nick Thompson,

In message <4B03BD0C.7080803@gefanuc.com> you wrote:
>
> I'm happy to submit a new patch to lowercase these enums if you
> think that would be a good idea. It might be inviting trouble,
> but I'm not aware of any outstanding patches that rely on these
> values directly.

I'm sorry, but I was actually wrong here. I missed the fact that it
was an enum. And the "CodingStyle" says: "Names of macros defining
constants and labels in enums are capitalized.'

Sorry, my fault. I hereby withdraw my complaint and apologize for not
being more careful.

Best regards,

Wolfgang Denk

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