From mboxrd@z Thu Jan 1 00:00:00 1970 From: Scott Wood Date: Tue, 1 Dec 2009 16:53:03 -0600 Subject: [U-Boot] [PATCH] NAND: DaVinci: Update 4 bit ECC correction In-Reply-To: <1259706299-10213-1-git-send-email-s-paulraj@ti.com> References: <1259706299-10213-1-git-send-email-s-paulraj@ti.com> Message-ID: <20091201225303.GA19467@loki.buserror.net> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Tue, Dec 01, 2009 at 05:24:59PM -0500, s-paulraj at ti.com wrote: > From: Sandeep Paulraj > > There was a bug in the 4 bit ECC calculation routine > in the DaVinci NAND driver. This becomes prominent > when we use 4K page size NAND devices. > This is a fix for the issue. > > Signed-off-by: Sandeep Paulraj > --- > drivers/mtd/nand/davinci_nand.c | 11 +++++++++++ > 1 files changed, 11 insertions(+), 0 deletions(-) > > diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c > index 41a9568..68a0e15 100644 > --- a/drivers/mtd/nand/davinci_nand.c > +++ b/drivers/mtd/nand/davinci_nand.c > @@ -388,6 +388,17 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat, > emif_regs->NANDFCR |= 1 << 13; > > /* > + * ECC_STATE in NANDFSR register reads 0x3 (Error correction complete) > + * immediately after setting the 4BITECC_ADD_CALC_START bit. So if we > + * begin trying to poll for the state, we may fall right out of your > + * loop "your" loop? > without any of the correction calculations having taken place. > + * So wait till ECC_STATE reads less than 4. > + */ > + do { > + val = ((emif_regs->NANDFSR >> 8) & 0xf); > + } while (val < 4); Comment says wait until less than 4, code says wait until@least 4. Could symbolic constants be used to describe the states instead of magic numbers like 4 and 0xc00? Is it possible that there could be a race, whereby the hardware finishes before you read NANDFSR for the first time, and thus you never see it be greater than 3? -Scott