From mboxrd@z Thu Jan 1 00:00:00 1970 From: Scott Wood Date: Fri, 15 Jan 2010 17:13:28 -0600 Subject: [U-Boot] [PATCH 3/9] Add v1.1 support to nand_spl fsl nfc driver In-Reply-To: <1263357841-5100-4-git-send-email-jcrigby@gmail.com> References: <1263357841-5100-1-git-send-email-jcrigby@gmail.com> <1263357841-5100-2-git-send-email-jcrigby@gmail.com> <1263357841-5100-3-git-send-email-jcrigby@gmail.com> <1263357841-5100-4-git-send-email-jcrigby@gmail.com> Message-ID: <20100115231328.GA2956@loki.buserror.net> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Tue, Jan 12, 2010 at 09:43:55PM -0700, John Rigby wrote: > struct fsl_nfc_regs { > - u32 main_area0[128]; /* @0x000 */ > - u32 main_area1[128]; > - u32 main_area2[128]; > - u32 main_area3[128]; > - u32 spare_area0[4]; > - u32 spare_area1[4]; > - u32 spare_area2[4]; > - u32 spare_area3[4]; > - u32 reserved1[64 - 16 + 64 * 5]; > - u16 bufsiz; /* @ 0xe00 */ > + u8 main_area[NAND_MXC_NR_BUFS][512]; > + u8 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE]; You could do u32 ...[NAND_MXC_SPARE_BUF_SIZE / 4] to avoid the casts later on... > diff --git a/nand_spl/nand_boot_fsl_nfc.c b/nand_spl/nand_boot_fsl_nfc.c > index a9df2a8..02d8330 100644 > --- a/nand_spl/nand_boot_fsl_nfc.c > +++ b/nand_spl/nand_boot_fsl_nfc.c > @@ -26,13 +26,17 @@ > > #include > #include > +#ifdef CONFIG_MX31 > #include > +#else > +#include > +#endif Hmm, can't this be pushed into an arch header? > #include > #include > > -static struct fsl_nfc_regs *nfc; > +struct fsl_nfc_regs *nfc; > > -static void nfc_wait_ready(void) > +void nfc_wait_ready(void) Why non-static? > @@ -65,12 +91,12 @@ static void nfc_nand_page_address(unsigned int page_address) > { > unsigned int page_count; > > - writew(0x00, &nfc->flash_cmd); > + writew(0x00, &nfc->flash_add); > writew(NFC_ADDR, &nfc->nand_flash_config2); > nfc_wait_ready(); > > - /* code only for 2kb flash */ > - if (CONFIG_SYS_NAND_PAGE_SIZE == 0x800) { > + /* code only for large page flash */ > + if (CONFIG_SYS_NAND_PAGE_SIZE > 512) { > writew(0x00, &nfc->flash_add); > writew(NFC_ADDR, &nfc->nand_flash_config2); > nfc_wait_ready(); > @@ -88,22 +114,38 @@ static void nfc_nand_page_address(unsigned int page_address) > page_count = page_count >> 8; > } while (page_count); > } > + > + writew(0x00, &nfc->flash_add); > + writew(NFC_ADDR, &nfc->nand_flash_config2); > + nfc_wait_ready(); This (along with later bits) looks like it changes the behavior for existing chips. Have you tested it on a previously-supported chip? Maybe elaborate on the changes in the commit message. -Scott