* [U-Boot] [PATCH 3/3] Add support for EDB93XX boards
@ 2009-12-23 19:26 Matthias Kaehlcke
0 siblings, 0 replies; 12+ messages in thread
From: Matthias Kaehlcke @ 2009-12-23 19:26 UTC (permalink / raw)
To: u-boot
Added support for the following EDB93XX boards:
EDB9301
EDB9302
EDB9302A
EDB9307
EDB9307A
EDB93012
EDB9315
EDB9315A
Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
---
MAINTAINERS | 10 ++
MAKEALL | 8 ++
Makefile | 10 ++
board/edb93xx/Makefile | 50 ++++++++
board/edb93xx/config.mk | 33 ++++++
board/edb93xx/early_udelay.h | 34 ++++++
board/edb93xx/edb93xx.c | 110 ++++++++++++++++++
board/edb93xx/flash_cfg.c | 38 ++++++
board/edb93xx/pll_cfg.c | 58 ++++++++++
board/edb93xx/pll_cfg.h | 72 ++++++++++++
board/edb93xx/sdram_cfg.c | 123 ++++++++++++++++++++
board/edb93xx/sdram_cfg.h | 144 +++++++++++++++++++++++
include/configs/edb93xx.h | 257 ++++++++++++++++++++++++++++++++++++++++++
13 files changed, 947 insertions(+), 0 deletions(-)
create mode 100644 board/edb93xx/Makefile
create mode 100644 board/edb93xx/config.mk
create mode 100644 board/edb93xx/early_udelay.h
create mode 100644 board/edb93xx/edb93xx.c
create mode 100644 board/edb93xx/flash_cfg.c
create mode 100644 board/edb93xx/pll_cfg.c
create mode 100644 board/edb93xx/pll_cfg.h
create mode 100644 board/edb93xx/sdram_cfg.c
create mode 100644 board/edb93xx/sdram_cfg.h
create mode 100644 include/configs/edb93xx.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 9734b1d..b84ce4a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -597,6 +597,16 @@ Gary Jennejohn <garyj@denx.de>
smdk2400 ARM920T
trab ARM920T
+Matthias Kaehlcke <matthias@kaehlcke.net>
+ edb9301 ARM920T (EP9301)
+ edb9302 ARM920T (EP9302)
+ edb9302a ARM920T (EP9302)
+ edb9307 ARM920T (EP9307)
+ edb9307a ARM920T (EP9307)
+ edb9312 ARM920T (EP9312)
+ edb9315 ARM920T (EP9315)
+ edb9315a ARM920T (EP9315)
+
Konstantin Kletschke <kletschke@synertronixx.de>
scb9328 ARM920T
diff --git a/MAKEALL b/MAKEALL
index ab1bb6f..b475707 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -552,6 +552,14 @@ LIST_ARM9=" \
cp946es \
cp966 \
da830evm \
+ edb9301 \
+ edb9302 \
+ edb9302a \
+ edb9307 \
+ edb9307a \
+ edb9312 \
+ edb9315 \
+ edb9315a \
imx27lite \
lpd7a400 \
mv88f6281gtw_ge \
diff --git a/Makefile b/Makefile
index ed6156f..d6f4fa0 100644
--- a/Makefile
+++ b/Makefile
@@ -2399,6 +2399,16 @@ TQM834x_config: unconfig
vme8349_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx vme8349 esd
+edb9301_config \
+edb9302_config \
+edb9302a_config \
+edb9307_config \
+edb9307a_config \
+edb9312_config \
+edb9315_config \
+edb9315a_config: unconfig
+ @$(MKCONFIG) -t $(@:_config=) edb93xx arm arm920t edb93xx NULL ep93xx
+
#########################################################################
## MPC85xx Systems
#########################################################################
diff --git a/board/edb93xx/Makefile b/board/edb93xx/Makefile
new file mode 100644
index 0000000..e2e2636
--- /dev/null
+++ b/board/edb93xx/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := edb93xx.o flash_cfg.o pll_cfg.o sdram_cfg.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/edb93xx/config.mk b/board/edb93xx/config.mk
new file mode 100644
index 0000000..b2fc6fa
--- /dev/null
+++ b/board/edb93xx/config.mk
@@ -0,0 +1,33 @@
+LDSCRIPT := $(SRCTREE)/cpu/arm920t/ep93xx/u-boot.lds
+
+ifdef CONFIG_EDB9301
+TEXT_BASE = 0x05700000
+endif
+
+ifdef CONFIG_EDB9302
+TEXT_BASE = 0x05700000
+endif
+
+ifdef CONFIG_EDB9302A
+TEXT_BASE = 0xc5700000
+endif
+
+ifdef CONFIG_EDB9307
+TEXT_BASE = 0x01f00000
+endif
+
+ifdef CONFIG_EDB9307A
+TEXT_BASE = 0xc1f00000
+endif
+
+ifdef CONFIG_EDB9312
+TEXT_BASE = 0x01f00000
+endif
+
+ifdef CONFIG_EDB9315
+TEXT_BASE = 0x01f00000
+endif
+
+ifdef CONFIG_EDB9315A
+TEXT_BASE = 0xc1f00000
+endif
diff --git a/board/edb93xx/early_udelay.h b/board/edb93xx/early_udelay.h
new file mode 100644
index 0000000..3b26b3f
--- /dev/null
+++ b/board/edb93xx/early_udelay.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* delay execution before timers are initialized */
+static inline void early_udelay(uint32_t usecs)
+{
+ /* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */
+ register uint32_t loops = (usecs * 1000) / 20;
+
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0" (loops));
+}
diff --git a/board/edb93xx/edb93xx.c b/board/edb93xx/edb93xx.c
new file mode 100644
index 0000000..42b9413
--- /dev/null
+++ b/board/edb93xx/edb93xx.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * (C) Copyright 2002 2003
+ * Network Audio Technologies, Inc. <www.netaudiotech.com>
+ * Adam Bezanson <bezanson@netaudiotech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+
+#define MAX_BANK_SIZE 0x04000000 /* 64 MB */
+
+static ulong const bank_addr[CONFIG_NR_DRAM_BANKS] = {
+ PHYS_SDRAM_1,
+#ifdef PHYS_SDRAM_2
+ PHYS_SDRAM_2,
+#endif
+#ifdef PHYS_SDRAM_3
+ PHYS_SDRAM_3,
+#endif
+#ifdef PHYS_SDRAM_4
+ PHYS_SDRAM_4
+#endif
+};
+
+int board_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+ icache_enable();
+
+#ifdef USE_920T_MMU
+ dcache_enable();
+#endif
+
+ /*
+ * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of
+ * 14.7456/2 MHz
+ */
+ uint32_t value = readl(&syscon->pwrcnt);
+ value |= SYSCON_PWRCNT_UART_BAUD;
+ writel(value, &syscon->pwrcnt);
+
+ /* Machine number, as defined in linux/arch/arm/tools/mach-types */
+ gd->bd->bi_arch_number = MACH_TYPE;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+ /* We have a console */
+ gd->have_console = 1;
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+ ep93xx_eth_init(bd);
+}
+
+int dram_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ unsigned int *src, *dst;
+ int i;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ const ulong bank_size = get_ram_size((long *)bank_addr[i],
+ MAX_BANK_SIZE);
+ if (bank_size) {
+ gd->bd->bi_dram[i].start = bank_addr[i];
+ gd->bd->bi_dram[i].size = bank_size;
+ }
+ }
+
+#ifdef CONFIG_EDB93XX_SDCS3
+ dst = (unsigned int *)0x00000000;
+#else
+ dst = (unsigned int *)0xc0000000;
+#endif
+
+ /* copy exception vectors */
+ src = (unsigned int *)_armboot_start;
+
+ for (i = 0; i < 16; i++)
+ *dst++ = *src++;
+
+ return 0;
+}
diff --git a/board/edb93xx/flash_cfg.c b/board/edb93xx/flash_cfg.c
new file mode 100644
index 0000000..24ea210
--- /dev/null
+++ b/board/edb93xx/flash_cfg.c
@@ -0,0 +1,38 @@
+/*
+ * Flash setup for Cirrus edb93xx boards
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+
+#define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \
+ SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \
+ 1 << SMC_BCR_MW_SHIFT)
+
+void flash_cfg(void)
+{
+ struct smc_regs *smc = (struct smc_regs *)SMC_BASE;
+
+ writel(SMC_BCR6_VALUE, &smc->bcr6);
+}
diff --git a/board/edb93xx/pll_cfg.c b/board/edb93xx/pll_cfg.c
new file mode 100644
index 0000000..a687af0
--- /dev/null
+++ b/board/edb93xx/pll_cfg.c
@@ -0,0 +1,58 @@
+/*
+ * PLL setup for Cirrus edb93xx boards
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include "pll_cfg.h"
+#include "early_udelay.h"
+
+void pll_cfg(void)
+{
+ struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+ /* setup PLL1 */
+ writel(CLKSET1_VAL, &syscon->clkset1);
+
+ /*
+ * flush the pipeline
+ * writing to CLKSET1 causes the EP93xx to enter standby for between
+ * 8 ms to 16 ms, until PLL1 stabilizes
+ */
+ asm("nop");
+ asm("nop");
+ asm("nop");
+ asm("nop");
+ asm("nop");
+
+ /* setup PLL2 */
+ writel(CLKSET2_VAL, &syscon->clkset2);
+
+ /*
+ * the user's guide recommends to wait at least 1 ms for PLL2 to
+ * stabilize
+ */
+ early_udelay(1000);
+}
diff --git a/board/edb93xx/pll_cfg.h b/board/edb93xx/pll_cfg.h
new file mode 100644
index 0000000..8001e01
--- /dev/null
+++ b/board/edb93xx/pll_cfg.h
@@ -0,0 +1,72 @@
+/*
+ * PLL register values for Cirrus edb93xx boards
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/ep93xx.h>
+
+#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \
+ defined(CONFIG_EDB9302A)
+/*
+ * fclk_div: 2, nbyp1: 1, hclk_div: 5, pclk_div: 2
+ * pll1_x1: 294912000.000000, pll1_x2ip: 36864000.000000,
+ * pll1_x2: 331776000.000000, pll1_out: 331776000.000000
+ */
+#define CLKSET1_VAL (7 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
+ 8 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
+ 19 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
+ 1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \
+ 3 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \
+ SYSCON_CLKSET1_NBYP1 | \
+ 1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT)
+#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) ||\
+ defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) ||\
+ defined(CONFIG_EDB9315A)
+/*
+ * fclk_div: 2, nbyp1: 1, hclk_div: 4, pclk_div: 2
+ * pll1_x1: 3096576000.000000, pll1_x2ip: 129024000.000000,
+ * pll1_x2: 3999744000.000000, pll1_out: 1999872000.000000
+ */
+#define CLKSET1_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
+ 30 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
+ 20 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
+ 1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \
+ 2 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \
+ SYSCON_CLKSET1_NBYP1 | \
+ 1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT)
+#else
+#error "Undefined board"
+#endif
+
+/*
+ * usb_div: 4, nbyp2: 1, pll2_en: 1
+ * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000,
+ * pll2_x2: 384000000.000000, pll2_out: 192000000.000000
+ */
+#define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
+ 24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
+ 24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
+ 1 << SYSCON_CLKSET_PLL_PS_SHIFT | \
+ SYSCON_CLKSET2_PLL2_EN | \
+ SYSCON_CLKSET2_NBYP2 | \
+ 3 << SYSCON_CLKSET2_USB_DIV_SHIFT)
diff --git a/board/edb93xx/sdram_cfg.c b/board/edb93xx/sdram_cfg.c
new file mode 100644
index 0000000..6fc6832
--- /dev/null
+++ b/board/edb93xx/sdram_cfg.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/io.h>
+#include "sdram_cfg.h"
+#include "early_udelay.h"
+
+#define PROGRAM_MODE_REG(bank) (*(volatile uint32_t *) \
+ (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank | SDRAM_MODE_REG_VAL))
+
+#define PRECHARGE_BANK(bank) (*(volatile uint32_t *) \
+ (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank))
+
+static void force_precharge(void);
+static void setup_refresh_timer(void);
+static void program_mode_registers(void);
+
+void sdram_cfg(void)
+{
+ struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
+
+ writel(SDRAM_DEVCFG_VAL, &sdram->SDRAM_DEVCFG_REG);
+
+ /* Issue continous NOP commands */
+ writel(GLCONFIG_INIT | GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig);
+
+ early_udelay(200);
+
+ force_precharge();
+
+ setup_refresh_timer();
+
+ program_mode_registers();
+
+ /* Select normal operation mode */
+ writel(GLCONFIG_CKE, &sdram->glconfig);
+}
+
+#if defined(CONFIG_EP9301) || defined(CONFIG_EP9302)
+static void force_precharge(void)
+{
+ /*
+ * Errata for EP9301/2 rev. E0 says that PRECHARGE ALL isn't always
+ * issued.
+ * Do a read from each bank to make sure they're precharged
+ * Logical address bits A[22:21] map to BA[1:0] (SROMLL is set)
+ * The errata further says that this isn't going to be fixed,
+ * therefore do it for all revisions
+ */
+
+ PRECHARGE_BANK(0);
+ PRECHARGE_BANK(1);
+ PRECHARGE_BANK(2);
+ PRECHARGE_BANK(3);
+}
+#else
+static void force_precharge(void) {}
+#endif
+
+static void setup_refresh_timer(void)
+{
+ struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
+
+ /* Load refresh timer with 10 to issue refresh every 10 cycles */
+ writel(0x0a, &sdram->refrshtimr);
+
+ /*
+ * Wait at least 80 clock cycles to provide 8 refresh cycles
+ * to all SDRAMs
+ */
+ early_udelay(1);
+
+ /*
+ * Program refresh timer with normal value
+ * We need 8192 refresh cycles every 64ms
+ * at 15ns (HCLK >= 66MHz) per cycle:
+ * 64ms / 8192 = 7.8125us
+ * 7.8125us / 15ns = 520 (0x208)
+ */
+ /*
+ * TODO: redboot uses 0x1e0 for the slowest possible device
+ * but i don't understand how this value is calculated
+ */
+ writel(0x208, &sdram->refrshtimr);
+}
+
+static void program_mode_registers(void)
+{
+ PROGRAM_MODE_REG(0);
+
+#if (CONFIG_NR_DRAM_BANKS >= 2)
+ PROGRAM_MODE_REG(1);
+#endif
+
+#if (CONFIG_NR_DRAM_BANKS >= 3)
+ PROGRAM_MODE_REG(2);
+#endif
+
+#if (CONFIG_NR_DRAM_BANKS == 4)
+ PROGRAM_MODE_REG(3);
+#endif
+}
diff --git a/board/edb93xx/sdram_cfg.h b/board/edb93xx/sdram_cfg.h
new file mode 100644
index 0000000..983ff83
--- /dev/null
+++ b/board/edb93xx/sdram_cfg.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/ep93xx.h>
+
+#define SDRAM_BASE_ADDR PHYS_SDRAM_1
+
+#ifdef CONFIG_EDB93XX_SDCS0
+#define SDRAM_DEVCFG_REG devcfg0
+#elif defined(CONFIG_EDB93XX_SDCS3)
+#define SDRAM_DEVCFG_REG devcfg3
+#else
+#error "SDRAM bank configuration"
+#endif
+
+#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) ||\
+ defined(CONFIG_EDB9302A)
+/*
+ * 1x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM
+ *
+ * CLK cycle time min:
+ * @ CAS latency = 3: 7.5ns
+ * @ CAS latency = 2: 10ns
+ * We're running at 66MHz (15ns cycle time) external bus speed (HCLK),
+ * so it's safe to use CAS latency = 2
+ *
+ * RAS-to-CAS delay min:
+ * 20ns
+ * At 15ns cycle time, we use RAS-to-CAS delay = 2
+ *
+ * SROMLL = 1: Swap BA[1:0] with A[13:12], making the SDRAM appear
+ * as four blocks of 8MB size, instead of eight blocks of 4MB size:
+ *
+ * EDB9301/EDB9302:
+ *
+ * 0x00000000 - 0x007fffff
+ * 0x01000000 - 0x017fffff
+ * 0x04000000 - 0x047fffff
+ * 0x05000000 - 0x057fffff
+ *
+ *
+ * EDB9302a:
+ *
+ * 0xc0000000 - 0xc07fffff
+ * 0xc1000000 - 0xc17fffff
+ * 0xc4000000 - 0xc47fffff
+ * 0xc5000000 - 0xc57fffff
+ *
+ * BANKCOUNT = 1: This is a device with four banks
+ */
+
+#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT | \
+ SDRAM_DEVCFG_SROMLL | \
+ SDRAM_DEVCFG_CASLAT_2 | \
+ SDRAM_DEVCFG_RASTOCAS_2 | \
+ SDRAM_DEVCFG_EXTBUSWIDTH)
+
+/*
+ * 16 bit ext. bus
+ *
+ * A[22:09] is output as SYA[13:0]
+ * CAS latency: 2
+ * Burst type: sequential
+ * Burst length: 8 (required for 16 bit ext. bus)
+ * SYA[13:0] = 0x0023
+ */
+#define SDRAM_MODE_REG_VAL 0x4600
+
+#define SDRAM_BANK_SEL_0 0x00000000 /* A[22:21] = b00 */
+#define SDRAM_BANK_SEL_1 0x00200000 /* A[22:21] = b01 */
+#define SDRAM_BANK_SEL_2 0x00400000 /* A[22:21] = b10 */
+#define SDRAM_BANK_SEL_3 0x00600000 /* A[22:21] = b11 */
+
+#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) ||\
+ defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) ||\
+ defined(CONFIG_EDB9315A)
+/*
+ * 2x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM
+ *
+ * CLK cycle time min:
+ * @ CAS latency = 3: 7.5ns
+ * @ CAS latency = 2: 10ns
+ * We're running at 100MHz (10ns cycle time) external bus speed (HCLK),
+ * so it's safe to use CAS latency = 2
+ *
+ * RAS-to-CAS delay min:
+ * 20ns
+ * At 10ns cycle time, we use RAS-to-CAS delay = 2
+ *
+ * EDB9307, EDB9312, EDB9315:
+ *
+ * 0x00000000 - 0x01ffffff
+ * 0x04000000 - 0x05ffffff
+ *
+ *
+ * EDB9307a, EDB9315a:
+ *
+ * 0xc0000000 - 0xc1ffffff
+ * 0xc4000000 - 0xc5ffffff
+ */
+
+#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT | \
+ SDRAM_DEVCFG_SROMLL | \
+ SDRAM_DEVCFG_CASLAT_2 | \
+ SDRAM_DEVCFG_RASTOCAS_2)
+
+/*
+ * 32 bit ext. bus
+ *
+ * A[23:10] is output as SYA[13:0]
+ * CAS latency: 2
+ * Burst type: sequential
+ * Burst length: 4
+ * SYA[13:0] = 0x0022
+ */
+#define SDRAM_MODE_REG_VAL 0x8800
+
+#define SDRAM_BANK_SEL_0 0x00000000 /* A[23:22] = b00 */
+#define SDRAM_BANK_SEL_1 0x00400000 /* A[23:22] = b01 */
+#define SDRAM_BANK_SEL_2 0x00800000 /* A[23:22] = b10 */
+#define SDRAM_BANK_SEL_3 0x00c00000 /* A[23:22] = b11 */
+#endif
diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h
new file mode 100644
index 0000000..0968c7d
--- /dev/null
+++ b/include/configs/edb93xx.h
@@ -0,0 +1,257 @@
+/*
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_MK_edb9301
+#define CONFIG_EDB9301
+#elif defined(CONFIG_MK_edb9302)
+#define CONFIG_EDB9302
+#elif defined(CONFIG_MK_edb9302a)
+#define CONFIG_EDB9302A
+#elif defined(CONFIG_MK_edb9307)
+#define CONFIG_EDB9307
+#elif defined(CONFIG_MK_edb9307a)
+#define CONFIG_EDB9307A
+#elif defined(CONFIG_MK_edb9312)
+#define CONFIG_EDB9312
+#elif defined(CONFIG_MK_edb9315)
+#define CONFIG_EDB9315
+#elif defined(CONFIG_MK_edb9315a)
+#define CONFIG_EDB9315A
+#else
+#error "no board defined"
+#endif
+
+/* Initial environment and monitor configuration options. */
+#define CONFIG_BOOTDELAY 2
+#define CONFIG_CMDLINE_TAG 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_BOOTARGS "root=/dev/nfs console=ttyAM0,115200 ip=dhcp"
+#define CONFIG_BOOTFILE "edb93xx.img"
+
+#define CONFIG_SYS_HUSH_PARSER 1
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#ifdef CONFIG_EDB9301
+#define CONFIG_EP9301
+#define MACH_TYPE MACH_TYPE_EDB9301
+#define CONFIG_SYS_PROMPT "EDB9301> "
+#define CONFIG_ENV_SECT_SIZE 0x00020000
+#elif defined(CONFIG_EDB9302)
+#define CONFIG_EP9302
+#define MACH_TYPE MACH_TYPE_EDB9302
+#define CONFIG_SYS_PROMPT "EDB9302> "
+#define CONFIG_ENV_SECT_SIZE 0x00020000
+#elif defined(CONFIG_EDB9302A)
+#define CONFIG_EP9302
+#define MACH_TYPE MACH_TYPE_EDB9302A
+#define CONFIG_SYS_PROMPT "EDB9302A> "
+#define CONFIG_ENV_SECT_SIZE 0x00020000
+#elif defined(CONFIG_EDB9307)
+#define CONFIG_EP9307
+#define MACH_TYPE MACH_TYPE_EDB9307
+#define CONFIG_SYS_PROMPT "EDB9307> "
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#elif defined(CONFIG_EDB9307A)
+#define CONFIG_EP9307
+#define MACH_TYPE MACH_TYPE_EDB9307A
+#define CONFIG_SYS_PROMPT "EDB9307A> "
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#elif defined(CONFIG_EDB9312)
+#define CONFIG_EP9312
+#define MACH_TYPE MACH_TYPE_EDB9312
+#define CONFIG_SYS_PROMPT "EDB9312> "
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#elif defined(CONFIG_EDB9315)
+#define CONFIG_EP9315
+#define MACH_TYPE MACH_TYPE_EDB9315
+#define CONFIG_SYS_PROMPT "EDB9315> "
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#elif defined(CONFIG_EDB9315A)
+#define CONFIG_EP9315
+#define MACH_TYPE MACH_TYPE_EDB9315A
+#define CONFIG_SYS_PROMPT "EDB9315A> "
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#else
+#error "no board defined"
+#endif
+
+/* High-level configuration options */
+#define CONFIG_ARM920T 1 /* This is an ARM920T core... */
+#define CONFIG_EP93XX 1 /* in a Cirrus Logic 93xx SoC */
+
+#define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456 clock */
+#define CONFIG_SYS_HZ 1000 /* decr freq: 1 ms ticks */
+#undef CONFIG_USE_IRQ /* Don't need IRQ/FIQ */
+
+/* Monitor configuration */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#undef CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+
+#define CONFIG_SYS_LONGHELP /* Enable "long" help in mon */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
+/* Print buffer size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+/* Boot argument buffer size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
+
+/* Serial port hardware configuration */
+#define CONFIG_PL010_SERIAL
+#define CONFIG_CONS_INDEX 0
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+#define CONFIG_SYS_SERIAL0 0x808C0000
+#define CONFIG_SYS_SERIAL1 0x808D0000
+#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
+ (void *)CONFIG_SYS_SERIAL1}
+
+/* Network hardware configuration */
+#define CONFIG_DRIVER_EP93XX_MAC
+#define CONFIG_MII_SUPPRESS_PREAMBLE
+#define CONFIG_MII
+#define CONFIG_PHY_ADDR 1
+#define CONFIG_NET_MULTI
+#undef CONFIG_NETCONSOLE
+
+
+/* SDRAM configuration */
+#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302)
+/*
+ * EDB9301/2 has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
+ * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
+ * the SROMLL bit on the processor, resulting in this non-contiguous memory map.
+ */
+#define CONFIG_NR_DRAM_BANKS 4
+#define PHYS_SDRAM_1 0x00000000
+#define PHYS_SDRAM_SIZE_1 0x00800000
+#define PHYS_SDRAM_2 0x01000000
+#define PHYS_SDRAM_SIZE_2 0x00800000
+#define PHYS_SDRAM_3 0x04000000
+#define PHYS_SDRAM_SIZE_3 0x00800000
+#define PHYS_SDRAM_4 0x05000000
+#define PHYS_SDRAM_SIZE_4 0x00800000
+#define CONFIG_EDB93XX_SDCS3
+#define CONFIG_SYS_MEMTEST_START 0x00100000
+#define CONFIG_SYS_MEMTEST_END 0x007fffff
+
+#elif defined(CONFIG_EDB9302A)
+/*
+ * EDB9302a has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
+ * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
+ * the SROMLL bit on the processor, resulting in this non-contiguous memory map.
+ */
+#define CONFIG_NR_DRAM_BANKS 4
+#define PHYS_SDRAM_1 0xc0000000
+#define PHYS_SDRAM_SIZE_1 0x00800000
+#define PHYS_SDRAM_2 0xc1000000
+#define PHYS_SDRAM_SIZE_2 0x00800000
+#define PHYS_SDRAM_3 0xc4000000
+#define PHYS_SDRAM_SIZE_3 0x00800000
+#define PHYS_SDRAM_4 0xc5000000
+#define PHYS_SDRAM_SIZE_4 0x00800000
+#define CONFIG_EDB93XX_SDCS0
+#define CONFIG_SYS_MEMTEST_START 0xc0100000
+#define CONFIG_SYS_MEMTEST_END 0xc07fffff
+
+#elif defined(CONFIG_EDB9307) || defined CONFIG_EDB9312 || \
+ defined(CONFIG_EDB9315)
+/*
+ * The EDB9307, EDB9312, and EDB9315 have 2 banks of SDRAM consisting of
+ * 2x Samsung K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of
+ * 64 MB of SDRAM.
+ */
+#define CONFIG_NR_DRAM_BANKS 2
+#define PHYS_SDRAM_1 0x00000000
+#define PHYS_SDRAM_SIZE_1 0x02000000
+#define PHYS_SDRAM_2 0x04000000
+#define PHYS_SDRAM_SIZE_2 0x02000000
+#define CONFIG_EDB93XX_SDCS3
+#define CONFIG_SYS_MEMTEST_START 0x00100000
+#define CONFIG_SYS_MEMTEST_END 0x01e00000
+
+#elif defined(CONFIG_EDB9307A) || defined(CONFIG_EDB9315A)
+/*
+ * The EDB9307A and EDB9315A have 2 banks of SDRAM consisting of 2x Samsung
+ * K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of 64 MB of SDRAM.
+ */
+#define CONFIG_NR_DRAM_BANKS 2
+#define PHYS_SDRAM_1 0xc0000000
+#define PHYS_SDRAM_SIZE_1 0x02000000
+#define PHYS_SDRAM_2 0xc4000000
+#define PHYS_SDRAM_SIZE_2 0x02000000
+#define CONFIG_EDB93XX_SDCS0
+#define CONFIG_SYS_MEMTEST_START 0xc0100000
+#define CONFIG_SYS_MEMTEST_END 0xc1e00000
+#endif
+
+#if defined(CONFIG_EDB93XX_SDCS3)
+#define CONFIG_SYS_LOAD_ADDR 0x01000000 /* Default load address */
+#elif defined(CONFIG_EDB93XX_SDCS0)
+#define CONFIG_SYS_LOAD_ADDR 0xc1000000 /* Default load address */
+#endif
+
+/* Must match kernel config */
+#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
+
+/* Run-time memory allocatons */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+#define CONFIG_STACKSIZE (128 * 1024)
+
+#if defined(CONFIG_USE_IRQ)
+#define CONFIG_STACKSIZE_IRQ (4 * 1024)
+#define CONFIG_STACKSIZE_FIQ (4 * 1024)
+#endif
+
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
+
+/* -----------------------------------------------------------------------------
+ * FLASH and environment organization
+ *
+ * The EDB9301 and EDB9302(a) have 1 bank of flash memory at 0x60000000
+ * consisting of 1x Intel TE28F128J3C-150 128 Mbit flash on a 16-bit data bus,
+ * for a total of 16 MB of CFI-compatible flash.
+ *
+ * The EDB9307(a), EDB9312, and EDB9315(a) have 1 bank of flash memory at
+ * 0x60000000 consisting of 2x Micron MT28F128J3-12 128 Mbit flash on a 32-bit
+ * data bus, for a total of 32 MB of CFI-compatible flash.
+ *
+ * EDB9301/02(a) EDB9307(a)/12/15(a)
+ * 0x60000000 - 0x0003FFFF u-boot u-boot
+ * 0x60040000 - 0x0005FFFF environment #1 environment #1
+ * 0x60060000 - 0x0007FFFF environment #2 environment #1 (continued)
+ * 0x60080000 - 0x0009FFFF unused environment #2
+ * 0x600A0000 - 0x000BFFFF unused environment #2 (continued)
+ * 0x600C0000 - 0x00FFFFFF unused unused
+ * 0x61000000 - 0x01FFFFFF not present unused
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 128
+
+#define PHYS_FLASH_1 0x60000000
+#define CONFIG_SYS_FLASH_BASE (PHYS_FLASH_1)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+
+#define CONFIG_ENV_OVERWRITE /* Vendor params unprotected */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR 0x60040000
+
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+#endif /* !defined (__CONFIG_H) */
--
1.6.3.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH 3/3] Add support for EDB93xx boards
[not found] <cover.1263903884.git.matthias@kaehlcke.net>
@ 2010-01-19 19:16 ` Matthias Kaehlcke
2010-01-19 21:58 ` Wolfgang Denk
0 siblings, 1 reply; 12+ messages in thread
From: Matthias Kaehlcke @ 2010-01-19 19:16 UTC (permalink / raw)
To: u-boot
Added support for the following EDB93xx boards:
EDB9301
EDB9302
EDB9302A
EDB9307
EDB9307A
EDB93012
EDB9315
EDB9315A
Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
---
MAINTAINERS | 10 ++
MAKEALL | 8 ++
Makefile | 10 ++
board/edb93xx/Makefile | 50 ++++++++
board/edb93xx/config.mk | 33 +++++
board/edb93xx/early_udelay.h | 34 +++++
board/edb93xx/edb93xx.c | 111 +++++++++++++++++
board/edb93xx/flash_cfg.c | 38 ++++++
board/edb93xx/pll_cfg.c | 58 +++++++++
board/edb93xx/pll_cfg.h | 72 +++++++++++
board/edb93xx/sdram_cfg.c | 117 ++++++++++++++++++
board/edb93xx/sdram_cfg.h | 144 ++++++++++++++++++++++
include/configs/edb93xx.h | 273 ++++++++++++++++++++++++++++++++++++++++++
13 files changed, 958 insertions(+), 0 deletions(-)
create mode 100644 board/edb93xx/Makefile
create mode 100644 board/edb93xx/config.mk
create mode 100644 board/edb93xx/early_udelay.h
create mode 100644 board/edb93xx/edb93xx.c
create mode 100644 board/edb93xx/flash_cfg.c
create mode 100644 board/edb93xx/pll_cfg.c
create mode 100644 board/edb93xx/pll_cfg.h
create mode 100644 board/edb93xx/sdram_cfg.c
create mode 100644 board/edb93xx/sdram_cfg.h
create mode 100644 include/configs/edb93xx.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 3879fde..23523f3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -598,6 +598,16 @@ Gary Jennejohn <garyj@denx.de>
smdk2400 ARM920T
trab ARM920T
+Matthias Kaehlcke <matthias@kaehlcke.net>
+ edb9301 ARM920T (EP9301)
+ edb9302 ARM920T (EP9302)
+ edb9302a ARM920T (EP9302)
+ edb9307 ARM920T (EP9307)
+ edb9307a ARM920T (EP9307)
+ edb9312 ARM920T (EP9312)
+ edb9315 ARM920T (EP9315)
+ edb9315a ARM920T (EP9315)
+
Konstantin Kletschke <kletschke@synertronixx.de>
scb9328 ARM920T
diff --git a/MAKEALL b/MAKEALL
index dd635bd..c3ef638 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -554,6 +554,14 @@ LIST_ARM9=" \
cp946es \
cp966 \
da830evm \
+ edb9301 \
+ edb9302 \
+ edb9302a \
+ edb9307 \
+ edb9307a \
+ edb9312 \
+ edb9315 \
+ edb9315a \
imx27lite \
lpd7a400 \
mv88f6281gtw_ge \
diff --git a/Makefile b/Makefile
index 793fcec..a1db2f9 100644
--- a/Makefile
+++ b/Makefile
@@ -2404,6 +2404,16 @@ caddy2_config \
vme8349_config: unconfig
@$(MKCONFIG) -t $(@:_config=) vme8349 ppc mpc83xx vme8349 esd
+edb9301_config \
+edb9302_config \
+edb9302a_config \
+edb9307_config \
+edb9307a_config \
+edb9312_config \
+edb9315_config \
+edb9315a_config: unconfig
+ @$(MKCONFIG) -t $(@:_config=) edb93xx arm arm920t edb93xx NULL ep93xx
+
#########################################################################
## MPC85xx Systems
#########################################################################
diff --git a/board/edb93xx/Makefile b/board/edb93xx/Makefile
new file mode 100644
index 0000000..e2e2636
--- /dev/null
+++ b/board/edb93xx/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := edb93xx.o flash_cfg.o pll_cfg.o sdram_cfg.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/edb93xx/config.mk b/board/edb93xx/config.mk
new file mode 100644
index 0000000..b2fc6fa
--- /dev/null
+++ b/board/edb93xx/config.mk
@@ -0,0 +1,33 @@
+LDSCRIPT := $(SRCTREE)/cpu/arm920t/ep93xx/u-boot.lds
+
+ifdef CONFIG_EDB9301
+TEXT_BASE = 0x05700000
+endif
+
+ifdef CONFIG_EDB9302
+TEXT_BASE = 0x05700000
+endif
+
+ifdef CONFIG_EDB9302A
+TEXT_BASE = 0xc5700000
+endif
+
+ifdef CONFIG_EDB9307
+TEXT_BASE = 0x01f00000
+endif
+
+ifdef CONFIG_EDB9307A
+TEXT_BASE = 0xc1f00000
+endif
+
+ifdef CONFIG_EDB9312
+TEXT_BASE = 0x01f00000
+endif
+
+ifdef CONFIG_EDB9315
+TEXT_BASE = 0x01f00000
+endif
+
+ifdef CONFIG_EDB9315A
+TEXT_BASE = 0xc1f00000
+endif
diff --git a/board/edb93xx/early_udelay.h b/board/edb93xx/early_udelay.h
new file mode 100644
index 0000000..3b26b3f
--- /dev/null
+++ b/board/edb93xx/early_udelay.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* delay execution before timers are initialized */
+static inline void early_udelay(uint32_t usecs)
+{
+ /* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */
+ register uint32_t loops = (usecs * 1000) / 20;
+
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0" (loops));
+}
diff --git a/board/edb93xx/edb93xx.c b/board/edb93xx/edb93xx.c
new file mode 100644
index 0000000..8989d6e
--- /dev/null
+++ b/board/edb93xx/edb93xx.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * (C) Copyright 2002 2003
+ * Network Audio Technologies, Inc. <www.netaudiotech.com>
+ * Adam Bezanson <bezanson@netaudiotech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+
+#define MAX_BANK_SIZE 0x04000000 /* 64 MB */
+
+static ulong const bank_addr[CONFIG_NR_DRAM_BANKS] = {
+ PHYS_SDRAM_1,
+#ifdef PHYS_SDRAM_2
+ PHYS_SDRAM_2,
+#endif
+#ifdef PHYS_SDRAM_3
+ PHYS_SDRAM_3,
+#endif
+#ifdef PHYS_SDRAM_4
+ PHYS_SDRAM_4
+#endif
+};
+
+int board_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+ icache_enable();
+
+#ifdef USE_920T_MMU
+ dcache_enable();
+#endif
+
+ /*
+ * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of
+ * 14.7456/2 MHz
+ */
+ uint32_t value = readl(&syscon->pwrcnt);
+ value |= SYSCON_PWRCNT_UART_BAUD;
+ writel(value, &syscon->pwrcnt);
+
+ /* Machine number, as defined in linux/arch/arm/tools/mach-types */
+ gd->bd->bi_arch_number = MACH_TYPE;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+ /* We have a console */
+ gd->have_console = 1;
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+ return ep93xx_eth_init(bd);
+}
+
+int dram_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ unsigned int *src, *dst;
+ int i;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ const ulong bank_size = get_ram_size((long *)bank_addr[i],
+ MAX_BANK_SIZE);
+ if (bank_size) {
+ gd->bd->bi_dram[i].start = bank_addr[i];
+ gd->bd->bi_dram[i].size = bank_size;
+ }
+ }
+
+#ifdef CONFIG_EDB93XX_SDCS3
+ dst = (unsigned int *)0x00000000;
+#else
+ dst = (unsigned int *)0xc0000000;
+#endif
+
+ /* copy exception vectors */
+ src = (unsigned int *)_armboot_start;
+
+ for (i = 0; i < 16; i++)
+ *dst++ = *src++;
+
+ return 0;
+}
diff --git a/board/edb93xx/flash_cfg.c b/board/edb93xx/flash_cfg.c
new file mode 100644
index 0000000..24ea210
--- /dev/null
+++ b/board/edb93xx/flash_cfg.c
@@ -0,0 +1,38 @@
+/*
+ * Flash setup for Cirrus edb93xx boards
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+
+#define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \
+ SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \
+ 1 << SMC_BCR_MW_SHIFT)
+
+void flash_cfg(void)
+{
+ struct smc_regs *smc = (struct smc_regs *)SMC_BASE;
+
+ writel(SMC_BCR6_VALUE, &smc->bcr6);
+}
diff --git a/board/edb93xx/pll_cfg.c b/board/edb93xx/pll_cfg.c
new file mode 100644
index 0000000..a687af0
--- /dev/null
+++ b/board/edb93xx/pll_cfg.c
@@ -0,0 +1,58 @@
+/*
+ * PLL setup for Cirrus edb93xx boards
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include "pll_cfg.h"
+#include "early_udelay.h"
+
+void pll_cfg(void)
+{
+ struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+ /* setup PLL1 */
+ writel(CLKSET1_VAL, &syscon->clkset1);
+
+ /*
+ * flush the pipeline
+ * writing to CLKSET1 causes the EP93xx to enter standby for between
+ * 8 ms to 16 ms, until PLL1 stabilizes
+ */
+ asm("nop");
+ asm("nop");
+ asm("nop");
+ asm("nop");
+ asm("nop");
+
+ /* setup PLL2 */
+ writel(CLKSET2_VAL, &syscon->clkset2);
+
+ /*
+ * the user's guide recommends to wait at least 1 ms for PLL2 to
+ * stabilize
+ */
+ early_udelay(1000);
+}
diff --git a/board/edb93xx/pll_cfg.h b/board/edb93xx/pll_cfg.h
new file mode 100644
index 0000000..8001e01
--- /dev/null
+++ b/board/edb93xx/pll_cfg.h
@@ -0,0 +1,72 @@
+/*
+ * PLL register values for Cirrus edb93xx boards
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/ep93xx.h>
+
+#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \
+ defined(CONFIG_EDB9302A)
+/*
+ * fclk_div: 2, nbyp1: 1, hclk_div: 5, pclk_div: 2
+ * pll1_x1: 294912000.000000, pll1_x2ip: 36864000.000000,
+ * pll1_x2: 331776000.000000, pll1_out: 331776000.000000
+ */
+#define CLKSET1_VAL (7 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
+ 8 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
+ 19 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
+ 1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \
+ 3 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \
+ SYSCON_CLKSET1_NBYP1 | \
+ 1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT)
+#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) ||\
+ defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) ||\
+ defined(CONFIG_EDB9315A)
+/*
+ * fclk_div: 2, nbyp1: 1, hclk_div: 4, pclk_div: 2
+ * pll1_x1: 3096576000.000000, pll1_x2ip: 129024000.000000,
+ * pll1_x2: 3999744000.000000, pll1_out: 1999872000.000000
+ */
+#define CLKSET1_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
+ 30 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
+ 20 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
+ 1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \
+ 2 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \
+ SYSCON_CLKSET1_NBYP1 | \
+ 1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT)
+#else
+#error "Undefined board"
+#endif
+
+/*
+ * usb_div: 4, nbyp2: 1, pll2_en: 1
+ * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000,
+ * pll2_x2: 384000000.000000, pll2_out: 192000000.000000
+ */
+#define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
+ 24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
+ 24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
+ 1 << SYSCON_CLKSET_PLL_PS_SHIFT | \
+ SYSCON_CLKSET2_PLL2_EN | \
+ SYSCON_CLKSET2_NBYP2 | \
+ 3 << SYSCON_CLKSET2_USB_DIV_SHIFT)
diff --git a/board/edb93xx/sdram_cfg.c b/board/edb93xx/sdram_cfg.c
new file mode 100644
index 0000000..201390b
--- /dev/null
+++ b/board/edb93xx/sdram_cfg.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/io.h>
+#include "sdram_cfg.h"
+#include "early_udelay.h"
+
+#define PROGRAM_MODE_REG(bank) (*(volatile uint32_t *) \
+ (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank | SDRAM_MODE_REG_VAL))
+
+#define PRECHARGE_BANK(bank) (*(volatile uint32_t *) \
+ (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank))
+
+static void force_precharge(void);
+static void setup_refresh_timer(void);
+static void program_mode_registers(void);
+
+void sdram_cfg(void)
+{
+ struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
+
+ writel(SDRAM_DEVCFG_VAL, &sdram->SDRAM_DEVCFG_REG);
+
+ /* Issue continous NOP commands */
+ writel(GLCONFIG_INIT | GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig);
+
+ early_udelay(200);
+
+ force_precharge();
+
+ setup_refresh_timer();
+
+ program_mode_registers();
+
+ /* Select normal operation mode */
+ writel(GLCONFIG_CKE, &sdram->glconfig);
+}
+
+static void force_precharge(void)
+{
+ /*
+ * Errata most EP93xx revisions say that PRECHARGE ALL isn't always
+ * issued.
+ *
+ * Do a read from each bank to make sure they're precharged
+ */
+
+ PRECHARGE_BANK(0);
+ PRECHARGE_BANK(1);
+ PRECHARGE_BANK(2);
+ PRECHARGE_BANK(3);
+}
+
+static void setup_refresh_timer(void)
+{
+ struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
+
+ /* Load refresh timer with 10 to issue refresh every 10 cycles */
+ writel(0x0a, &sdram->refrshtimr);
+
+ /*
+ * Wait at least 80 clock cycles to provide 8 refresh cycles
+ * to all SDRAMs
+ */
+ early_udelay(1);
+
+ /*
+ * Program refresh timer with normal value
+ * We need 8192 refresh cycles every 64ms
+ * at 15ns (HCLK >= 66MHz) per cycle:
+ * 64ms / 8192 = 7.8125us
+ * 7.8125us / 15ns = 520 (0x208)
+ */
+ /*
+ * TODO: redboot uses 0x1e0 for the slowest possible device
+ * but i don't understand how this value is calculated
+ */
+ writel(0x208, &sdram->refrshtimr);
+}
+
+static void program_mode_registers(void)
+{
+ PROGRAM_MODE_REG(0);
+
+#if (CONFIG_NR_DRAM_BANKS >= 2)
+ PROGRAM_MODE_REG(1);
+#endif
+
+#if (CONFIG_NR_DRAM_BANKS >= 3)
+ PROGRAM_MODE_REG(2);
+#endif
+
+#if (CONFIG_NR_DRAM_BANKS == 4)
+ PROGRAM_MODE_REG(3);
+#endif
+}
diff --git a/board/edb93xx/sdram_cfg.h b/board/edb93xx/sdram_cfg.h
new file mode 100644
index 0000000..983ff83
--- /dev/null
+++ b/board/edb93xx/sdram_cfg.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/ep93xx.h>
+
+#define SDRAM_BASE_ADDR PHYS_SDRAM_1
+
+#ifdef CONFIG_EDB93XX_SDCS0
+#define SDRAM_DEVCFG_REG devcfg0
+#elif defined(CONFIG_EDB93XX_SDCS3)
+#define SDRAM_DEVCFG_REG devcfg3
+#else
+#error "SDRAM bank configuration"
+#endif
+
+#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) ||\
+ defined(CONFIG_EDB9302A)
+/*
+ * 1x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM
+ *
+ * CLK cycle time min:
+ * @ CAS latency = 3: 7.5ns
+ * @ CAS latency = 2: 10ns
+ * We're running at 66MHz (15ns cycle time) external bus speed (HCLK),
+ * so it's safe to use CAS latency = 2
+ *
+ * RAS-to-CAS delay min:
+ * 20ns
+ * At 15ns cycle time, we use RAS-to-CAS delay = 2
+ *
+ * SROMLL = 1: Swap BA[1:0] with A[13:12], making the SDRAM appear
+ * as four blocks of 8MB size, instead of eight blocks of 4MB size:
+ *
+ * EDB9301/EDB9302:
+ *
+ * 0x00000000 - 0x007fffff
+ * 0x01000000 - 0x017fffff
+ * 0x04000000 - 0x047fffff
+ * 0x05000000 - 0x057fffff
+ *
+ *
+ * EDB9302a:
+ *
+ * 0xc0000000 - 0xc07fffff
+ * 0xc1000000 - 0xc17fffff
+ * 0xc4000000 - 0xc47fffff
+ * 0xc5000000 - 0xc57fffff
+ *
+ * BANKCOUNT = 1: This is a device with four banks
+ */
+
+#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT | \
+ SDRAM_DEVCFG_SROMLL | \
+ SDRAM_DEVCFG_CASLAT_2 | \
+ SDRAM_DEVCFG_RASTOCAS_2 | \
+ SDRAM_DEVCFG_EXTBUSWIDTH)
+
+/*
+ * 16 bit ext. bus
+ *
+ * A[22:09] is output as SYA[13:0]
+ * CAS latency: 2
+ * Burst type: sequential
+ * Burst length: 8 (required for 16 bit ext. bus)
+ * SYA[13:0] = 0x0023
+ */
+#define SDRAM_MODE_REG_VAL 0x4600
+
+#define SDRAM_BANK_SEL_0 0x00000000 /* A[22:21] = b00 */
+#define SDRAM_BANK_SEL_1 0x00200000 /* A[22:21] = b01 */
+#define SDRAM_BANK_SEL_2 0x00400000 /* A[22:21] = b10 */
+#define SDRAM_BANK_SEL_3 0x00600000 /* A[22:21] = b11 */
+
+#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) ||\
+ defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) ||\
+ defined(CONFIG_EDB9315A)
+/*
+ * 2x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM
+ *
+ * CLK cycle time min:
+ * @ CAS latency = 3: 7.5ns
+ * @ CAS latency = 2: 10ns
+ * We're running at 100MHz (10ns cycle time) external bus speed (HCLK),
+ * so it's safe to use CAS latency = 2
+ *
+ * RAS-to-CAS delay min:
+ * 20ns
+ * At 10ns cycle time, we use RAS-to-CAS delay = 2
+ *
+ * EDB9307, EDB9312, EDB9315:
+ *
+ * 0x00000000 - 0x01ffffff
+ * 0x04000000 - 0x05ffffff
+ *
+ *
+ * EDB9307a, EDB9315a:
+ *
+ * 0xc0000000 - 0xc1ffffff
+ * 0xc4000000 - 0xc5ffffff
+ */
+
+#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT | \
+ SDRAM_DEVCFG_SROMLL | \
+ SDRAM_DEVCFG_CASLAT_2 | \
+ SDRAM_DEVCFG_RASTOCAS_2)
+
+/*
+ * 32 bit ext. bus
+ *
+ * A[23:10] is output as SYA[13:0]
+ * CAS latency: 2
+ * Burst type: sequential
+ * Burst length: 4
+ * SYA[13:0] = 0x0022
+ */
+#define SDRAM_MODE_REG_VAL 0x8800
+
+#define SDRAM_BANK_SEL_0 0x00000000 /* A[23:22] = b00 */
+#define SDRAM_BANK_SEL_1 0x00400000 /* A[23:22] = b01 */
+#define SDRAM_BANK_SEL_2 0x00800000 /* A[23:22] = b10 */
+#define SDRAM_BANK_SEL_3 0x00c00000 /* A[23:22] = b11 */
+#endif
diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h
new file mode 100644
index 0000000..457dbb2
--- /dev/null
+++ b/include/configs/edb93xx.h
@@ -0,0 +1,273 @@
+/*
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_MK_edb9301
+#define CONFIG_EDB9301
+#elif defined(CONFIG_MK_edb9302)
+#define CONFIG_EDB9302
+#elif defined(CONFIG_MK_edb9302a)
+#define CONFIG_EDB9302A
+#elif defined(CONFIG_MK_edb9307)
+#define CONFIG_EDB9307
+#elif defined(CONFIG_MK_edb9307a)
+#define CONFIG_EDB9307A
+#elif defined(CONFIG_MK_edb9312)
+#define CONFIG_EDB9312
+#elif defined(CONFIG_MK_edb9315)
+#define CONFIG_EDB9315
+#elif defined(CONFIG_MK_edb9315a)
+#define CONFIG_EDB9315A
+#else
+#error "no board defined"
+#endif
+
+/* Initial environment and monitor configuration options. */
+#define CONFIG_BOOTDELAY 2
+#define CONFIG_CMDLINE_TAG 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_BOOTARGS "root=/dev/nfs console=ttyAM0,115200 ip=dhcp"
+#define CONFIG_BOOTFILE "edb93xx.img"
+
+#define CONFIG_SYS_HUSH_PARSER 1
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#ifdef CONFIG_EDB9301
+#define CONFIG_EP9301
+#define MACH_TYPE MACH_TYPE_EDB9301
+#define CONFIG_SYS_PROMPT "EDB9301> "
+#define CONFIG_ENV_SECT_SIZE 0x00020000
+#elif defined(CONFIG_EDB9302)
+#define CONFIG_EP9302
+#define MACH_TYPE MACH_TYPE_EDB9302
+#define CONFIG_SYS_PROMPT "EDB9302> "
+#define CONFIG_ENV_SECT_SIZE 0x00020000
+#elif defined(CONFIG_EDB9302A)
+#define CONFIG_EP9302
+#define MACH_TYPE MACH_TYPE_EDB9302A
+#define CONFIG_SYS_PROMPT "EDB9302A> "
+#define CONFIG_ENV_SECT_SIZE 0x00020000
+#elif defined(CONFIG_EDB9307)
+#define CONFIG_EP9307
+#define MACH_TYPE MACH_TYPE_EDB9307
+#define CONFIG_SYS_PROMPT "EDB9307> "
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#elif defined(CONFIG_EDB9307A)
+#define CONFIG_EP9307
+#define MACH_TYPE MACH_TYPE_EDB9307A
+#define CONFIG_SYS_PROMPT "EDB9307A> "
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#elif defined(CONFIG_EDB9312)
+#define CONFIG_EP9312
+#define MACH_TYPE MACH_TYPE_EDB9312
+#define CONFIG_SYS_PROMPT "EDB9312> "
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#elif defined(CONFIG_EDB9315)
+#define CONFIG_EP9315
+#define MACH_TYPE MACH_TYPE_EDB9315
+#define CONFIG_SYS_PROMPT "EDB9315> "
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#elif defined(CONFIG_EDB9315A)
+#define CONFIG_EP9315
+#define MACH_TYPE MACH_TYPE_EDB9315A
+#define CONFIG_SYS_PROMPT "EDB9315A> "
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#else
+#error "no board defined"
+#endif
+
+/* High-level configuration options */
+#define CONFIG_ARM920T 1 /* This is an ARM920T core... */
+#define CONFIG_EP93XX 1 /* in a Cirrus Logic 93xx SoC */
+
+#define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456 clock */
+#define CONFIG_SYS_HZ 1000 /* decr freq: 1 ms ticks */
+#undef CONFIG_USE_IRQ /* Don't need IRQ/FIQ */
+
+/* Monitor configuration */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#undef CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+
+#define CONFIG_SYS_LONGHELP /* Enable "long" help in mon */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
+/* Print buffer size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+/* Boot argument buffer size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
+
+/* Serial port hardware configuration */
+#define CONFIG_PL010_SERIAL
+#define CONFIG_CONS_INDEX 0
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+#define CONFIG_SYS_SERIAL0 0x808C0000
+#define CONFIG_SYS_SERIAL1 0x808D0000
+#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
+ (void *)CONFIG_SYS_SERIAL1}
+
+/* Status LED */
+#define CONFIG_STATUS_LED 1 /* Status LED enabled */
+#define CONFIG_BOARD_SPECIFIC_LED 1
+#define STATUS_LED_GREEN 0
+#define STATUS_LED_RED 1
+/* Green */
+#define STATUS_LED_BIT STATUS_LED_GREEN
+#define STATUS_LED_STATE STATUS_LED_ON
+#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
+/* Red */
+#define STATUS_LED_BIT1 STATUS_LED_RED
+#define STATUS_LED_STATE1 STATUS_LED_OFF
+#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
+/* Optional value */
+#define STATUS_LED_BOOT STATUS_LED_BIT
+
+/* Network hardware configuration */
+#define CONFIG_DRIVER_EP93XX_MAC
+#define CONFIG_MII_SUPPRESS_PREAMBLE
+#define CONFIG_MII
+#define CONFIG_PHY_ADDR 1
+#define CONFIG_NET_MULTI
+#undef CONFIG_NETCONSOLE
+
+
+/* SDRAM configuration */
+#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302)
+/*
+ * EDB9301/2 has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
+ * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
+ * the SROMLL bit on the processor, resulting in this non-contiguous memory map.
+ */
+#define CONFIG_NR_DRAM_BANKS 4
+#define PHYS_SDRAM_1 0x00000000
+#define PHYS_SDRAM_SIZE_1 0x00800000
+#define PHYS_SDRAM_2 0x01000000
+#define PHYS_SDRAM_SIZE_2 0x00800000
+#define PHYS_SDRAM_3 0x04000000
+#define PHYS_SDRAM_SIZE_3 0x00800000
+#define PHYS_SDRAM_4 0x05000000
+#define PHYS_SDRAM_SIZE_4 0x00800000
+#define CONFIG_EDB93XX_SDCS3
+#define CONFIG_SYS_MEMTEST_START 0x00100000
+#define CONFIG_SYS_MEMTEST_END 0x007fffff
+
+#elif defined(CONFIG_EDB9302A)
+/*
+ * EDB9302a has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
+ * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
+ * the SROMLL bit on the processor, resulting in this non-contiguous memory map.
+ */
+#define CONFIG_NR_DRAM_BANKS 4
+#define PHYS_SDRAM_1 0xc0000000
+#define PHYS_SDRAM_SIZE_1 0x00800000
+#define PHYS_SDRAM_2 0xc1000000
+#define PHYS_SDRAM_SIZE_2 0x00800000
+#define PHYS_SDRAM_3 0xc4000000
+#define PHYS_SDRAM_SIZE_3 0x00800000
+#define PHYS_SDRAM_4 0xc5000000
+#define PHYS_SDRAM_SIZE_4 0x00800000
+#define CONFIG_EDB93XX_SDCS0
+#define CONFIG_SYS_MEMTEST_START 0xc0100000
+#define CONFIG_SYS_MEMTEST_END 0xc07fffff
+
+#elif defined(CONFIG_EDB9307) || defined CONFIG_EDB9312 || \
+ defined(CONFIG_EDB9315)
+/*
+ * The EDB9307, EDB9312, and EDB9315 have 2 banks of SDRAM consisting of
+ * 2x Samsung K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of
+ * 64 MB of SDRAM.
+ */
+#define CONFIG_NR_DRAM_BANKS 2
+#define PHYS_SDRAM_1 0x00000000
+#define PHYS_SDRAM_SIZE_1 0x02000000
+#define PHYS_SDRAM_2 0x04000000
+#define PHYS_SDRAM_SIZE_2 0x02000000
+#define CONFIG_EDB93XX_SDCS3
+#define CONFIG_SYS_MEMTEST_START 0x00100000
+#define CONFIG_SYS_MEMTEST_END 0x01e00000
+
+#elif defined(CONFIG_EDB9307A) || defined(CONFIG_EDB9315A)
+/*
+ * The EDB9307A and EDB9315A have 2 banks of SDRAM consisting of 2x Samsung
+ * K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of 64 MB of SDRAM.
+ */
+#define CONFIG_NR_DRAM_BANKS 2
+#define PHYS_SDRAM_1 0xc0000000
+#define PHYS_SDRAM_SIZE_1 0x02000000
+#define PHYS_SDRAM_2 0xc4000000
+#define PHYS_SDRAM_SIZE_2 0x02000000
+#define CONFIG_EDB93XX_SDCS0
+#define CONFIG_SYS_MEMTEST_START 0xc0100000
+#define CONFIG_SYS_MEMTEST_END 0xc1e00000
+#endif
+
+#if defined(CONFIG_EDB93XX_SDCS3)
+#define CONFIG_SYS_LOAD_ADDR 0x01000000 /* Default load address */
+#elif defined(CONFIG_EDB93XX_SDCS0)
+#define CONFIG_SYS_LOAD_ADDR 0xc1000000 /* Default load address */
+#endif
+
+/* Must match kernel config */
+#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
+
+/* Run-time memory allocatons */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+#define CONFIG_STACKSIZE (128 * 1024)
+
+#if defined(CONFIG_USE_IRQ)
+#define CONFIG_STACKSIZE_IRQ (4 * 1024)
+#define CONFIG_STACKSIZE_FIQ (4 * 1024)
+#endif
+
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
+
+/* -----------------------------------------------------------------------------
+ * FLASH and environment organization
+ *
+ * The EDB9301 and EDB9302(a) have 1 bank of flash memory at 0x60000000
+ * consisting of 1x Intel TE28F128J3C-150 128 Mbit flash on a 16-bit data bus,
+ * for a total of 16 MB of CFI-compatible flash.
+ *
+ * The EDB9307(a), EDB9312, and EDB9315(a) have 1 bank of flash memory at
+ * 0x60000000 consisting of 2x Micron MT28F128J3-12 128 Mbit flash on a 32-bit
+ * data bus, for a total of 32 MB of CFI-compatible flash.
+ *
+ * EDB9301/02(a) EDB9307(a)/12/15(a)
+ * 0x60000000 - 0x0003FFFF u-boot u-boot
+ * 0x60040000 - 0x0005FFFF environment #1 environment #1
+ * 0x60060000 - 0x0007FFFF environment #2 environment #1 (continued)
+ * 0x60080000 - 0x0009FFFF unused environment #2
+ * 0x600A0000 - 0x000BFFFF unused environment #2 (continued)
+ * 0x600C0000 - 0x00FFFFFF unused unused
+ * 0x61000000 - 0x01FFFFFF not present unused
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 128
+
+#define PHYS_FLASH_1 0x60000000
+#define CONFIG_SYS_FLASH_BASE (PHYS_FLASH_1)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+
+#define CONFIG_ENV_OVERWRITE /* Vendor params unprotected */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR 0x60040000
+
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+#endif /* !defined (__CONFIG_H) */
--
1.6.3.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH 3/3] Add support for EDB93xx boards
2010-01-19 19:16 ` Matthias Kaehlcke
@ 2010-01-19 21:58 ` Wolfgang Denk
0 siblings, 0 replies; 12+ messages in thread
From: Wolfgang Denk @ 2010-01-19 21:58 UTC (permalink / raw)
To: u-boot
Dear Matthias Kaehlcke,
In message <20100119191627.GM16182@darwin> you wrote:
> Added support for the following EDB93xx boards:
>
> EDB9301
> EDB9302
> EDB9302A
> EDB9307
> EDB9307A
> EDB93012
> EDB9315
> EDB9315A
...
> +int board_init(void)
> +{
> + DECLARE_GLOBAL_DATA_PTR;
This is bound to fail. DECLARE_GLOBAL_DATA_PTR must be on file level,
never at function level! Fix globally!
> + /* Machine number, as defined in linux/arch/arm/tools/mach-types */
> + gd->bd->bi_arch_number = MACH_TYPE;
Please use CONFIG_MACH_TYPE instead (fix globally).
...
> + /* copy exception vectors */
> + src = (unsigned int *)_armboot_start;
> +
> + for (i = 0; i < 16; i++)
> + *dst++ = *src++;
Any reason for not using memcpy() ?
> diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h
> new file mode 100644
> index 0000000..457dbb2
> --- /dev/null
> +++ b/include/configs/edb93xx.h
> @@ -0,0 +1,273 @@
> +/*
> + */
Please add valid file header.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Doubt is a pain too lonely to know that faith is his twin brother.
- Kahlil Gibran
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH 1/3] ARM: Add support for EP93xx SoCs
[not found] <cover.1264351928.git.matthias@kaehlcke.net>
@ 2010-01-24 16:56 ` Matthias Kaehlcke
2010-01-31 18:53 ` Tom
2010-01-24 16:56 ` [U-Boot] [PATCH 2/3] Add EP93xx ethernet driver Matthias Kaehlcke
2010-01-24 16:56 ` [U-Boot] [PATCH 3/3] Add support for EDB93xx boards Matthias Kaehlcke
2 siblings, 1 reply; 12+ messages in thread
From: Matthias Kaehlcke @ 2010-01-24 16:56 UTC (permalink / raw)
To: u-boot
Add support for the Cirrus EP93xx platform
Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
---
cpu/arm920t/ep93xx/Makefile | 56 ++++
cpu/arm920t/ep93xx/cpu.c | 51 +++
cpu/arm920t/ep93xx/led.c | 101 ++++++
cpu/arm920t/ep93xx/lowlevel_init.S | 65 ++++
cpu/arm920t/ep93xx/speed.c | 110 +++++++
cpu/arm920t/ep93xx/timer.c | 168 ++++++++++
cpu/arm920t/ep93xx/u-boot.lds | 59 ++++
include/asm-arm/arch-ep93xx/ep93xx.h | 595 ++++++++++++++++++++++++++++++++++
include/common.h | 3 +-
9 files changed, 1207 insertions(+), 1 deletions(-)
create mode 100644 cpu/arm920t/ep93xx/Makefile
create mode 100644 cpu/arm920t/ep93xx/cpu.c
create mode 100644 cpu/arm920t/ep93xx/led.c
create mode 100644 cpu/arm920t/ep93xx/lowlevel_init.S
create mode 100644 cpu/arm920t/ep93xx/speed.c
create mode 100644 cpu/arm920t/ep93xx/timer.c
create mode 100644 cpu/arm920t/ep93xx/u-boot.lds
create mode 100644 include/asm-arm/arch-ep93xx/ep93xx.h
diff --git a/cpu/arm920t/ep93xx/Makefile b/cpu/arm920t/ep93xx/Makefile
new file mode 100644
index 0000000..30e12af
--- /dev/null
+++ b/cpu/arm920t/ep93xx/Makefile
@@ -0,0 +1,56 @@
+#
+# Cirrus Logic EP93xx CPU-specific Makefile
+#
+# Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+#
+# Copyright (C) 2004, 2005
+# Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+#
+# Copyright (C) 2006
+# Dominic Rath <Dominic.Rath@gmx.de>
+#
+# Based on an original Makefile, which is
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this project.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+# for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+COBJS = cpu.o led.o speed.o timer.o
+SOBJS = lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+
diff --git a/cpu/arm920t/ep93xx/cpu.c b/cpu/arm920t/ep93xx/cpu.c
new file mode 100644
index 0000000..1abb9c6
--- /dev/null
+++ b/cpu/arm920t/ep93xx/cpu.c
@@ -0,0 +1,51 @@
+/*
+ * Cirrus Logic EP93xx CPU-specific support.
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+
+/* We reset the CPU by generating a 1-->0 transition on DeviceCfg bit 31. */
+extern void reset_cpu(ulong addr)
+{
+ struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+ uint32_t value;
+
+ /* Unlock DeviceCfg and set SWRST */
+ writel(0xAA, &syscon->sysswlock);
+ value = readl(&syscon->devicecfg);
+ value |= SYSCON_DEVICECFG_SWRST;
+ writel(value, &syscon->devicecfg);
+
+ /* Unlock DeviceCfg and clear SWRST */
+ writel(0xAA, &syscon->sysswlock);
+ value = readl(&syscon->devicecfg);
+ value &= ~SYSCON_DEVICECFG_SWRST;
+ writel(value, &syscon->devicecfg);
+
+ /* Dying... */
+ while (1)
+ ; /* noop */
+}
diff --git a/cpu/arm920t/ep93xx/led.c b/cpu/arm920t/ep93xx/led.c
new file mode 100644
index 0000000..7e2c897
--- /dev/null
+++ b/cpu/arm920t/ep93xx/led.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2010, 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/io.h>
+#include <asm/arch/ep93xx.h>
+#include <config.h>
+#include <status_led.h>
+
+static uint8_t saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF};
+static uint32_t gpio_pin[2] = {1 << STATUS_LED_GREEN,
+ 1 << STATUS_LED_RED};
+
+inline void switch_LED_on(uint8_t led)
+{
+ register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
+
+ writel(readl(&gpio->pedr) | gpio_pin[led], &gpio->pedr);
+ saved_state[led] = STATUS_LED_ON;
+}
+
+inline void switch_LED_off(uint8_t led)
+{
+ register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
+
+ writel(readl(&gpio->pedr) & ~gpio_pin[led], &gpio->pedr);
+ saved_state[led] = STATUS_LED_OFF;
+}
+
+void red_LED_on(void)
+{
+ switch_LED_on(STATUS_LED_RED);
+}
+
+void red_LED_off(void)
+{
+ switch_LED_off(STATUS_LED_RED);
+}
+
+void green_LED_on(void)
+{
+ switch_LED_on(STATUS_LED_GREEN);
+}
+
+void green_LED_off(void)
+{
+ switch_LED_off(STATUS_LED_GREEN);
+}
+
+void __led_init(led_id_t mask, int state)
+{
+ __led_set(mask, state);
+}
+
+void __led_toggle(led_id_t mask)
+{
+ if (STATUS_LED_RED == mask) {
+ if (STATUS_LED_ON == saved_state[STATUS_LED_RED])
+ red_LED_off();
+ else
+ red_LED_on();
+ } else if (STATUS_LED_GREEN == mask) {
+ if (STATUS_LED_ON == saved_state[STATUS_LED_GREEN])
+ green_LED_off();
+ else
+ green_LED_on();
+ }
+}
+
+void __led_set(led_id_t mask, int state)
+{
+ if (STATUS_LED_RED == mask) {
+ if (STATUS_LED_ON == state)
+ red_LED_on();
+ else
+ red_LED_off();
+ } else if (STATUS_LED_GREEN == mask) {
+ if (STATUS_LED_ON == state)
+ green_LED_on();
+ else
+ green_LED_off();
+ }
+}
diff --git a/cpu/arm920t/ep93xx/lowlevel_init.S b/cpu/arm920t/ep93xx/lowlevel_init.S
new file mode 100644
index 0000000..a20ec89
--- /dev/null
+++ b/cpu/arm920t/ep93xx/lowlevel_init.S
@@ -0,0 +1,65 @@
+/*
+ * Low-level initialization for EP93xx
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <version.h>
+#include <asm/arch/ep93xx.h>
+
+.globl lowlevel_init
+lowlevel_init:
+ /* backup return address */
+ ldr r1, =SYSCON_SCRATCH0
+ str lr, [r1]
+
+ /* Turn on both LEDs */
+ bl red_LED_on
+ bl green_LED_on
+
+ /* Configure flash wait states before we switch to the PLL */
+ bl flash_cfg
+
+ /* Set up PLL */
+ bl pll_cfg
+
+ /* Turn off the Green LED and leave the Red LED on */
+ bl green_LED_off
+
+ /* Setup SDRAM */
+ bl sdram_cfg
+
+ /* Turn on Green LED, Turn off the Red LED */
+ bl green_LED_on
+ bl red_LED_off
+
+ /* FIXME: we use async mode for now */
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, r0, #0xc0000000
+ mcr p15, 0, r0, c1, c0, 0
+
+ /* restore return address */
+ ldr r1, =SYSCON_SCRATCH0
+ ldr lr, [r1]
+
+ mov pc, lr
diff --git a/cpu/arm920t/ep93xx/speed.c b/cpu/arm920t/ep93xx/speed.c
new file mode 100644
index 0000000..c83a3bb
--- /dev/null
+++ b/cpu/arm920t/ep93xx/speed.c
@@ -0,0 +1,110 @@
+/*
+ * Cirrus Logic EP93xx PLL support.
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+#include <div64.h>
+
+/*
+ * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
+ *
+ * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
+ * the specified bus in HZ.
+ */
+
+/*
+ * return the PLL output frequency
+ *
+ * PLL rate = CONFIG_SYS_CLK_FREQ * (X1FBD + 1) * (X2FBD + 1)
+ * / (X2IPD + 1) / 2^PS
+ */
+static ulong get_PLLCLK(uint32_t *pllreg)
+{
+ uint8_t i;
+ const uint32_t clkset = readl(pllreg);
+ uint64_t rate = CONFIG_SYS_CLK_FREQ;
+ rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1;
+ rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1;
+ do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */
+ for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++)
+ rate >>= 1;
+
+ return (ulong)rate;
+}
+
+/* return FCLK frequency */
+ulong get_FCLK()
+{
+ const uint8_t fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
+ struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+ const uint32_t clkset1 = readl(&syscon->clkset1);
+ const uint8_t fclk_div =
+ fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7];
+ const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div;
+
+ return fclk_rate;
+}
+
+/* return HCLK frequency */
+ulong get_HCLK(void)
+{
+ const uint8_t hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
+ struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+ const uint32_t clkset1 = readl(&syscon->clkset1);
+ const uint8_t hclk_div =
+ hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7];
+ const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div;
+
+ return hclk_rate;
+}
+
+/* return PCLK frequency */
+ulong get_PCLK(void)
+{
+ const uint8_t pclk_divisors[] = { 1, 2, 4, 8 };
+ struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+ const uint32_t clkset1 = readl(&syscon->clkset1);
+ const uint8_t pclk_div =
+ pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3];
+ const ulong pclk_rate = get_HCLK() / pclk_div;
+
+ return pclk_rate;
+}
+
+/* return UCLK frequency */
+ulong get_UCLK(void)
+{
+ struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+ ulong uclk_rate;
+
+ const uint32_t value = readl(&syscon->pwrcnt);
+ if (value & SYSCON_PWRCNT_UART_BAUD)
+ uclk_rate = CONFIG_SYS_CLK_FREQ;
+ else
+ uclk_rate = CONFIG_SYS_CLK_FREQ / 2;
+
+ return uclk_rate;
+}
diff --git a/cpu/arm920t/ep93xx/timer.c b/cpu/arm920t/ep93xx/timer.c
new file mode 100644
index 0000000..6d969d9
--- /dev/null
+++ b/cpu/arm920t/ep93xx/timer.c
@@ -0,0 +1,168 @@
+/*
+ * Cirrus Logic EP93xx timer support.
+ *
+ * Copyright (C) 2009, 2010
+ * Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+ *
+ * Based on the original intr.c Cirrus Logic EP93xx Rev D. interrupt support,
+ * author unknown.
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+
+#define TIMER_CLKSEL (1 << 3)
+#define TIMER_MODE (1 << 6)
+#define TIMER_ENABLE (1 << 7)
+
+#define TIMER_FREQ 508469
+#define TIMER_LOAD_VAL (TIMER_FREQ / CONFIG_SYS_HZ)
+
+static ulong timestamp;
+static ulong lastdec;
+
+static inline unsigned long clk_to_systicks(unsigned long clk_ticks)
+{
+ unsigned long sys_ticks = (clk_ticks * CONFIG_SYS_HZ) / TIMER_FREQ;
+
+ return sys_ticks;
+}
+
+static inline unsigned long usecs_to_ticks(unsigned long usecs)
+{
+ unsigned long ticks;
+
+ if (usecs >= 1000) {
+ ticks = usecs / 1000;
+ ticks *= (TIMER_LOAD_VAL * CONFIG_SYS_HZ);
+ ticks /= 1000;
+ } else {
+ ticks = usecs * TIMER_LOAD_VAL * CONFIG_SYS_HZ;
+ ticks /= (1000 * 1000);
+ }
+
+ return ticks;
+}
+
+static inline unsigned long read_timer(void)
+{
+ struct timer_regs *timer = (struct timer_regs *)TIMER_BASE;
+
+ return readl(&timer->timer3.value);
+}
+
+/*
+ * timer without interrupts
+ */
+unsigned long long get_ticks(void)
+{
+ const unsigned long now = read_timer();
+
+ if (lastdec >= now) {
+ /* normal mode */
+ timestamp += lastdec - now;
+ } else {
+ /* we have an overflow ... */
+ timestamp += lastdec + TIMER_LOAD_VAL - now;
+ }
+
+ lastdec = now;
+
+ return timestamp;
+}
+
+unsigned long get_timer_masked(void)
+{
+ return clk_to_systicks(get_ticks());
+}
+
+unsigned long get_timer(unsigned long base)
+{
+ return get_timer_masked() - base;
+}
+
+void reset_timer_masked(void)
+{
+ lastdec = read_timer();
+ timestamp = 0;
+}
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+void set_timer(unsigned long t)
+{
+ timestamp = t;
+}
+
+void __udelay(unsigned long usec)
+{
+ const unsigned long ticks = usecs_to_ticks(usec);
+ const unsigned long target = clk_to_systicks(ticks) + get_timer(0);
+
+ while (get_timer_masked() < target)
+ /* noop */;
+}
+
+void udelay_masked(unsigned long usec)
+{
+ const unsigned long ticks = usecs_to_ticks(usec);
+ const unsigned long target = clk_to_systicks(ticks) + get_timer(0);
+
+ reset_timer_masked();
+
+ while (get_timer_masked() < target)
+ /* noop */;
+}
+
+int timer_init(void)
+{
+ struct timer_regs *timer = (struct timer_regs *)TIMER_BASE;
+
+ /* use timer 3 with 508KHz and free running */
+ writel(TIMER_CLKSEL, &timer->timer3.control);
+
+ /* auto load, manual update of Timer 3 */
+ lastdec = TIMER_LOAD_VAL;
+ writel(TIMER_LOAD_VAL, &timer->timer3.load);
+
+ /* Enable the timer and periodic mode */
+ writel(TIMER_ENABLE | TIMER_MODE | TIMER_CLKSEL,
+ &timer->timer3.control);
+
+ reset_timer_masked();
+
+ return 0;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+unsigned long get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
+}
diff --git a/cpu/arm920t/ep93xx/u-boot.lds b/cpu/arm920t/ep93xx/u-boot.lds
new file mode 100644
index 0000000..737c9d8
--- /dev/null
+++ b/cpu/arm920t/ep93xx/u-boot.lds
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm920t/start.o (.text)
+ /* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */
+ . = 0x1000;
+ LONG(0x53555243)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
diff --git a/include/asm-arm/arch-ep93xx/ep93xx.h b/include/asm-arm/arch-ep93xx/ep93xx.h
new file mode 100644
index 0000000..6cafe54
--- /dev/null
+++ b/include/asm-arm/arch-ep93xx/ep93xx.h
@@ -0,0 +1,595 @@
+/*
+ * Cirrus Logic EP93xx register definitions.
+ *
+ * Copyright (C) 2009
+ * Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2006
+ * Dominic Rath <Dominic.Rath@gmx.de>
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+ *
+ * Based in large part on linux/include/asm-arm/arch-ep93xx/regmap.h, which is
+ *
+ * Copyright (C) 2004 Ray Lehtiniemi
+ * Copyright (C) 2003 Cirrus Logic, Inc
+ * Copyright (C) 1999 ARM Limited.
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#define EP93XX_AHB_BASE 0x80000000
+#define EP93XX_APB_BASE 0x80800000
+
+/*
+ * 0x80000000 - 0x8000FFFF: DMA
+ */
+#define DMA_OFFSET 0x000000
+#define DMA_BASE (EP93XX_AHB_BASE | DMA_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct dma_channel {
+ uint32_t control;
+ uint32_t interrupt;
+ uint32_t ppalloc;
+ uint32_t status;
+ uint32_t reserved0;
+ uint32_t remain;
+ uint32_t reserved1[2];
+ uint32_t maxcnt0;
+ uint32_t base0;
+ uint32_t current0;
+ uint32_t reserved2;
+ uint32_t maxcnt1;
+ uint32_t base1;
+ uint32_t current1;
+ uint32_t reserved3;
+};
+
+struct dma_regs {
+ struct dma_channel m2p_channel_0;
+ struct dma_channel m2p_channel_1;
+ struct dma_channel m2p_channel_2;
+ struct dma_channel m2p_channel_3;
+ struct dma_channel m2m_channel_0;
+ struct dma_channel m2m_channel_1;
+ struct dma_channel reserved0[2];
+ struct dma_channel m2p_channel_5;
+ struct dma_channel m2p_channel_4;
+ struct dma_channel m2p_channel_7;
+ struct dma_channel m2p_channel_6;
+ struct dma_channel m2p_channel_9;
+ struct dma_channel m2p_channel_8;
+ uint32_t channel_arbitration;
+ uint32_t reserved[15];
+ uint32_t global_interrupt;
+};
+#endif
+
+/*
+ * 0x80010000 - 0x8001FFFF: Ethernet MAC
+ */
+#define MAC_OFFSET 0x010000
+#define MAC_BASE (EP93XX_AHB_BASE | MAC_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct mac_queue {
+ uint32_t badd;
+ union { /* deal with half-word aligned registers */
+ uint32_t blen;
+ union {
+ uint16_t filler;
+ uint16_t curlen;
+ };
+ };
+ uint32_t curadd;
+};
+
+struct mac_regs {
+ uint32_t rxctl;
+ uint32_t txctl;
+ uint32_t testctl;
+ uint32_t reserved0;
+ uint32_t miicmd;
+ uint32_t miidata;
+ uint32_t miists;
+ uint32_t reserved1;
+ uint32_t selfctl;
+ uint32_t inten;
+ uint32_t intstsp;
+ uint32_t intstsc;
+ uint32_t reserved2[2];
+ uint32_t diagad;
+ uint32_t diagdata;
+ uint32_t gt;
+ uint32_t fct;
+ uint32_t fcf;
+ uint32_t afp;
+ union {
+ struct {
+ uint32_t indad;
+ uint32_t indad_upper;
+ };
+ uint32_t hashtbl;
+ };
+ uint32_t reserved3[2];
+ uint32_t giintsts;
+ uint32_t giintmsk;
+ uint32_t giintrosts;
+ uint32_t giintfrc;
+ uint32_t txcollcnt;
+ uint32_t rxmissnct;
+ uint32_t rxruntcnt;
+ uint32_t reserved4;
+ uint32_t bmctl;
+ uint32_t bmsts;
+ uint32_t rxbca;
+ uint32_t reserved5;
+ struct mac_queue rxdq;
+ uint32_t rxdqenq;
+ struct mac_queue rxstsq;
+ uint32_t rxstsqenq;
+ struct mac_queue txdq;
+ uint32_t txdqenq;
+ struct mac_queue txstsq;
+ uint32_t reserved6;
+ uint32_t rxbufthrshld;
+ uint32_t txbufthrshld;
+ uint32_t rxststhrshld;
+ uint32_t txststhrshld;
+ uint32_t rxdthrshld;
+ uint32_t txdthrshld;
+ uint32_t maxfrmlen;
+ uint32_t maxhdrlen;
+};
+#endif
+
+#define SELFCTL_RWP (1 << 7)
+#define SELFCTL_GPO0 (1 << 5)
+#define SELFCTL_PUWE (1 << 4)
+#define SELFCTL_PDWE (1 << 3)
+#define SELFCTL_MIIL (1 << 2)
+#define SELFCTL_RESET (1 << 0)
+
+#define INTSTS_RWI (1 << 30)
+#define INTSTS_RXMI (1 << 29)
+#define INTSTS_RXBI (1 << 28)
+#define INTSTS_RXSQI (1 << 27)
+#define INTSTS_TXLEI (1 << 26)
+#define INTSTS_ECIE (1 << 25)
+#define INTSTS_TXUHI (1 << 24)
+#define INTSTS_MOI (1 << 18)
+#define INTSTS_TXCOI (1 << 17)
+#define INTSTS_RXROI (1 << 16)
+#define INTSTS_MIII (1 << 12)
+#define INTSTS_PHYI (1 << 11)
+#define INTSTS_TI (1 << 10)
+#define INTSTS_AHBE (1 << 8)
+#define INTSTS_OTHER (1 << 4)
+#define INTSTS_TXSQ (1 << 3)
+#define INTSTS_RXSQ (1 << 2)
+
+#define BMCTL_MT (1 << 13)
+#define BMCTL_TT (1 << 12)
+#define BMCTL_UNH (1 << 11)
+#define BMCTL_TXCHR (1 << 10)
+#define BMCTL_TXDIS (1 << 9)
+#define BMCTL_TXEN (1 << 8)
+#define BMCTL_EH2 (1 << 6)
+#define BMCTL_EH1 (1 << 5)
+#define BMCTL_EEOB (1 << 4)
+#define BMCTL_RXCHR (1 << 2)
+#define BMCTL_RXDIS (1 << 1)
+#define BMCTL_RXEN (1 << 0)
+
+#define BMSTS_TXACT (1 << 7)
+#define BMSTS_TP (1 << 4)
+#define BMSTS_RXACT (1 << 3)
+#define BMSTS_QID_MASK 0x07
+#define BMSTS_QID_RXDATA 0x00
+#define BMSTS_QID_TXDATA 0x01
+#define BMSTS_QID_RXSTS 0x02
+#define BMSTS_QID_TXSTS 0x03
+#define BMSTS_QID_RXDESC 0x04
+#define BMSTS_QID_TXDESC 0x05
+
+#define AFP_MASK 0x07
+#define AFP_IAPRIMARY 0x00
+#define AFP_IASECONDARY1 0x01
+#define AFP_IASECONDARY2 0x02
+#define AFP_IASECONDARY3 0x03
+#define AFP_TX 0x06
+#define AFP_HASH 0x07
+
+#define RXCTL_PAUSEA (1 << 20)
+#define RXCTL_RXFCE1 (1 << 19)
+#define RXCTL_RXFCE0 (1 << 18)
+#define RXCTL_BCRC (1 << 17)
+#define RXCTL_SRXON (1 << 16)
+#define RXCTL_RCRCA (1 << 13)
+#define RXCTL_RA (1 << 12)
+#define RXCTL_PA (1 << 11)
+#define RXCTL_BA (1 << 10)
+#define RXCTL_MA (1 << 9)
+#define RXCTL_IAHA (1 << 8)
+#define RXCTL_IA3 (1 << 3)
+#define RXCTL_IA2 (1 << 2)
+#define RXCTL_IA1 (1 << 1)
+#define RXCTL_IA0 (1 << 0)
+
+#define TXCTL_DEFDIS (1 << 7)
+#define TXCTL_MBE (1 << 6)
+#define TXCTL_ICRC (1 << 5)
+#define TXCTL_TPD (1 << 4)
+#define TXCTL_OCOLL (1 << 3)
+#define TXCTL_SP (1 << 2)
+#define TXCTL_PB (1 << 1)
+#define TXCTL_STXON (1 << 0)
+
+#define MIICMD_REGAD_MASK (0x001F)
+#define MIICMD_PHYAD_MASK (0x03E0)
+#define MIICMD_OPCODE_MASK (0xC000)
+#define MIICMD_PHYAD_8950 (0x0000)
+#define MIICMD_OPCODE_READ (0x8000)
+#define MIICMD_OPCODE_WRITE (0x4000)
+
+#define MIISTS_BUSY (1 << 0)
+
+/*
+ * 0x80020000 - 0x8002FFFF: USB OHCI
+ */
+#define USB_OFFSET 0x020000
+#define USB_BASE (EP93XX_AHB_BASE | USB_OFFSET)
+
+/*
+ * 0x80030000 - 0x8003FFFF: Raster engine
+ */
+#if (defined(CONFIG_EP9307) || defined(CONFIG_EP9312) || defined(CONFIG_EP9315))
+#define RASTER_OFFSET 0x030000
+#define RASTER_BASE (EP93XX_AHB_BASE | RASTER_OFFSET)
+#endif
+
+/*
+ * 0x80040000 - 0x8004FFFF: Graphics accelerator
+ */
+#if defined(CONFIG_EP9315)
+#define GFX_OFFSET 0x040000
+#define GFX_BASE (EP93XX_AHB_BASE | GFX_OFFSET)
+#endif
+
+/*
+ * 0x80050000 - 0x8005FFFF: Reserved
+ */
+
+/*
+ * 0x80060000 - 0x8006FFFF: SDRAM controller
+ */
+#define SDRAM_OFFSET 0x060000
+#define SDRAM_BASE (EP93XX_AHB_BASE | SDRAM_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct sdram_regs {
+ uint32_t reserved;
+ uint32_t glconfig;
+ uint32_t refrshtimr;
+ uint32_t bootsts;
+ uint32_t devcfg0;
+ uint32_t devcfg1;
+ uint32_t devcfg2;
+ uint32_t devcfg3;
+};
+#endif
+
+#define SDRAM_DEVCFG_EXTBUSWIDTH (1 << 2)
+#define SDRAM_DEVCFG_BANKCOUNT (1 << 3)
+#define SDRAM_DEVCFG_SROMLL (1 << 5)
+#define SDRAM_DEVCFG_CASLAT_2 0x00010000
+#define SDRAM_DEVCFG_RASTOCAS_2 0x00200000
+
+#define GLCONFIG_INIT (1 << 0)
+#define GLCONFIG_MRS (1 << 1)
+#define GLCONFIG_SMEMBUSY (1 << 5)
+#define GLCONFIG_LCR (1 << 6)
+#define GLCONFIG_REARBEN (1 << 7)
+#define GLCONFIG_CLKSHUTDOWN (1 << 30)
+#define GLCONFIG_CKE (1 << 31)
+
+/*
+ * 0x80070000 - 0x8007FFFF: Reserved
+ */
+
+/*
+ * 0x80080000 - 0x8008FFFF: SRAM controller & PCMCIA
+ */
+#define SMC_OFFSET 0x080000
+#define SMC_BASE (EP93XX_AHB_BASE | SMC_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct smc_regs {
+ uint32_t bcr0;
+ uint32_t bcr1;
+ uint32_t bcr2;
+ uint32_t bcr3;
+ uint32_t reserved0[2];
+ uint32_t bcr6;
+ uint32_t bcr7;
+#if defined(CONFIG_EP9315)
+ uint32_t pcattribute;
+ uint32_t pccommon;
+ uint32_t pcio;
+ uint32_t reserved1[5];
+ uint32_t pcmciactrl;
+#endif
+};
+#endif
+
+#define SMC_BCR_IDCY_SHIFT 0
+#define SMC_BCR_WST1_SHIFT 5
+#define SMC_BCR_BLE (1 << 10)
+#define SMC_BCR_WST2_SHIFT 11
+#define SMC_BCR_MW_SHIFT 28
+
+/*
+ * 0x80090000 - 0x8009FFFF: Boot ROM
+ */
+
+/*
+ * 0x800A0000 - 0x800AFFFF: IDE interface
+ */
+
+/*
+ * 0x800B0000 - 0x800BFFFF: VIC1
+ */
+
+/*
+ * 0x800C0000 - 0x800CFFFF: VIC2
+ */
+
+/*
+ * 0x800D0000 - 0x800FFFFF: Reserved
+ */
+
+/*
+ * 0x80800000 - 0x8080FFFF: Reserved
+ */
+
+/*
+ * 0x80810000 - 0x8081FFFF: Timers
+ */
+#define TIMER_OFFSET 0x010000
+#define TIMER_BASE (EP93XX_APB_BASE | TIMER_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct timer {
+ uint32_t load;
+ uint32_t value;
+ uint32_t control;
+ uint32_t clear;
+};
+
+struct timer4 {
+ uint32_t value_low;
+ uint32_t value_high;
+};
+
+struct timer_regs {
+ struct timer timer1;
+ uint32_t reserved0[4];
+ struct timer timer2;
+ uint32_t reserved1[12];
+ struct timer4 timer4;
+ uint32_t reserved2[6];
+ struct timer timer3;
+};
+#endif
+
+/*
+ * 0x80820000 - 0x8082FFFF: I2S
+ */
+#define I2S_OFFSET 0x020000
+#define I2S_BASE (EP93XX_APB_BASE | I2S_OFFSET)
+
+/*
+ * 0x80830000 - 0x8083FFFF: Security
+ */
+#define SECURITY_OFFSET 0x030000
+#define SECURITY_BASE (EP93XX_APB_BASE | SECURITY_OFFSET)
+
+#define EXTENSIONID (SECURITY_BASE + 0x2714)
+
+/*
+ * 0x80840000 - 0x8084FFFF: GPIO
+ */
+#define GPIO_OFFSET 0x040000
+#define GPIO_BASE (EP93XX_APB_BASE | GPIO_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct gpio_int {
+ uint32_t inttype1;
+ uint32_t inttype2;
+ uint32_t eoi;
+ uint32_t inten;
+ uint32_t intsts;
+ uint32_t rawintsts;
+ uint32_t db;
+};
+
+struct gpio_regs {
+ uint32_t padr;
+ uint32_t pbdr;
+ uint32_t pcdr;
+ uint32_t pddr;
+ uint32_t paddr;
+ uint32_t pbddr;
+ uint32_t pcddr;
+ uint32_t pdddr;
+ uint32_t pedr;
+ uint32_t peddr;
+ uint32_t reserved0[2];
+ uint32_t pfdr;
+ uint32_t pfddr;
+ uint32_t pgdr;
+ uint32_t pgddr;
+ uint32_t phdr;
+ uint32_t phddr;
+ uint32_t reserved1;
+ uint32_t finttype1;
+ uint32_t finttype2;
+ uint32_t reserved2;
+ struct gpio_int pfint;
+ uint32_t reserved3[10];
+ struct gpio_int paint;
+ struct gpio_int pbint;
+ uint32_t eedrive;
+};
+#endif
+
+/*
+ * 0x80850000 - 0x8087FFFF: Reserved
+ */
+
+/*
+ * 0x80880000 - 0x8088FFFF: AAC
+ */
+#define AAC_OFFSET 0x080000
+#define AAC_BASE (EP93XX_APB_BASE | AAC_OFFSET)
+
+/*
+ * 0x80890000 - 0x8089FFFF: Reserved
+ */
+
+/*
+ * 0x808A0000 - 0x808AFFFF: SPI
+ */
+#define SPI_OFFSET 0x0A0000
+#define SPI_BASE (EP93XX_APB_BASE | SPI_OFFSET)
+
+/*
+ * 0x808B0000 - 0x808BFFFF: IrDA
+ */
+#define IRDA_OFFSET 0x0B0000
+#define IRDA_BASE (EP93XX_APB_BASE | IRDA_OFFSET)
+
+/*
+ * 0x808C0000 - 0x808CFFFF: UART1
+ */
+#define UART1_OFFSET 0x0C0000
+#define UART1_BASE (EP93XX_APB_BASE | UART1_OFFSET)
+
+/*
+ * 0x808D0000 - 0x808DFFFF: UART2
+ */
+#define UART2_OFFSET 0x0D0000
+#define UART2_BASE (EP93XX_APB_BASE | UART2_OFFSET)
+
+/*
+ * 0x808E0000 - 0x808EFFFF: UART3
+ */
+#define UART3_OFFSET 0x0E0000
+#define UART3_BASE (EP93XX_APB_BASE | UART3_OFFSET)
+
+/*
+ * 0x808F0000 - 0x808FFFFF: Key Matrix
+ */
+#define KEY_OFFSET 0x0F0000
+#define KEY_BASE (EP93XX_APB_BASE | KEY_OFFSET)
+
+/*
+ * 0x80900000 - 0x8090FFFF: Touchscreen
+ */
+#define TOUCH_OFFSET 0x900000
+#define TOUCH_BASE (EP93XX_APB_BASE | TOUCH_OFFSET)
+
+/*
+ * 0x80910000 - 0x8091FFFF: Pulse Width Modulation
+ */
+#define PWM_OFFSET 0x910000
+#define PWM_BASE (EP93XX_APB_BASE | PWM_OFFSET)
+
+/*
+ * 0x80920000 - 0x8092FFFF: Real time clock
+ */
+#define RTC_OFFSET 0x920000
+#define RTC_BASE (EP93XX_APB_BASE | RTC_OFFSET)
+
+/*
+ * 0x80930000 - 0x8093FFFF: Syscon
+ */
+#define SYSCON_OFFSET 0x930000
+#define SYSCON_BASE (EP93XX_APB_BASE | SYSCON_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct syscon_regs {
+ uint32_t pwrsts;
+ uint32_t pwrcnt;
+ uint32_t halt;
+ uint32_t stby;
+ uint32_t reserved0[2];
+ uint32_t teoi;
+ uint32_t stfclr;
+ uint32_t clkset1;
+ uint32_t clkset2;
+ uint32_t reserved1[6];
+ uint32_t scratch0;
+ uint32_t scratch1;
+ uint32_t reserved2[2];
+ uint32_t apbwait;
+ uint32_t bustmstrarb;
+ uint32_t bootmodeclr;
+ uint32_t reserved3[9];
+ uint32_t devicecfg;
+ uint32_t vidclkdiv;
+ uint32_t mirclkdiv;
+ uint32_t i2sclkdiv;
+ uint32_t keytchclkdiv;
+ uint32_t chipid;
+ uint32_t syscfg;
+ uint32_t reserved4[8];
+ uint32_t sysswlock;
+};
+#else
+#define SYSCON_SCRATCH0 (SYSCON_BASE + 0x0040)
+#endif
+
+#define SYSCON_PWRCNT_UART_BAUD (1 << 29)
+
+#define SYSCON_CLKSET_PLL_X2IPD_SHIFT 0
+#define SYSCON_CLKSET_PLL_X2FBD2_SHIFT 5
+#define SYSCON_CLKSET_PLL_X1FBD1_SHIFT 11
+#define SYSCON_CLKSET_PLL_PS_SHIFT 16
+#define SYSCON_CLKSET1_PCLK_DIV_SHIFT 18
+#define SYSCON_CLKSET1_HCLK_DIV_SHIFT 20
+#define SYSCON_CLKSET1_NBYP1 (1 << 23)
+#define SYSCON_CLKSET1_FCLK_DIV_SHIFT 25
+
+#define SYSCON_CLKSET2_PLL2_EN (1 << 18)
+#define SYSCON_CLKSET2_NBYP2 (1 << 19)
+#define SYSCON_CLKSET2_USB_DIV_SHIFT 28
+
+#define SYSCON_CHIPID_REV_MASK 0xF0000000
+#define SYSCON_DEVICECFG_SWRST (1 << 31)
+
+/*
+ * 0x80930000 - 0x8093FFFF: Watchdog Timer
+ */
+#define WATCHDOG_OFFSET 0x940000
+#define WATCHDOG_BASE (EP93XX_APB_BASE | WATCHDOG_OFFSET)
+
+/*
+ * 0x80950000 - 0x9000FFFF: Reserved
+ */
diff --git a/include/common.h b/include/common.h
index 391790a..f2a7067 100644
--- a/include/common.h
+++ b/include/common.h
@@ -502,7 +502,8 @@ ulong get_PCI_freq (void);
#endif
#if defined(CONFIG_S3C24X0) || \
defined(CONFIG_LH7A40X) || \
- defined(CONFIG_S3C6400)
+ defined(CONFIG_S3C6400) || \
+ defined(CONFIG_EP93XX)
ulong get_FCLK (void);
ulong get_HCLK (void);
ulong get_PCLK (void);
--
1.6.3.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH 2/3] Add EP93xx ethernet driver
[not found] <cover.1264351928.git.matthias@kaehlcke.net>
2010-01-24 16:56 ` [U-Boot] [PATCH 1/3] ARM: Add support for EP93xx SoCs Matthias Kaehlcke
@ 2010-01-24 16:56 ` Matthias Kaehlcke
2010-01-25 4:09 ` Ben Warren
2010-01-24 16:56 ` [U-Boot] [PATCH 3/3] Add support for EDB93xx boards Matthias Kaehlcke
2 siblings, 1 reply; 12+ messages in thread
From: Matthias Kaehlcke @ 2010-01-24 16:56 UTC (permalink / raw)
To: u-boot
Added ethernet driver for EP93xx SoCs
Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
---
drivers/net/Makefile | 1 +
drivers/net/ep93xx_eth.c | 654 ++++++++++++++++++++++++++++++++++++++++++++++
drivers/net/ep93xx_eth.h | 144 ++++++++++
include/common.h | 5 +
include/netdev.h | 1 +
5 files changed, 805 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/ep93xx_eth.c
create mode 100644 drivers/net/ep93xx_eth.h
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 904727e..dc3107c 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -37,6 +37,7 @@ COBJS-$(CONFIG_DNET) += dnet.o
COBJS-$(CONFIG_E1000) += e1000.o
COBJS-$(CONFIG_EEPRO100) += eepro100.o
COBJS-$(CONFIG_ENC28J60) += enc28j60.o
+COBJS-$(CONFIG_EP93XX) += ep93xx_eth.o
COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o
COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
COBJS-$(CONFIG_FTMAC100) += ftmac100.o
diff --git a/drivers/net/ep93xx_eth.c b/drivers/net/ep93xx_eth.c
new file mode 100644
index 0000000..33d14df
--- /dev/null
+++ b/drivers/net/ep93xx_eth.c
@@ -0,0 +1,654 @@
+/*
+ * Cirrus Logic EP93xx ethernet MAC / MII driver.
+ *
+ * Copyright (C) 2010, 2009
+ * Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+ *
+ * Based on the original eth.[ch] Cirrus Logic EP93xx Rev D. Ethernet Driver,
+ * which is
+ *
+ * (C) Copyright 2002 2003
+ * Adam Bezanson, Network Audio Technologies, Inc.
+ * <bezanson@netaudiotech.com>
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <command.h>
+#include <common.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <linux/types.h>
+#include "ep93xx_eth.h"
+
+#define GET_PRIV(eth_dev) ((struct ep93xx_priv *)eth_dev->priv)
+#define GET_REGS(eth_dev) (GET_PRIV(eth_dev)->regs)
+
+/* ep93xx_miiphy ops forward declarations */
+static int ep93xx_miiphy_read(char * const dev, unsigned char const addr,
+ unsigned char const reg, unsigned short * const value);
+static int ep93xx_miiphy_write(char * const dev, unsigned char const addr,
+ unsigned char const reg, unsigned short const value);
+
+#if defined(EP93XX_MAC_DEBUG)
+/**
+ * Dump ep93xx_mac values to the terminal.
+ */
+inline void dump_dev(struct eth_device *dev)
+{
+ struct ep93xx_priv *priv = GET_PRIV(dev);
+ int i;
+
+ printf("\ndump_dev()\n");
+ printf(" rx_dq.base %08X\n", (uint32_t)priv->rx_dq.base);
+ printf(" rx_dq.current %08X\n", (uint32_t)priv->rx_dq.current);
+ printf(" rx_dq.end %08X\n", (uint32_t)priv->rx_dq.end);
+ printf(" rx_sq.base %08X\n", (uint32_t)priv->rx_sq.base);
+ printf(" rx_sq.current %08X\n", (uint32_t)priv->rx_sq.current);
+ printf(" rx_sq.end %08X\n", (uint32_t)priv->rx_sq.end);
+
+ for (i = 0; i < NUMRXDESC; i++)
+ printf(" rx_buffer[%2.d] %08X\n", i,
+ (uint32_t)NetRxPackets[i]);
+
+ printf(" tx_dq.base %08X\n", (uint32_t)priv->tx_dq.base);
+ printf(" tx_dq.current %08X\n", (uint32_t)priv->tx_dq.current);
+ printf(" tx_dq.end %08X\n", (uint32_t)priv->tx_dq.end);
+ printf(" tx_sq.base %08X\n", (uint32_t)priv->tx_sq.base);
+ printf(" tx_sq.current %08X\n", (uint32_t)priv->tx_sq.current);
+ printf(" tx_sq.end %08X\n", (uint32_t)priv->tx_sq.end);
+}
+
+/**
+ * Dump all RX status queue entries to the terminal.
+ */
+inline void dump_rx_status_queue(struct eth_device *dev)
+{
+ struct ep93xx_priv *priv = GET_PRIV(dev);
+ int i;
+
+ printf("\ndump_rx_status_queue()\n");
+ printf(" descriptor address word1 word2\n");
+ for (i = 0; i < NUMRXDESC; i++) {
+ printf(" [ %08X ] %08X %08X\n",
+ (uint32_t)(priv->rx_sq.base + i),
+ (uint32_t)(priv->rx_sq.base + i)->word1,
+ (uint32_t)(priv->rx_sq.base + i)->word2);
+ }
+}
+
+/**
+ * Dump all RX descriptor queue entries to the terminal.
+ */
+inline void dump_rx_descriptor_queue(struct eth_device *dev)
+{
+ struct ep93xx_priv *priv = GET_PRIV(dev);
+ int i;
+
+ printf("\ndump_rx_descriptor_queue()\n");
+ printf(" descriptor address word1 word2\n");
+ for (i = 0; i < NUMRXDESC; i++) {
+ printf(" [ %08X ] %08X %08X\n",
+ (uint32_t)(priv->rx_dq.base + i),
+ (uint32_t)(priv->rx_dq.base + i)->word1,
+ (uint32_t)(priv->rx_dq.base + i)->word2);
+ }
+}
+
+/**
+ * Dump all TX descriptor queue entries to the terminal.
+ */
+inline void dump_tx_descriptor_queue(struct eth_device *dev)
+{
+ struct ep93xx_priv *priv = GET_PRIV(dev);
+ int i;
+
+ printf("\ndump_tx_descriptor_queue()\n");
+ printf(" descriptor address word1 word2\n");
+ for (i = 0; i < NUMTXDESC; i++) {
+ printf(" [ %08X ] %08X %08X\n",
+ (uint32_t)(priv->tx_dq.base + i),
+ (uint32_t)(priv->tx_dq.base + i)->word1,
+ (uint32_t)(priv->tx_dq.base + i)->word2);
+ }
+}
+
+/**
+ * Dump all TX status queue entries to the terminal.
+ */
+inline void dump_tx_status_queue(struct eth_device *dev)
+{
+ struct ep93xx_priv *priv = GET_PRIV(dev);
+ int i;
+
+ printf("\ndump_tx_status_queue()\n");
+ printf(" descriptor address word1\n");
+ for (i = 0; i < NUMTXDESC; i++) {
+ printf(" [ %08X ] %08X\n",
+ (uint32_t)(priv->rx_sq.base + i),
+ (uint32_t)(priv->rx_sq.base + i)->word1);
+ }
+}
+#else
+#define dump_dev(x)
+#define dump_rx_descriptor_queue(x)
+#define dump_rx_status_queue(x)
+#define dump_tx_descriptor_queue(x)
+#define dump_tx_status_queue(x)
+#endif /* defined(EP93XX_MAC_DEBUG) */
+
+/**
+ * Reset the EP93xx MAC by twiddling the soft reset bit and spinning until
+ * it's cleared.
+ */
+static void ep93xx_mac_reset(struct eth_device *dev)
+{
+ struct mac_regs *mac = GET_REGS(dev);
+ uint32_t value;
+
+ debug("+ep93xx_mac_reset");
+
+ value = readl(&mac->selfctl);
+ value |= SELFCTL_RESET;
+ writel(value, &mac->selfctl);
+
+ while (readl(&mac->selfctl) & SELFCTL_RESET)
+ ; /* noop */
+
+ debug("-ep93xx_mac_reset");
+}
+
+/* Eth device open */
+static int ep93xx_eth_open(struct eth_device *dev, bd_t *bd)
+{
+ struct ep93xx_priv *priv = GET_PRIV(dev);
+ struct mac_regs *mac = GET_REGS(dev);
+ uchar *mac_addr = dev->enetaddr;
+ int i;
+
+ debug("+ep93xx_eth_open");
+
+ /* Reset the MAC */
+ ep93xx_mac_reset(dev);
+
+ /* Reset the descriptor queues' current and end address values */
+ priv->tx_dq.current = priv->tx_dq.base;
+ priv->tx_dq.end = (priv->tx_dq.base + NUMTXDESC);
+
+ priv->tx_sq.current = priv->tx_sq.base;
+ priv->tx_sq.end = (priv->tx_sq.base + NUMTXDESC);
+
+ priv->rx_dq.current = priv->rx_dq.base;
+ priv->rx_dq.end = (priv->rx_dq.base + NUMRXDESC);
+
+ priv->rx_sq.current = priv->rx_sq.base;
+ priv->rx_sq.end = (priv->rx_sq.base + NUMRXDESC);
+
+ /*
+ * Set the transmit descriptor and status queues' base address,
+ * current address, and length registers. Set the maximum frame
+ * length and threshold. Enable the transmit descriptor processor.
+ */
+ writel((uint32_t)priv->tx_dq.base, &mac->txdq.badd);
+ writel((uint32_t)priv->tx_dq.base, &mac->txdq.curadd);
+ writel(sizeof(struct tx_descriptor) * NUMTXDESC, &mac->txdq.blen);
+
+ writel((uint32_t)priv->tx_sq.base, &mac->txstsq.badd);
+ writel((uint32_t)priv->tx_sq.base, &mac->txstsq.curadd);
+ writel(sizeof(struct tx_status) * NUMTXDESC, &mac->txstsq.blen);
+
+ writel(0x00040000, &mac->txdthrshld);
+ writel(0x00040000, &mac->txststhrshld);
+
+ writel((TXSTARTMAX << 0) | (PKTSIZE_ALIGN << 16), &mac->maxfrmlen);
+ writel(BMCTL_TXEN, &mac->bmctl);
+
+ /*
+ * Set the receive descriptor and status queues' base address,
+ * current address, and length registers. Enable the receive
+ * descriptor processor.
+ */
+ writel((uint32_t)priv->rx_dq.base, &mac->rxdq.badd);
+ writel((uint32_t)priv->rx_dq.base, &mac->rxdq.curadd);
+ writel(sizeof(struct rx_descriptor) * NUMRXDESC, &mac->rxdq.blen);
+
+ writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.badd);
+ writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.curadd);
+ writel(sizeof(struct rx_status) * NUMRXDESC, &mac->rxstsq.blen);
+
+ writel(0x00040000, &mac->rxdthrshld);
+
+ writel(BMCTL_RXEN, &mac->bmctl);
+
+ writel(0x00040000, &mac->rxststhrshld);
+
+ /* Wait until the receive descriptor processor is active */
+ while (!(readl(&mac->bmsts) & BMSTS_RXACT))
+ ; /* noop */
+
+ /*
+ * Initialize the RX descriptor queue. Clear the TX descriptor queue.
+ * Clear the RX and TX status queues. Enqueue the RX descriptor and
+ * status entries to the MAC.
+ */
+ for (i = 0; i < NUMRXDESC; i++) {
+ /* set buffer address */
+ (priv->rx_dq.base + i)->word1 = (uint32_t)NetRxPackets[i];
+
+ /* set buffer length, clear buffer index and NSOF */
+ (priv->rx_dq.base + i)->word2 = PKTSIZE_ALIGN;
+ }
+
+ memset(priv->tx_dq.base, 0,
+ (sizeof(struct tx_descriptor) * NUMTXDESC));
+ memset(priv->rx_sq.base, 0,
+ (sizeof(struct rx_status) * NUMRXDESC));
+ memset(priv->tx_sq.base, 0,
+ (sizeof(struct tx_status) * NUMTXDESC));
+
+ writel(NUMRXDESC, &mac->rxdqenq);
+ writel(NUMRXDESC, &mac->rxstsqenq);
+
+ /* Set the primary MAC address */
+ writel(AFP_IAPRIMARY, &mac->afp);
+ writel(mac_addr[0] | (mac_addr[1] << 8) |
+ (mac_addr[2] << 16) | (mac_addr[3] << 24),
+ &mac->indad);
+ writel(mac_addr[4] | (mac_addr[5] << 8), &mac->indad_upper);
+
+ /* Turn on RX and TX */
+ writel(RXCTL_IA0 | RXCTL_BA | RXCTL_SRXON |
+ RXCTL_RCRCA | RXCTL_MA, &mac->rxctl);
+ writel(TXCTL_STXON, &mac->txctl);
+
+ /* Dump data structures if we're debugging */
+ dump_dev(dev);
+ dump_rx_descriptor_queue(dev);
+ dump_rx_status_queue(dev);
+ dump_tx_descriptor_queue(dev);
+ dump_tx_status_queue(dev);
+
+ debug("-ep93xx_eth_open");
+
+ return 1;
+}
+
+/**
+ * Halt EP93xx MAC transmit and receive by clearing the TxCTL and RxCTL
+ * registers.
+ */
+static void ep93xx_eth_close(struct eth_device *dev)
+{
+ struct mac_regs *mac = GET_REGS(dev);
+
+ debug("+ep93xx_eth_close");
+
+ writel(0x00000000, &mac->rxctl);
+ writel(0x00000000, &mac->txctl);
+
+ debug("-ep93xx_eth_close");
+}
+
+/**
+ * Copy a frame of data from the MAC into the protocol layer for further
+ * processing.
+ */
+static int ep93xx_eth_rcv_packet(struct eth_device *dev)
+{
+ struct mac_regs *mac = GET_REGS(dev);
+ struct ep93xx_priv *priv = GET_PRIV(dev);
+ int len = -1;
+
+ debug("+ep93xx_eth_rcv_packet");
+
+ if (RX_STATUS_RFP(priv->rx_sq.current)) {
+ if (RX_STATUS_RWE(priv->rx_sq.current)) {
+ /*
+ * We have a good frame. Extract the frame's length
+ * from the current rx_status_queue entry, and copy
+ * the frame's data into NetRxPackets[] of the
+ * protocol stack. We track the total number of
+ * bytes in the frame (nbytes_frame) which will be
+ * used when we pass the data off to the protocol
+ * layer via NetReceive().
+ */
+ len = RX_STATUS_FRAME_LEN(priv->rx_sq.current);
+
+ NetReceive((uchar *)priv->rx_dq.current->word1, len);
+
+ debug("reporting %d bytes...\n", len);
+ } else {
+ /* Do we have an erroneous packet? */
+ error("packet rx error, status %08X %08X",
+ priv->rx_sq.current->word1,
+ priv->rx_sq.current->word2);
+ dump_rx_descriptor_queue(dev);
+ dump_rx_status_queue(dev);
+ }
+
+ /*
+ * Clear the associated status queue entry, and
+ * increment our current pointers to the next RX
+ * descriptor and status queue entries (making sure
+ * we wrap properly).
+ */
+ memset((void *)priv->rx_sq.current, 0,
+ sizeof(struct rx_status));
+
+ priv->rx_sq.current++;
+ if (priv->rx_sq.current >= priv->rx_sq.end)
+ priv->rx_sq.current = priv->rx_sq.base;
+
+ priv->rx_dq.current++;
+ if (priv->rx_dq.current >= priv->rx_dq.end)
+ priv->rx_dq.current = priv->rx_dq.base;
+
+ /*
+ * Finally, return the RX descriptor and status entries
+ * back to the MAC engine, and loop again, checking for
+ * more descriptors to process.
+ */
+ writel(1, &mac->rxdqenq);
+ writel(1, &mac->rxstsqenq);
+ } else {
+ len = 0;
+ }
+
+ debug("-ep93xx_eth_rcv_packet %d", len);
+ return len;
+}
+
+/**
+ * Send a block of data via ethernet.
+ */
+static int ep93xx_eth_send_packet(struct eth_device *dev,
+ volatile void * const packet, int const length)
+{
+ struct mac_regs *mac = GET_REGS(dev);
+ struct ep93xx_priv *priv = GET_PRIV(dev);
+ int ret = -1;
+
+ debug("+ep93xx_eth_send_packet");
+
+ /* Parameter check */
+ BUG_ON(packet == NULL);
+
+ /*
+ * Initialize the TX descriptor queue with the new packet's info.
+ * Clear the associated status queue entry. Enqueue the packet
+ * to the MAC for transmission.
+ */
+
+ /* set buffer address */
+ priv->tx_dq.current->word1 = (uint32_t)packet;
+
+ /* set buffer length and EOF bit */
+ priv->tx_dq.current->word2 = length | TX_DESC_EOF;
+
+ /* clear tx status */
+ priv->tx_sq.current->word1 = 0;
+
+ /* enqueue the TX descriptor */
+ writel(1, &mac->txdqenq);
+
+ /* wait for the frame to become processed */
+ while (!TX_STATUS_TXFP(priv->tx_sq.current))
+ ; /* noop */
+
+ if (!TX_STATUS_TXWE(priv->tx_sq.current)) {
+ error("packet tx error, status %08X",
+ priv->tx_sq.current->word1);
+ dump_tx_descriptor_queue(dev);
+ dump_tx_status_queue(dev);
+
+ /* TODO: Add better error handling? */
+ goto eth_send_failed_0;
+ }
+
+ ret = 0;
+ /* Fall through */
+
+eth_send_failed_0:
+ debug("-ep93xx_eth_send_packet %d", ret);
+ return ret;
+}
+
+#if defined(CONFIG_MII)
+int ep93xx_miiphy_initialize(bd_t * const bd)
+{
+ miiphy_register("ep93xx_eth0", ep93xx_miiphy_read, ep93xx_miiphy_write);
+ return 0;
+}
+#endif
+
+/**
+ * Initialize the EP93xx MAC. The MAC hardware is reset. Buffers are
+ * allocated, if necessary, for the TX and RX descriptor and status queues,
+ * as well as for received packets. The EP93XX MAC hardware is initialized.
+ * Transmit and receive operations are enabled.
+ */
+int ep93xx_eth_initialize(u8 dev_num, int base_addr)
+{
+ int ret = -1;
+ struct eth_device *dev;
+ struct ep93xx_priv *priv;
+
+ debug("+ep93xx_eth_initialize");
+
+ priv = malloc(sizeof(*priv));
+ if (!priv) {
+ error("malloc() failed");
+ goto eth_init_failed_0;
+ }
+ memset(priv, 0, sizeof(*priv));
+
+ priv->regs = (struct mac_regs *)base_addr;
+
+ priv->tx_dq.base = calloc(NUMTXDESC,
+ sizeof(struct tx_descriptor));
+ if (priv->tx_dq.base == NULL) {
+ error("calloc() failed");
+ goto eth_init_failed_1;
+ }
+
+ priv->tx_sq.base = calloc(NUMTXDESC,
+ sizeof(struct tx_status));
+ if (priv->tx_sq.base == NULL) {
+ error("calloc() failed");
+ goto eth_init_failed_2;
+ }
+
+ priv->rx_dq.base = calloc(NUMRXDESC,
+ sizeof(struct rx_descriptor));
+ if (priv->rx_dq.base == NULL) {
+ error("calloc() failed");
+ goto eth_init_failed_3;
+ }
+
+ priv->rx_sq.base = calloc(NUMRXDESC,
+ sizeof(struct rx_status));
+ if (priv->rx_sq.base == NULL) {
+ error("calloc() failed");
+ goto eth_init_failed_4;
+ }
+
+ dev = malloc(sizeof *dev);
+ if (dev == NULL) {
+ error("malloc() failed");
+ goto eth_init_failed_5;
+ }
+ memset(dev, 0, sizeof *dev);
+
+ dev->iobase = base_addr;
+ dev->priv = priv;
+ dev->init = ep93xx_eth_open;
+ dev->halt = ep93xx_eth_close;
+ dev->send = ep93xx_eth_send_packet;
+ dev->recv = ep93xx_eth_rcv_packet;
+
+ sprintf(dev->name, "ep93xx_eth-%hu", dev_num);
+
+ eth_register(dev);
+
+ /* Done! */
+ ret = 0;
+ goto eth_init_done;
+
+eth_init_failed_5:
+ free(priv->rx_sq.base);
+ /* Fall through */
+
+eth_init_failed_4:
+ free(priv->rx_dq.base);
+ /* Fall through */
+
+eth_init_failed_3:
+ free(priv->tx_sq.base);
+ /* Fall through */
+
+eth_init_failed_2:
+ free(priv->tx_dq.base);
+ /* Fall through */
+
+eth_init_failed_1:
+ free(priv);
+ /* Fall through */
+
+eth_init_failed_0:
+ /* Fall through */
+
+eth_init_done:
+ debug("-ep93xx_eth_initialize %d", ret);
+ return ret;
+}
+
+#if defined(CONFIG_MII)
+
+/**
+ * Maximum MII address we support
+ */
+#define MII_ADDRESS_MAX 31
+
+/**
+ * Maximum MII register address we support
+ */
+#define MII_REGISTER_MAX 31
+
+/**
+ * Read a 16-bit value from an MII register.
+ */
+static int ep93xx_miiphy_read(char * const dev, unsigned char const addr,
+ unsigned char const reg, unsigned short * const value)
+{
+ struct mac_regs *mac = (struct mac_regs *)MAC_BASE;
+ int ret = -1;
+ uint32_t self_ctl;
+
+ debug("+ep93xx_miiphy_read");
+
+ /* Parameter checks */
+ BUG_ON(dev == NULL);
+ BUG_ON(addr > MII_ADDRESS_MAX);
+ BUG_ON(reg > MII_REGISTER_MAX);
+ BUG_ON(value == NULL);
+
+ /*
+ * Save the current SelfCTL register value. Set MAC to suppress
+ * preamble bits. Wait for any previous MII command to complete
+ * before issuing the new command.
+ */
+ self_ctl = readl(&mac->selfctl);
+#if defined(CONFIG_MII_SUPPRESS_PREAMBLE)
+ writel(self_ctl & ~(1 << 8), &mac->selfctl);
+#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
+
+ while (readl(&mac->miists) & MIISTS_BUSY)
+ ; /* noop */
+
+ /*
+ * Issue the MII 'read' command. Wait for the command to complete.
+ * Read the MII data value.
+ */
+ writel(MIICMD_OPCODE_READ | ((uint32_t)addr << 5) | (uint32_t)reg,
+ &mac->miicmd);
+ while (readl(&mac->miists) & MIISTS_BUSY)
+ ; /* noop */
+
+ *value = (unsigned short)readl(&mac->miidata);
+
+ /* Restore the saved SelfCTL value and return. */
+ writel(self_ctl, &mac->selfctl);
+
+ ret = 0;
+ /* Fall through */
+
+ debug("-ep93xx_miiphy_read");
+ return ret;
+}
+
+/**
+ * Write a 16-bit value to an MII register.
+ */
+static int ep93xx_miiphy_write(char * const dev, unsigned char const addr,
+ unsigned char const reg, unsigned short const value)
+{
+ struct mac_regs *mac = (struct mac_regs *)MAC_BASE;
+ int ret = -1;
+ uint32_t self_ctl;
+
+ debug("+ep93xx_miiphy_write");
+
+ /* Parameter checks */
+ BUG_ON(dev == NULL);
+ BUG_ON(addr > MII_ADDRESS_MAX);
+ BUG_ON(reg > MII_REGISTER_MAX);
+
+ /*
+ * Save the current SelfCTL register value. Set MAC to suppress
+ * preamble bits. Wait for any previous MII command to complete
+ * before issuing the new command.
+ */
+ self_ctl = readl(&mac->selfctl);
+#if defined(CONFIG_MII_SUPPRESS_PREAMBLE)
+ writel(self_ctl & ~(1 << 8), &mac->selfctl);
+#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
+
+ while (readl(&mac->miists) & MIISTS_BUSY)
+ ; /* noop */
+
+ /* Issue the MII 'write' command. Wait for the command to complete. */
+ writel((uint32_t)value, &mac->miidata);
+ writel(MIICMD_OPCODE_WRITE | ((uint32_t)addr << 5) | (uint32_t)reg,
+ &mac->miicmd);
+ while (readl(&mac->miists) & MIISTS_BUSY)
+ ; /* noop */
+
+ /* Restore the saved SelfCTL value and return. */
+ writel(self_ctl, &mac->selfctl);
+
+ ret = 0;
+ /* Fall through */
+
+ debug("-ep93xx_miiphy_write");
+ return ret;
+}
+#endif /* defined(CONFIG_MII) */
diff --git a/drivers/net/ep93xx_eth.h b/drivers/net/ep93xx_eth.h
new file mode 100644
index 0000000..5f7bf13
--- /dev/null
+++ b/drivers/net/ep93xx_eth.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ETH_H
+#define _ETH_H
+
+#include <net.h>
+
+/**
+ * #define this to dump device status and queue info during initialization and
+ * following errors.
+ */
+#undef EP93XX_MAC_DEBUG
+
+/**
+ * Number of descriptor and status entries in our RX queues.
+ * It must be power of 2 !
+ */
+#define NUMRXDESC PKTBUFSRX
+
+/**
+ * Number of descriptor and status entries in our TX queues.
+ */
+#define NUMTXDESC 1
+
+/**
+ * 944 = (1024 - 64) - 16, Fifo size - Minframesize - 16 (Chip FACT)
+ */
+#define TXSTARTMAX 944
+
+/**
+ * Receive descriptor queue entry
+ */
+struct rx_descriptor {
+ uint32_t word1;
+ uint32_t word2;
+};
+
+/**
+ * Receive status queue entry
+ */
+struct rx_status {
+ uint32_t word1;
+ uint32_t word2;
+};
+
+#define RX_STATUS_RWE(rx_status) ((rx_status->word1 >> 30) & 0x01)
+#define RX_STATUS_RFP(rx_status) ((rx_status->word1 >> 31) & 0x01)
+#define RX_STATUS_FRAME_LEN(rx_status) (rx_status->word2 & 0xFFFF)
+
+/**
+ * Transmit descriptor queue entry
+ */
+struct tx_descriptor {
+ uint32_t word1;
+ uint32_t word2;
+};
+
+#define TX_DESC_EOF (1 << 31)
+
+/**
+ * Transmit status queue entry
+ */
+struct tx_status {
+ uint32_t word1;
+};
+
+#define TX_STATUS_TXWE(tx_status) (((tx_status)->word1 >> 30) & 0x01)
+#define TX_STATUS_TXFP(tx_status) (((tx_status)->word1 >> 31) & 0x01)
+
+/**
+ * Transmit descriptor queue
+ */
+struct tx_descriptor_queue {
+ struct tx_descriptor *base;
+ struct tx_descriptor *current;
+ struct tx_descriptor *end;
+};
+
+/**
+ * Transmit status queue
+ */
+struct tx_status_queue {
+ struct tx_status *base;
+ volatile struct tx_status *current;
+ struct tx_status *end;
+};
+
+/**
+ * Receive descriptor queue
+ */
+struct rx_descriptor_queue {
+ struct rx_descriptor *base;
+ struct rx_descriptor *current;
+ struct rx_descriptor *end;
+};
+
+/**
+ * Receive status queue
+ */
+struct rx_status_queue {
+ struct rx_status *base;
+ volatile struct rx_status *current;
+ struct rx_status *end;
+};
+
+/**
+ * EP93xx MAC private data structure
+ */
+struct ep93xx_priv {
+ struct rx_descriptor_queue rx_dq;
+ struct rx_status_queue rx_sq;
+ void *rx_buffer[NUMRXDESC];
+
+ struct tx_descriptor_queue tx_dq;
+ struct tx_status_queue tx_sq;
+
+ struct mac_regs *regs;
+};
+
+#endif
diff --git a/include/common.h b/include/common.h
index f2a7067..c0dfc45 100644
--- a/include/common.h
+++ b/include/common.h
@@ -123,6 +123,11 @@ typedef volatile unsigned char vu_char;
#define debugX(level,fmt,args...)
#endif /* DEBUG */
+#define error(fmt, args...) do { \
+ printf("ERROR: " fmt "\nat %s:%d/%s()\n", \
+ ##args, __FILE__, __LINE__, __func__); \
+} while (0)
+
#ifndef BUG
#define BUG() do { \
printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \
diff --git a/include/netdev.h b/include/netdev.h
index a9d5ec9..1e0484f 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -49,6 +49,7 @@ int davinci_emac_initialize(void);
int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
int e1000_initialize(bd_t *bis);
int eepro100_initialize(bd_t *bis);
+int ep93xx_eth_initialize(u8 dev_num, int base_addr);
int eth_3com_initialize (bd_t * bis);
int fec_initialize (bd_t *bis);
int fecmxc_initialize (bd_t *bis);
--
1.6.3.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH 3/3] Add support for EDB93xx boards
[not found] <cover.1264351928.git.matthias@kaehlcke.net>
2010-01-24 16:56 ` [U-Boot] [PATCH 1/3] ARM: Add support for EP93xx SoCs Matthias Kaehlcke
2010-01-24 16:56 ` [U-Boot] [PATCH 2/3] Add EP93xx ethernet driver Matthias Kaehlcke
@ 2010-01-24 16:56 ` Matthias Kaehlcke
2010-01-31 19:00 ` Tom
2 siblings, 1 reply; 12+ messages in thread
From: Matthias Kaehlcke @ 2010-01-24 16:56 UTC (permalink / raw)
To: u-boot
Added support for the following EDB93xx boards:
EDB9301
EDB9302
EDB9302A
EDB9307
EDB9307A
EDB93012
EDB9315
EDB9315A
Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
---
MAINTAINERS | 10 ++
MAKEALL | 8 ++
Makefile | 10 ++
board/edb93xx/Makefile | 50 ++++++++
board/edb93xx/config.mk | 33 +++++
board/edb93xx/early_udelay.h | 34 +++++
board/edb93xx/edb93xx.c | 109 +++++++++++++++++
board/edb93xx/flash_cfg.c | 38 ++++++
board/edb93xx/pll_cfg.c | 58 +++++++++
board/edb93xx/pll_cfg.h | 72 +++++++++++
board/edb93xx/sdram_cfg.c | 117 ++++++++++++++++++
board/edb93xx/sdram_cfg.h | 144 ++++++++++++++++++++++
include/configs/edb93xx.h | 273 ++++++++++++++++++++++++++++++++++++++++++
13 files changed, 956 insertions(+), 0 deletions(-)
create mode 100644 board/edb93xx/Makefile
create mode 100644 board/edb93xx/config.mk
create mode 100644 board/edb93xx/early_udelay.h
create mode 100644 board/edb93xx/edb93xx.c
create mode 100644 board/edb93xx/flash_cfg.c
create mode 100644 board/edb93xx/pll_cfg.c
create mode 100644 board/edb93xx/pll_cfg.h
create mode 100644 board/edb93xx/sdram_cfg.c
create mode 100644 board/edb93xx/sdram_cfg.h
create mode 100644 include/configs/edb93xx.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 3879fde..23523f3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -598,6 +598,16 @@ Gary Jennejohn <garyj@denx.de>
smdk2400 ARM920T
trab ARM920T
+Matthias Kaehlcke <matthias@kaehlcke.net>
+ edb9301 ARM920T (EP9301)
+ edb9302 ARM920T (EP9302)
+ edb9302a ARM920T (EP9302)
+ edb9307 ARM920T (EP9307)
+ edb9307a ARM920T (EP9307)
+ edb9312 ARM920T (EP9312)
+ edb9315 ARM920T (EP9315)
+ edb9315a ARM920T (EP9315)
+
Konstantin Kletschke <kletschke@synertronixx.de>
scb9328 ARM920T
diff --git a/MAKEALL b/MAKEALL
index dd635bd..c3ef638 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -554,6 +554,14 @@ LIST_ARM9=" \
cp946es \
cp966 \
da830evm \
+ edb9301 \
+ edb9302 \
+ edb9302a \
+ edb9307 \
+ edb9307a \
+ edb9312 \
+ edb9315 \
+ edb9315a \
imx27lite \
lpd7a400 \
mv88f6281gtw_ge \
diff --git a/Makefile b/Makefile
index 793fcec..a1db2f9 100644
--- a/Makefile
+++ b/Makefile
@@ -2404,6 +2404,16 @@ caddy2_config \
vme8349_config: unconfig
@$(MKCONFIG) -t $(@:_config=) vme8349 ppc mpc83xx vme8349 esd
+edb9301_config \
+edb9302_config \
+edb9302a_config \
+edb9307_config \
+edb9307a_config \
+edb9312_config \
+edb9315_config \
+edb9315a_config: unconfig
+ @$(MKCONFIG) -t $(@:_config=) edb93xx arm arm920t edb93xx NULL ep93xx
+
#########################################################################
## MPC85xx Systems
#########################################################################
diff --git a/board/edb93xx/Makefile b/board/edb93xx/Makefile
new file mode 100644
index 0000000..e2e2636
--- /dev/null
+++ b/board/edb93xx/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := edb93xx.o flash_cfg.o pll_cfg.o sdram_cfg.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/edb93xx/config.mk b/board/edb93xx/config.mk
new file mode 100644
index 0000000..b2fc6fa
--- /dev/null
+++ b/board/edb93xx/config.mk
@@ -0,0 +1,33 @@
+LDSCRIPT := $(SRCTREE)/cpu/arm920t/ep93xx/u-boot.lds
+
+ifdef CONFIG_EDB9301
+TEXT_BASE = 0x05700000
+endif
+
+ifdef CONFIG_EDB9302
+TEXT_BASE = 0x05700000
+endif
+
+ifdef CONFIG_EDB9302A
+TEXT_BASE = 0xc5700000
+endif
+
+ifdef CONFIG_EDB9307
+TEXT_BASE = 0x01f00000
+endif
+
+ifdef CONFIG_EDB9307A
+TEXT_BASE = 0xc1f00000
+endif
+
+ifdef CONFIG_EDB9312
+TEXT_BASE = 0x01f00000
+endif
+
+ifdef CONFIG_EDB9315
+TEXT_BASE = 0x01f00000
+endif
+
+ifdef CONFIG_EDB9315A
+TEXT_BASE = 0xc1f00000
+endif
diff --git a/board/edb93xx/early_udelay.h b/board/edb93xx/early_udelay.h
new file mode 100644
index 0000000..3b26b3f
--- /dev/null
+++ b/board/edb93xx/early_udelay.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* delay execution before timers are initialized */
+static inline void early_udelay(uint32_t usecs)
+{
+ /* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */
+ register uint32_t loops = (usecs * 1000) / 20;
+
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0" (loops));
+}
diff --git a/board/edb93xx/edb93xx.c b/board/edb93xx/edb93xx.c
new file mode 100644
index 0000000..52ec259
--- /dev/null
+++ b/board/edb93xx/edb93xx.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * (C) Copyright 2002 2003
+ * Network Audio Technologies, Inc. <www.netaudiotech.com>
+ * Adam Bezanson <bezanson@netaudiotech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MAX_BANK_SIZE 0x04000000 /* 64 MB */
+
+static ulong const bank_addr[CONFIG_NR_DRAM_BANKS] = {
+ PHYS_SDRAM_1,
+#ifdef PHYS_SDRAM_2
+ PHYS_SDRAM_2,
+#endif
+#ifdef PHYS_SDRAM_3
+ PHYS_SDRAM_3,
+#endif
+#ifdef PHYS_SDRAM_4
+ PHYS_SDRAM_4
+#endif
+};
+
+int board_init(void)
+{
+ struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+ icache_enable();
+
+#ifdef USE_920T_MMU
+ dcache_enable();
+#endif
+
+ /*
+ * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of
+ * 14.7456/2 MHz
+ */
+ uint32_t value = readl(&syscon->pwrcnt);
+ value |= SYSCON_PWRCNT_UART_BAUD;
+ writel(value, &syscon->pwrcnt);
+
+ /* Machine number, as defined in linux/arch/arm/tools/mach-types */
+ gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+ /* We have a console */
+ gd->have_console = 1;
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+ return ep93xx_eth_initialize(0, MAC_BASE);
+}
+
+int dram_init(void)
+{
+ unsigned int *src, *dst;
+ int i;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ const ulong bank_size = get_ram_size((long *)bank_addr[i],
+ MAX_BANK_SIZE);
+ if (bank_size) {
+ gd->bd->bi_dram[i].start = bank_addr[i];
+ gd->bd->bi_dram[i].size = bank_size;
+ }
+ }
+
+ /* copy exception vectors */
+ src = (unsigned int *)_armboot_start;
+
+#ifdef CONFIG_EDB93XX_SDCS3
+ dst = (unsigned int *)0x00000000;
+#else
+ dst = (unsigned int *)0xc0000000;
+#endif
+ memcpy(dst, src, 16 * sizeof(unsigned int));
+
+ return 0;
+}
diff --git a/board/edb93xx/flash_cfg.c b/board/edb93xx/flash_cfg.c
new file mode 100644
index 0000000..24ea210
--- /dev/null
+++ b/board/edb93xx/flash_cfg.c
@@ -0,0 +1,38 @@
+/*
+ * Flash setup for Cirrus edb93xx boards
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+
+#define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \
+ SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \
+ 1 << SMC_BCR_MW_SHIFT)
+
+void flash_cfg(void)
+{
+ struct smc_regs *smc = (struct smc_regs *)SMC_BASE;
+
+ writel(SMC_BCR6_VALUE, &smc->bcr6);
+}
diff --git a/board/edb93xx/pll_cfg.c b/board/edb93xx/pll_cfg.c
new file mode 100644
index 0000000..a687af0
--- /dev/null
+++ b/board/edb93xx/pll_cfg.c
@@ -0,0 +1,58 @@
+/*
+ * PLL setup for Cirrus edb93xx boards
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include "pll_cfg.h"
+#include "early_udelay.h"
+
+void pll_cfg(void)
+{
+ struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+ /* setup PLL1 */
+ writel(CLKSET1_VAL, &syscon->clkset1);
+
+ /*
+ * flush the pipeline
+ * writing to CLKSET1 causes the EP93xx to enter standby for between
+ * 8 ms to 16 ms, until PLL1 stabilizes
+ */
+ asm("nop");
+ asm("nop");
+ asm("nop");
+ asm("nop");
+ asm("nop");
+
+ /* setup PLL2 */
+ writel(CLKSET2_VAL, &syscon->clkset2);
+
+ /*
+ * the user's guide recommends to wait at least 1 ms for PLL2 to
+ * stabilize
+ */
+ early_udelay(1000);
+}
diff --git a/board/edb93xx/pll_cfg.h b/board/edb93xx/pll_cfg.h
new file mode 100644
index 0000000..8001e01
--- /dev/null
+++ b/board/edb93xx/pll_cfg.h
@@ -0,0 +1,72 @@
+/*
+ * PLL register values for Cirrus edb93xx boards
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/ep93xx.h>
+
+#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \
+ defined(CONFIG_EDB9302A)
+/*
+ * fclk_div: 2, nbyp1: 1, hclk_div: 5, pclk_div: 2
+ * pll1_x1: 294912000.000000, pll1_x2ip: 36864000.000000,
+ * pll1_x2: 331776000.000000, pll1_out: 331776000.000000
+ */
+#define CLKSET1_VAL (7 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
+ 8 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
+ 19 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
+ 1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \
+ 3 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \
+ SYSCON_CLKSET1_NBYP1 | \
+ 1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT)
+#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) ||\
+ defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) ||\
+ defined(CONFIG_EDB9315A)
+/*
+ * fclk_div: 2, nbyp1: 1, hclk_div: 4, pclk_div: 2
+ * pll1_x1: 3096576000.000000, pll1_x2ip: 129024000.000000,
+ * pll1_x2: 3999744000.000000, pll1_out: 1999872000.000000
+ */
+#define CLKSET1_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
+ 30 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
+ 20 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
+ 1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \
+ 2 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \
+ SYSCON_CLKSET1_NBYP1 | \
+ 1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT)
+#else
+#error "Undefined board"
+#endif
+
+/*
+ * usb_div: 4, nbyp2: 1, pll2_en: 1
+ * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000,
+ * pll2_x2: 384000000.000000, pll2_out: 192000000.000000
+ */
+#define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
+ 24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
+ 24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
+ 1 << SYSCON_CLKSET_PLL_PS_SHIFT | \
+ SYSCON_CLKSET2_PLL2_EN | \
+ SYSCON_CLKSET2_NBYP2 | \
+ 3 << SYSCON_CLKSET2_USB_DIV_SHIFT)
diff --git a/board/edb93xx/sdram_cfg.c b/board/edb93xx/sdram_cfg.c
new file mode 100644
index 0000000..201390b
--- /dev/null
+++ b/board/edb93xx/sdram_cfg.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/io.h>
+#include "sdram_cfg.h"
+#include "early_udelay.h"
+
+#define PROGRAM_MODE_REG(bank) (*(volatile uint32_t *) \
+ (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank | SDRAM_MODE_REG_VAL))
+
+#define PRECHARGE_BANK(bank) (*(volatile uint32_t *) \
+ (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank))
+
+static void force_precharge(void);
+static void setup_refresh_timer(void);
+static void program_mode_registers(void);
+
+void sdram_cfg(void)
+{
+ struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
+
+ writel(SDRAM_DEVCFG_VAL, &sdram->SDRAM_DEVCFG_REG);
+
+ /* Issue continous NOP commands */
+ writel(GLCONFIG_INIT | GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig);
+
+ early_udelay(200);
+
+ force_precharge();
+
+ setup_refresh_timer();
+
+ program_mode_registers();
+
+ /* Select normal operation mode */
+ writel(GLCONFIG_CKE, &sdram->glconfig);
+}
+
+static void force_precharge(void)
+{
+ /*
+ * Errata most EP93xx revisions say that PRECHARGE ALL isn't always
+ * issued.
+ *
+ * Do a read from each bank to make sure they're precharged
+ */
+
+ PRECHARGE_BANK(0);
+ PRECHARGE_BANK(1);
+ PRECHARGE_BANK(2);
+ PRECHARGE_BANK(3);
+}
+
+static void setup_refresh_timer(void)
+{
+ struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
+
+ /* Load refresh timer with 10 to issue refresh every 10 cycles */
+ writel(0x0a, &sdram->refrshtimr);
+
+ /*
+ * Wait at least 80 clock cycles to provide 8 refresh cycles
+ * to all SDRAMs
+ */
+ early_udelay(1);
+
+ /*
+ * Program refresh timer with normal value
+ * We need 8192 refresh cycles every 64ms
+ * at 15ns (HCLK >= 66MHz) per cycle:
+ * 64ms / 8192 = 7.8125us
+ * 7.8125us / 15ns = 520 (0x208)
+ */
+ /*
+ * TODO: redboot uses 0x1e0 for the slowest possible device
+ * but i don't understand how this value is calculated
+ */
+ writel(0x208, &sdram->refrshtimr);
+}
+
+static void program_mode_registers(void)
+{
+ PROGRAM_MODE_REG(0);
+
+#if (CONFIG_NR_DRAM_BANKS >= 2)
+ PROGRAM_MODE_REG(1);
+#endif
+
+#if (CONFIG_NR_DRAM_BANKS >= 3)
+ PROGRAM_MODE_REG(2);
+#endif
+
+#if (CONFIG_NR_DRAM_BANKS == 4)
+ PROGRAM_MODE_REG(3);
+#endif
+}
diff --git a/board/edb93xx/sdram_cfg.h b/board/edb93xx/sdram_cfg.h
new file mode 100644
index 0000000..983ff83
--- /dev/null
+++ b/board/edb93xx/sdram_cfg.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/ep93xx.h>
+
+#define SDRAM_BASE_ADDR PHYS_SDRAM_1
+
+#ifdef CONFIG_EDB93XX_SDCS0
+#define SDRAM_DEVCFG_REG devcfg0
+#elif defined(CONFIG_EDB93XX_SDCS3)
+#define SDRAM_DEVCFG_REG devcfg3
+#else
+#error "SDRAM bank configuration"
+#endif
+
+#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) ||\
+ defined(CONFIG_EDB9302A)
+/*
+ * 1x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM
+ *
+ * CLK cycle time min:
+ * @ CAS latency = 3: 7.5ns
+ * @ CAS latency = 2: 10ns
+ * We're running at 66MHz (15ns cycle time) external bus speed (HCLK),
+ * so it's safe to use CAS latency = 2
+ *
+ * RAS-to-CAS delay min:
+ * 20ns
+ * At 15ns cycle time, we use RAS-to-CAS delay = 2
+ *
+ * SROMLL = 1: Swap BA[1:0] with A[13:12], making the SDRAM appear
+ * as four blocks of 8MB size, instead of eight blocks of 4MB size:
+ *
+ * EDB9301/EDB9302:
+ *
+ * 0x00000000 - 0x007fffff
+ * 0x01000000 - 0x017fffff
+ * 0x04000000 - 0x047fffff
+ * 0x05000000 - 0x057fffff
+ *
+ *
+ * EDB9302a:
+ *
+ * 0xc0000000 - 0xc07fffff
+ * 0xc1000000 - 0xc17fffff
+ * 0xc4000000 - 0xc47fffff
+ * 0xc5000000 - 0xc57fffff
+ *
+ * BANKCOUNT = 1: This is a device with four banks
+ */
+
+#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT | \
+ SDRAM_DEVCFG_SROMLL | \
+ SDRAM_DEVCFG_CASLAT_2 | \
+ SDRAM_DEVCFG_RASTOCAS_2 | \
+ SDRAM_DEVCFG_EXTBUSWIDTH)
+
+/*
+ * 16 bit ext. bus
+ *
+ * A[22:09] is output as SYA[13:0]
+ * CAS latency: 2
+ * Burst type: sequential
+ * Burst length: 8 (required for 16 bit ext. bus)
+ * SYA[13:0] = 0x0023
+ */
+#define SDRAM_MODE_REG_VAL 0x4600
+
+#define SDRAM_BANK_SEL_0 0x00000000 /* A[22:21] = b00 */
+#define SDRAM_BANK_SEL_1 0x00200000 /* A[22:21] = b01 */
+#define SDRAM_BANK_SEL_2 0x00400000 /* A[22:21] = b10 */
+#define SDRAM_BANK_SEL_3 0x00600000 /* A[22:21] = b11 */
+
+#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) ||\
+ defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) ||\
+ defined(CONFIG_EDB9315A)
+/*
+ * 2x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM
+ *
+ * CLK cycle time min:
+ * @ CAS latency = 3: 7.5ns
+ * @ CAS latency = 2: 10ns
+ * We're running at 100MHz (10ns cycle time) external bus speed (HCLK),
+ * so it's safe to use CAS latency = 2
+ *
+ * RAS-to-CAS delay min:
+ * 20ns
+ * At 10ns cycle time, we use RAS-to-CAS delay = 2
+ *
+ * EDB9307, EDB9312, EDB9315:
+ *
+ * 0x00000000 - 0x01ffffff
+ * 0x04000000 - 0x05ffffff
+ *
+ *
+ * EDB9307a, EDB9315a:
+ *
+ * 0xc0000000 - 0xc1ffffff
+ * 0xc4000000 - 0xc5ffffff
+ */
+
+#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT | \
+ SDRAM_DEVCFG_SROMLL | \
+ SDRAM_DEVCFG_CASLAT_2 | \
+ SDRAM_DEVCFG_RASTOCAS_2)
+
+/*
+ * 32 bit ext. bus
+ *
+ * A[23:10] is output as SYA[13:0]
+ * CAS latency: 2
+ * Burst type: sequential
+ * Burst length: 4
+ * SYA[13:0] = 0x0022
+ */
+#define SDRAM_MODE_REG_VAL 0x8800
+
+#define SDRAM_BANK_SEL_0 0x00000000 /* A[23:22] = b00 */
+#define SDRAM_BANK_SEL_1 0x00400000 /* A[23:22] = b01 */
+#define SDRAM_BANK_SEL_2 0x00800000 /* A[23:22] = b10 */
+#define SDRAM_BANK_SEL_3 0x00c00000 /* A[23:22] = b11 */
+#endif
diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h
new file mode 100644
index 0000000..fec21c8
--- /dev/null
+++ b/include/configs/edb93xx.h
@@ -0,0 +1,273 @@
+/*
+ * U-boot - Configuration file for Cirrus Logic EDB93xx boards
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_MK_edb9301
+#define CONFIG_EDB9301
+#elif defined(CONFIG_MK_edb9302)
+#define CONFIG_EDB9302
+#elif defined(CONFIG_MK_edb9302a)
+#define CONFIG_EDB9302A
+#elif defined(CONFIG_MK_edb9307)
+#define CONFIG_EDB9307
+#elif defined(CONFIG_MK_edb9307a)
+#define CONFIG_EDB9307A
+#elif defined(CONFIG_MK_edb9312)
+#define CONFIG_EDB9312
+#elif defined(CONFIG_MK_edb9315)
+#define CONFIG_EDB9315
+#elif defined(CONFIG_MK_edb9315a)
+#define CONFIG_EDB9315A
+#else
+#error "no board defined"
+#endif
+
+/* Initial environment and monitor configuration options. */
+#define CONFIG_BOOTDELAY 2
+#define CONFIG_CMDLINE_TAG 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_BOOTARGS "root=/dev/nfs console=ttyAM0,115200 ip=dhcp"
+#define CONFIG_BOOTFILE "edb93xx.img"
+
+#define CONFIG_SYS_HUSH_PARSER 1
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#ifdef CONFIG_EDB9301
+#define CONFIG_EP9301
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9301
+#define CONFIG_SYS_PROMPT "EDB9301> "
+#define CONFIG_ENV_SECT_SIZE 0x00020000
+#elif defined(CONFIG_EDB9302)
+#define CONFIG_EP9302
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302
+#define CONFIG_SYS_PROMPT "EDB9302> "
+#define CONFIG_ENV_SECT_SIZE 0x00020000
+#elif defined(CONFIG_EDB9302A)
+#define CONFIG_EP9302
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302A
+#define CONFIG_SYS_PROMPT "EDB9302A> "
+#define CONFIG_ENV_SECT_SIZE 0x00020000
+#elif defined(CONFIG_EDB9307)
+#define CONFIG_EP9307
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307
+#define CONFIG_SYS_PROMPT "EDB9307> "
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#elif defined(CONFIG_EDB9307A)
+#define CONFIG_EP9307
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307A
+#define CONFIG_SYS_PROMPT "EDB9307A> "
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#elif defined(CONFIG_EDB9312)
+#define CONFIG_EP9312
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9312
+#define CONFIG_SYS_PROMPT "EDB9312> "
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#elif defined(CONFIG_EDB9315)
+#define CONFIG_EP9315
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315
+#define CONFIG_SYS_PROMPT "EDB9315> "
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#elif defined(CONFIG_EDB9315A)
+#define CONFIG_EP9315
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315A
+#define CONFIG_SYS_PROMPT "EDB9315A> "
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#else
+#error "no board defined"
+#endif
+
+/* High-level configuration options */
+#define CONFIG_ARM920T 1 /* This is an ARM920T core... */
+#define CONFIG_EP93XX 1 /* in a Cirrus Logic 93xx SoC */
+
+#define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456 clock */
+#define CONFIG_SYS_HZ 1000 /* decr freq: 1 ms ticks */
+#undef CONFIG_USE_IRQ /* Don't need IRQ/FIQ */
+
+/* Monitor configuration */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#undef CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+
+#define CONFIG_SYS_LONGHELP /* Enable "long" help in mon */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
+/* Print buffer size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+/* Boot argument buffer size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
+
+/* Serial port hardware configuration */
+#define CONFIG_PL010_SERIAL
+#define CONFIG_CONS_INDEX 0
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+#define CONFIG_SYS_SERIAL0 0x808C0000
+#define CONFIG_SYS_SERIAL1 0x808D0000
+#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
+ (void *)CONFIG_SYS_SERIAL1}
+
+/* Status LED */
+#define CONFIG_STATUS_LED 1 /* Status LED enabled */
+#define CONFIG_BOARD_SPECIFIC_LED 1
+#define STATUS_LED_GREEN 0
+#define STATUS_LED_RED 1
+/* Green */
+#define STATUS_LED_BIT STATUS_LED_GREEN
+#define STATUS_LED_STATE STATUS_LED_ON
+#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
+/* Red */
+#define STATUS_LED_BIT1 STATUS_LED_RED
+#define STATUS_LED_STATE1 STATUS_LED_OFF
+#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
+/* Optional value */
+#define STATUS_LED_BOOT STATUS_LED_BIT
+
+/* Network hardware configuration */
+#define CONFIG_DRIVER_EP93XX_MAC
+#define CONFIG_MII_SUPPRESS_PREAMBLE
+#define CONFIG_MII
+#define CONFIG_PHY_ADDR 1
+#define CONFIG_NET_MULTI
+#undef CONFIG_NETCONSOLE
+
+/* SDRAM configuration */
+#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302)
+/*
+ * EDB9301/2 has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
+ * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
+ * the SROMLL bit on the processor, resulting in this non-contiguous memory map.
+ */
+#define CONFIG_NR_DRAM_BANKS 4
+#define PHYS_SDRAM_1 0x00000000
+#define PHYS_SDRAM_SIZE_1 0x00800000
+#define PHYS_SDRAM_2 0x01000000
+#define PHYS_SDRAM_SIZE_2 0x00800000
+#define PHYS_SDRAM_3 0x04000000
+#define PHYS_SDRAM_SIZE_3 0x00800000
+#define PHYS_SDRAM_4 0x05000000
+#define PHYS_SDRAM_SIZE_4 0x00800000
+#define CONFIG_EDB93XX_SDCS3
+#define CONFIG_SYS_MEMTEST_START 0x00100000
+#define CONFIG_SYS_MEMTEST_END 0x007fffff
+
+#elif defined(CONFIG_EDB9302A)
+/*
+ * EDB9302a has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
+ * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
+ * the SROMLL bit on the processor, resulting in this non-contiguous memory map.
+ */
+#define CONFIG_NR_DRAM_BANKS 4
+#define PHYS_SDRAM_1 0xc0000000
+#define PHYS_SDRAM_SIZE_1 0x00800000
+#define PHYS_SDRAM_2 0xc1000000
+#define PHYS_SDRAM_SIZE_2 0x00800000
+#define PHYS_SDRAM_3 0xc4000000
+#define PHYS_SDRAM_SIZE_3 0x00800000
+#define PHYS_SDRAM_4 0xc5000000
+#define PHYS_SDRAM_SIZE_4 0x00800000
+#define CONFIG_EDB93XX_SDCS0
+#define CONFIG_SYS_MEMTEST_START 0xc0100000
+#define CONFIG_SYS_MEMTEST_END 0xc07fffff
+
+#elif defined(CONFIG_EDB9307) || defined CONFIG_EDB9312 || \
+ defined(CONFIG_EDB9315)
+/*
+ * The EDB9307, EDB9312, and EDB9315 have 2 banks of SDRAM consisting of
+ * 2x Samsung K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of
+ * 64 MB of SDRAM.
+ */
+#define CONFIG_NR_DRAM_BANKS 2
+#define PHYS_SDRAM_1 0x00000000
+#define PHYS_SDRAM_SIZE_1 0x02000000
+#define PHYS_SDRAM_2 0x04000000
+#define PHYS_SDRAM_SIZE_2 0x02000000
+#define CONFIG_EDB93XX_SDCS3
+#define CONFIG_SYS_MEMTEST_START 0x00100000
+#define CONFIG_SYS_MEMTEST_END 0x01e00000
+
+#elif defined(CONFIG_EDB9307A) || defined(CONFIG_EDB9315A)
+/*
+ * The EDB9307A and EDB9315A have 2 banks of SDRAM consisting of 2x Samsung
+ * K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of 64 MB of SDRAM.
+ */
+#define CONFIG_NR_DRAM_BANKS 2
+#define PHYS_SDRAM_1 0xc0000000
+#define PHYS_SDRAM_SIZE_1 0x02000000
+#define PHYS_SDRAM_2 0xc4000000
+#define PHYS_SDRAM_SIZE_2 0x02000000
+#define CONFIG_EDB93XX_SDCS0
+#define CONFIG_SYS_MEMTEST_START 0xc0100000
+#define CONFIG_SYS_MEMTEST_END 0xc1e00000
+#endif
+
+#if defined(CONFIG_EDB93XX_SDCS3)
+#define CONFIG_SYS_LOAD_ADDR 0x01000000 /* Default load address */
+#elif defined(CONFIG_EDB93XX_SDCS0)
+#define CONFIG_SYS_LOAD_ADDR 0xc1000000 /* Default load address */
+#endif
+
+/* Must match kernel config */
+#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
+
+/* Run-time memory allocatons */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+#define CONFIG_STACKSIZE (128 * 1024)
+
+#if defined(CONFIG_USE_IRQ)
+#define CONFIG_STACKSIZE_IRQ (4 * 1024)
+#define CONFIG_STACKSIZE_FIQ (4 * 1024)
+#endif
+
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
+
+/* -----------------------------------------------------------------------------
+ * FLASH and environment organization
+ *
+ * The EDB9301 and EDB9302(a) have 1 bank of flash memory at 0x60000000
+ * consisting of 1x Intel TE28F128J3C-150 128 Mbit flash on a 16-bit data bus,
+ * for a total of 16 MB of CFI-compatible flash.
+ *
+ * The EDB9307(a), EDB9312, and EDB9315(a) have 1 bank of flash memory at
+ * 0x60000000 consisting of 2x Micron MT28F128J3-12 128 Mbit flash on a 32-bit
+ * data bus, for a total of 32 MB of CFI-compatible flash.
+ *
+ * EDB9301/02(a) EDB9307(a)/12/15(a)
+ * 0x60000000 - 0x0003FFFF u-boot u-boot
+ * 0x60040000 - 0x0005FFFF environment #1 environment #1
+ * 0x60060000 - 0x0007FFFF environment #2 environment #1 (continued)
+ * 0x60080000 - 0x0009FFFF unused environment #2
+ * 0x600A0000 - 0x000BFFFF unused environment #2 (continued)
+ * 0x600C0000 - 0x00FFFFFF unused unused
+ * 0x61000000 - 0x01FFFFFF not present unused
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 128
+
+#define PHYS_FLASH_1 0x60000000
+#define CONFIG_SYS_FLASH_BASE (PHYS_FLASH_1)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+
+#define CONFIG_ENV_OVERWRITE /* Vendor params unprotected */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR 0x60040000
+
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+#endif /* !defined (__CONFIG_H) */
--
1.6.3.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH 2/3] Add EP93xx ethernet driver
2010-01-24 16:56 ` [U-Boot] [PATCH 2/3] Add EP93xx ethernet driver Matthias Kaehlcke
@ 2010-01-25 4:09 ` Ben Warren
0 siblings, 0 replies; 12+ messages in thread
From: Ben Warren @ 2010-01-25 4:09 UTC (permalink / raw)
To: u-boot
Hi Matthias,
On Sun, Jan 24, 2010 at 8:56 AM, Matthias Kaehlcke <matthias@kaehlcke.net>wrote:
> Added ethernet driver for EP93xx SoCs
>
> Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
> ---
> drivers/net/Makefile | 1 +
> drivers/net/ep93xx_eth.c | 654
> ++++++++++++++++++++++++++++++++++++++++++++++
> drivers/net/ep93xx_eth.h | 144 ++++++++++
> include/common.h | 5 +
> include/netdev.h | 1 +
> 5 files changed, 805 insertions(+), 0 deletions(-)
> create mode 100644 drivers/net/ep93xx_eth.c
> create mode 100644 drivers/net/ep93xx_eth.h
>
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> index 904727e..dc3107c 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -37,6 +37,7 @@ COBJS-$(CONFIG_DNET) += dnet.o
> COBJS-$(CONFIG_E1000) += e1000.o
> COBJS-$(CONFIG_EEPRO100) += eepro100.o
> COBJS-$(CONFIG_ENC28J60) += enc28j60.o
> +COBJS-$(CONFIG_EP93XX) += ep93xx_eth.o
> COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o
> COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
> COBJS-$(CONFIG_FTMAC100) += ftmac100.o
> diff --git a/drivers/net/ep93xx_eth.c b/drivers/net/ep93xx_eth.c
> new file mode 100644
> index 0000000..33d14df
> --- /dev/null
> +++ b/drivers/net/ep93xx_eth.c
> @@ -0,0 +1,654 @@
> +/*
> + * Cirrus Logic EP93xx ethernet MAC / MII driver.
> + *
> + * Copyright (C) 2010, 2009
> + * Matthias Kaehlcke <matthias@kaehlcke.net>
> + *
> + * Copyright (C) 2004, 2005
> + * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
> + *
> + * Based on the original eth.[ch] Cirrus Logic EP93xx Rev D. Ethernet
> Driver,
> + * which is
> + *
> + * (C) Copyright 2002 2003
> + * Adam Bezanson, Network Audio Technologies, Inc.
> + * <bezanson@netaudiotech.com>
> + *
> + * See file CREDITS for list of people who contributed to this project.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful, but
> + * WITHOUT ANY WARRANTY; without even the implied warranty of
> MERCHANTABILITY
> + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
> + * for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, write to the Free Software Foundation, Inc.,
> + * 675 Mass Ave, Cambridge, MA 02139, USA.
> + */
> +
> +#include <command.h>
> +#include <common.h>
> +#include <asm/arch/ep93xx.h>
> +#include <asm/io.h>
> +#include <malloc.h>
> +#include <miiphy.h>
> +#include <linux/types.h>
> +#include "ep93xx_eth.h"
> +
> +#define GET_PRIV(eth_dev) ((struct ep93xx_priv *)eth_dev->priv)
>
You should probably have parens around "eth_dev", although problems would be
found at compile time.
> +#define GET_REGS(eth_dev) (GET_PRIV(eth_dev)->regs)
> +
> +/* ep93xx_miiphy ops forward declarations */
> +static int ep93xx_miiphy_read(char * const dev, unsigned char const addr,
> + unsigned char const reg, unsigned short * const
> value);
> +static int ep93xx_miiphy_write(char * const dev, unsigned char const addr,
> + unsigned char const reg, unsigned short const
> value);
> +
> +#if defined(EP93XX_MAC_DEBUG)
> +/**
> + * Dump ep93xx_mac values to the terminal.
> + */
> +inline void dump_dev(struct eth_device *dev)
>
All of these local functions should be static. inline is probably
pointless, especially since they're only compiled in when you're debugging.
> +{
> + struct ep93xx_priv *priv = GET_PRIV(dev);
> + int i;
> +
> + printf("\ndump_dev()\n");
> + printf(" rx_dq.base %08X\n", (uint32_t)priv->rx_dq.base);
>
If these are pointers, why not use %p instead of all this casting?
> + printf(" rx_dq.current %08X\n",
> (uint32_t)priv->rx_dq.current);
> + printf(" rx_dq.end %08X\n", (uint32_t)priv->rx_dq.end);
> + printf(" rx_sq.base %08X\n", (uint32_t)priv->rx_sq.base);
> + printf(" rx_sq.current %08X\n",
> (uint32_t)priv->rx_sq.current);
> + printf(" rx_sq.end %08X\n", (uint32_t)priv->rx_sq.end);
> +
> + for (i = 0; i < NUMRXDESC; i++)
> + printf(" rx_buffer[%2.d] %08X\n", i,
> + (uint32_t)NetRxPackets[i]);
> +
> + printf(" tx_dq.base %08X\n", (uint32_t)priv->tx_dq.base);
> + printf(" tx_dq.current %08X\n",
> (uint32_t)priv->tx_dq.current);
> + printf(" tx_dq.end %08X\n", (uint32_t)priv->tx_dq.end);
> + printf(" tx_sq.base %08X\n", (uint32_t)priv->tx_sq.base);
> + printf(" tx_sq.current %08X\n",
> (uint32_t)priv->tx_sq.current);
> + printf(" tx_sq.end %08X\n", (uint32_t)priv->tx_sq.end);
> +}
> +
> +/**
> + * Dump all RX status queue entries to the terminal.
> + */
> +inline void dump_rx_status_queue(struct eth_device *dev)
> +{
> + struct ep93xx_priv *priv = GET_PRIV(dev);
> + int i;
> +
> + printf("\ndump_rx_status_queue()\n");
> + printf(" descriptor address word1 word2\n");
> + for (i = 0; i < NUMRXDESC; i++) {
> + printf(" [ %08X ] %08X %08X\n",
> + (uint32_t)(priv->rx_sq.base + i),
> + (uint32_t)(priv->rx_sq.base + i)->word1,
> + (uint32_t)(priv->rx_sq.base + i)->word2);
>
word1 and word2 are defined as uint32_t, so no cast required.
> + }
> +}
> +
> +/**
> + * Dump all RX descriptor queue entries to the terminal.
> + */
> +inline void dump_rx_descriptor_queue(struct eth_device *dev)
> +{
> + struct ep93xx_priv *priv = GET_PRIV(dev);
> + int i;
> +
> + printf("\ndump_rx_descriptor_queue()\n");
> + printf(" descriptor address word1 word2\n");
> + for (i = 0; i < NUMRXDESC; i++) {
> + printf(" [ %08X ] %08X %08X\n",
> + (uint32_t)(priv->rx_dq.base + i),
> + (uint32_t)(priv->rx_dq.base + i)->word1,
> + (uint32_t)(priv->rx_dq.base + i)->word2);
> + }
> +}
> +
> +/**
> + * Dump all TX descriptor queue entries to the terminal.
> + */
> +inline void dump_tx_descriptor_queue(struct eth_device *dev)
> +{
> + struct ep93xx_priv *priv = GET_PRIV(dev);
> + int i;
> +
> + printf("\ndump_tx_descriptor_queue()\n");
> + printf(" descriptor address word1 word2\n");
> + for (i = 0; i < NUMTXDESC; i++) {
> + printf(" [ %08X ] %08X %08X\n",
> + (uint32_t)(priv->tx_dq.base + i),
> + (uint32_t)(priv->tx_dq.base + i)->word1,
> + (uint32_t)(priv->tx_dq.base + i)->word2);
> + }
> +}
> +
> +/**
> + * Dump all TX status queue entries to the terminal.
> + */
> +inline void dump_tx_status_queue(struct eth_device *dev)
> +{
> + struct ep93xx_priv *priv = GET_PRIV(dev);
> + int i;
> +
> + printf("\ndump_tx_status_queue()\n");
> + printf(" descriptor address word1\n");
> + for (i = 0; i < NUMTXDESC; i++) {
> + printf(" [ %08X ] %08X\n",
> + (uint32_t)(priv->rx_sq.base + i),
> + (uint32_t)(priv->rx_sq.base + i)->word1);
> + }
> +}
> +#else
> +#define dump_dev(x)
> +#define dump_rx_descriptor_queue(x)
> +#define dump_rx_status_queue(x)
> +#define dump_tx_descriptor_queue(x)
> +#define dump_tx_status_queue(x)
> +#endif /* defined(EP93XX_MAC_DEBUG) */
> +
> +/**
> + * Reset the EP93xx MAC by twiddling the soft reset bit and spinning until
> + * it's cleared.
> + */
> +static void ep93xx_mac_reset(struct eth_device *dev)
> +{
> + struct mac_regs *mac = GET_REGS(dev);
> + uint32_t value;
> +
> + debug("+ep93xx_mac_reset");
> +
> + value = readl(&mac->selfctl);
> + value |= SELFCTL_RESET;
> + writel(value, &mac->selfctl);
> +
> + while (readl(&mac->selfctl) & SELFCTL_RESET)
> + ; /* noop */
> +
> + debug("-ep93xx_mac_reset");
> +}
> +
> +/* Eth device open */
> +static int ep93xx_eth_open(struct eth_device *dev, bd_t *bd)
> +{
> + struct ep93xx_priv *priv = GET_PRIV(dev);
> + struct mac_regs *mac = GET_REGS(dev);
> + uchar *mac_addr = dev->enetaddr;
> + int i;
> +
> + debug("+ep93xx_eth_open");
> +
> + /* Reset the MAC */
> + ep93xx_mac_reset(dev);
> +
> + /* Reset the descriptor queues' current and end address values */
> + priv->tx_dq.current = priv->tx_dq.base;
> + priv->tx_dq.end = (priv->tx_dq.base + NUMTXDESC);
> +
> + priv->tx_sq.current = priv->tx_sq.base;
> + priv->tx_sq.end = (priv->tx_sq.base + NUMTXDESC);
> +
> + priv->rx_dq.current = priv->rx_dq.base;
> + priv->rx_dq.end = (priv->rx_dq.base + NUMRXDESC);
> +
> + priv->rx_sq.current = priv->rx_sq.base;
> + priv->rx_sq.end = (priv->rx_sq.base + NUMRXDESC);
> +
> + /*
> + * Set the transmit descriptor and status queues' base address,
> + * current address, and length registers. Set the maximum frame
> + * length and threshold. Enable the transmit descriptor processor.
> + */
> + writel((uint32_t)priv->tx_dq.base, &mac->txdq.badd);
> + writel((uint32_t)priv->tx_dq.base, &mac->txdq.curadd);
> + writel(sizeof(struct tx_descriptor) * NUMTXDESC, &mac->txdq.blen);
> +
> + writel((uint32_t)priv->tx_sq.base, &mac->txstsq.badd);
> + writel((uint32_t)priv->tx_sq.base, &mac->txstsq.curadd);
> + writel(sizeof(struct tx_status) * NUMTXDESC, &mac->txstsq.blen);
> +
> + writel(0x00040000, &mac->txdthrshld);
> + writel(0x00040000, &mac->txststhrshld);
> +
> + writel((TXSTARTMAX << 0) | (PKTSIZE_ALIGN << 16), &mac->maxfrmlen);
> + writel(BMCTL_TXEN, &mac->bmctl);
> +
> + /*
> + * Set the receive descriptor and status queues' base address,
> + * current address, and length registers. Enable the receive
> + * descriptor processor.
> + */
> + writel((uint32_t)priv->rx_dq.base, &mac->rxdq.badd);
> + writel((uint32_t)priv->rx_dq.base, &mac->rxdq.curadd);
> + writel(sizeof(struct rx_descriptor) * NUMRXDESC, &mac->rxdq.blen);
> +
> + writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.badd);
> + writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.curadd);
> + writel(sizeof(struct rx_status) * NUMRXDESC, &mac->rxstsq.blen);
> +
> + writel(0x00040000, &mac->rxdthrshld);
> +
> + writel(BMCTL_RXEN, &mac->bmctl);
> +
> + writel(0x00040000, &mac->rxststhrshld);
> +
> + /* Wait until the receive descriptor processor is active */
> + while (!(readl(&mac->bmsts) & BMSTS_RXACT))
> + ; /* noop */
> +
> + /*
> + * Initialize the RX descriptor queue. Clear the TX descriptor
> queue.
> + * Clear the RX and TX status queues. Enqueue the RX descriptor and
> + * status entries to the MAC.
> + */
> + for (i = 0; i < NUMRXDESC; i++) {
> + /* set buffer address */
> + (priv->rx_dq.base + i)->word1 = (uint32_t)NetRxPackets[i];
> +
> + /* set buffer length, clear buffer index and NSOF */
> + (priv->rx_dq.base + i)->word2 = PKTSIZE_ALIGN;
> + }
> +
> + memset(priv->tx_dq.base, 0,
> + (sizeof(struct tx_descriptor) * NUMTXDESC));
> + memset(priv->rx_sq.base, 0,
> + (sizeof(struct rx_status) * NUMRXDESC));
> + memset(priv->tx_sq.base, 0,
> + (sizeof(struct tx_status) * NUMTXDESC));
> +
> + writel(NUMRXDESC, &mac->rxdqenq);
> + writel(NUMRXDESC, &mac->rxstsqenq);
> +
> + /* Set the primary MAC address */
> + writel(AFP_IAPRIMARY, &mac->afp);
> + writel(mac_addr[0] | (mac_addr[1] << 8) |
> + (mac_addr[2] << 16) | (mac_addr[3] << 24),
> + &mac->indad);
> + writel(mac_addr[4] | (mac_addr[5] << 8), &mac->indad_upper);
> +
> + /* Turn on RX and TX */
> + writel(RXCTL_IA0 | RXCTL_BA | RXCTL_SRXON |
> + RXCTL_RCRCA | RXCTL_MA, &mac->rxctl);
> + writel(TXCTL_STXON, &mac->txctl);
> +
> + /* Dump data structures if we're debugging */
> + dump_dev(dev);
> + dump_rx_descriptor_queue(dev);
> + dump_rx_status_queue(dev);
> + dump_tx_descriptor_queue(dev);
> + dump_tx_status_queue(dev);
> +
> + debug("-ep93xx_eth_open");
> +
> + return 1;
> +}
> +
> +/**
> + * Halt EP93xx MAC transmit and receive by clearing the TxCTL and RxCTL
> + * registers.
> + */
> +static void ep93xx_eth_close(struct eth_device *dev)
> +{
> + struct mac_regs *mac = GET_REGS(dev);
> +
> + debug("+ep93xx_eth_close");
> +
> + writel(0x00000000, &mac->rxctl);
> + writel(0x00000000, &mac->txctl);
> +
> + debug("-ep93xx_eth_close");
> +}
> +
> +/**
> + * Copy a frame of data from the MAC into the protocol layer for further
> + * processing.
> + */
> +static int ep93xx_eth_rcv_packet(struct eth_device *dev)
> +{
> + struct mac_regs *mac = GET_REGS(dev);
> + struct ep93xx_priv *priv = GET_PRIV(dev);
> + int len = -1;
> +
> + debug("+ep93xx_eth_rcv_packet");
> +
> + if (RX_STATUS_RFP(priv->rx_sq.current)) {
> + if (RX_STATUS_RWE(priv->rx_sq.current)) {
> + /*
> + * We have a good frame. Extract the frame's length
> + * from the current rx_status_queue entry, and copy
> + * the frame's data into NetRxPackets[] of the
> + * protocol stack. We track the total number of
> + * bytes in the frame (nbytes_frame) which will be
> + * used when we pass the data off to the protocol
> + * layer via NetReceive().
> + */
> + len = RX_STATUS_FRAME_LEN(priv->rx_sq.current);
> +
> + NetReceive((uchar *)priv->rx_dq.current->word1,
> len);
> +
> + debug("reporting %d bytes...\n", len);
> + } else {
> + /* Do we have an erroneous packet? */
> + error("packet rx error, status %08X %08X",
> + priv->rx_sq.current->word1,
> + priv->rx_sq.current->word2);
> + dump_rx_descriptor_queue(dev);
> + dump_rx_status_queue(dev);
> + }
> +
> + /*
> + * Clear the associated status queue entry, and
> + * increment our current pointers to the next RX
> + * descriptor and status queue entries (making sure
> + * we wrap properly).
> + */
> + memset((void *)priv->rx_sq.current, 0,
> + sizeof(struct rx_status));
> +
> + priv->rx_sq.current++;
> + if (priv->rx_sq.current >= priv->rx_sq.end)
> + priv->rx_sq.current = priv->rx_sq.base;
> +
> + priv->rx_dq.current++;
> + if (priv->rx_dq.current >= priv->rx_dq.end)
> + priv->rx_dq.current = priv->rx_dq.base;
> +
> + /*
> + * Finally, return the RX descriptor and status entries
> + * back to the MAC engine, and loop again, checking for
> + * more descriptors to process.
> + */
> + writel(1, &mac->rxdqenq);
> + writel(1, &mac->rxstsqenq);
> + } else {
> + len = 0;
> + }
> +
> + debug("-ep93xx_eth_rcv_packet %d", len);
> + return len;
> +}
> +
> +/**
> + * Send a block of data via ethernet.
> + */
> +static int ep93xx_eth_send_packet(struct eth_device *dev,
> + volatile void * const packet, int const
> length)
> +{
> + struct mac_regs *mac = GET_REGS(dev);
> + struct ep93xx_priv *priv = GET_PRIV(dev);
> + int ret = -1;
> +
> + debug("+ep93xx_eth_send_packet");
> +
> + /* Parameter check */
> + BUG_ON(packet == NULL);
> +
> + /*
> + * Initialize the TX descriptor queue with the new packet's info.
> + * Clear the associated status queue entry. Enqueue the packet
> + * to the MAC for transmission.
> + */
> +
> + /* set buffer address */
> + priv->tx_dq.current->word1 = (uint32_t)packet;
> +
> + /* set buffer length and EOF bit */
> + priv->tx_dq.current->word2 = length | TX_DESC_EOF;
> +
> + /* clear tx status */
> + priv->tx_sq.current->word1 = 0;
> +
> + /* enqueue the TX descriptor */
> + writel(1, &mac->txdqenq);
> +
> + /* wait for the frame to become processed */
> + while (!TX_STATUS_TXFP(priv->tx_sq.current))
> + ; /* noop */
> +
> + if (!TX_STATUS_TXWE(priv->tx_sq.current)) {
> + error("packet tx error, status %08X",
> + priv->tx_sq.current->word1);
> + dump_tx_descriptor_queue(dev);
> + dump_tx_status_queue(dev);
> +
> + /* TODO: Add better error handling? */
> + goto eth_send_failed_0;
> + }
> +
> + ret = 0;
> + /* Fall through */
> +
> +eth_send_failed_0:
>
Strange label here. This isn't just a fail path.
> + debug("-ep93xx_eth_send_packet %d", ret);
> + return ret;
> +}
> +
> +#if defined(CONFIG_MII)
> +int ep93xx_miiphy_initialize(bd_t * const bd)
> +{
> + miiphy_register("ep93xx_eth0", ep93xx_miiphy_read,
> ep93xx_miiphy_write);
> + return 0;
> +}
> +#endif
> +
> +/**
> + * Initialize the EP93xx MAC. The MAC hardware is reset. Buffers are
> + * allocated, if necessary, for the TX and RX descriptor and status
> queues,
> + * as well as for received packets. The EP93XX MAC hardware is
> initialized.
> + * Transmit and receive operations are enabled.
> + */
> +int ep93xx_eth_initialize(u8 dev_num, int base_addr)
> +{
> + int ret = -1;
> + struct eth_device *dev;
> + struct ep93xx_priv *priv;
> +
> + debug("+ep93xx_eth_initialize");
> +
> + priv = malloc(sizeof(*priv));
> + if (!priv) {
> + error("malloc() failed");
> + goto eth_init_failed_0;
> + }
> + memset(priv, 0, sizeof(*priv));
> +
> + priv->regs = (struct mac_regs *)base_addr;
> +
> + priv->tx_dq.base = calloc(NUMTXDESC,
> + sizeof(struct tx_descriptor));
> + if (priv->tx_dq.base == NULL) {
> + error("calloc() failed");
> + goto eth_init_failed_1;
> + }
> +
> + priv->tx_sq.base = calloc(NUMTXDESC,
> + sizeof(struct tx_status));
> + if (priv->tx_sq.base == NULL) {
> + error("calloc() failed");
> + goto eth_init_failed_2;
> + }
> +
> + priv->rx_dq.base = calloc(NUMRXDESC,
> + sizeof(struct rx_descriptor));
> + if (priv->rx_dq.base == NULL) {
> + error("calloc() failed");
> + goto eth_init_failed_3;
> + }
> +
> + priv->rx_sq.base = calloc(NUMRXDESC,
> + sizeof(struct rx_status));
> + if (priv->rx_sq.base == NULL) {
> + error("calloc() failed");
> + goto eth_init_failed_4;
> + }
> +
> + dev = malloc(sizeof *dev);
> + if (dev == NULL) {
> + error("malloc() failed");
> + goto eth_init_failed_5;
> + }
> + memset(dev, 0, sizeof *dev);
> +
> + dev->iobase = base_addr;
> + dev->priv = priv;
> + dev->init = ep93xx_eth_open;
> + dev->halt = ep93xx_eth_close;
> + dev->send = ep93xx_eth_send_packet;
> + dev->recv = ep93xx_eth_rcv_packet;
> +
> + sprintf(dev->name, "ep93xx_eth-%hu", dev_num);
> +
> + eth_register(dev);
> +
> + /* Done! */
> + ret = 0;
>
Remember, -1 means critical error, 0 means non-critical error and >0 means #
of devices initialized. I expect you want this to be '1'.
> + goto eth_init_done;
> +
> +eth_init_failed_5:
> + free(priv->rx_sq.base);
> + /* Fall through */
> +
> +eth_init_failed_4:
> + free(priv->rx_dq.base);
> + /* Fall through */
> +
> +eth_init_failed_3:
> + free(priv->tx_sq.base);
> + /* Fall through */
> +
> +eth_init_failed_2:
> + free(priv->tx_dq.base);
> + /* Fall through */
> +
> +eth_init_failed_1:
> + free(priv);
> + /* Fall through */
> +
> +eth_init_failed_0:
> + /* Fall through */
> +
> +eth_init_done:
> + debug("-ep93xx_eth_initialize %d", ret);
> + return ret;
> +}
> +
> +#if defined(CONFIG_MII)
> +
> +/**
> + * Maximum MII address we support
> + */
> +#define MII_ADDRESS_MAX 31
> +
> +/**
> + * Maximum MII register address we support
> + */
> +#define MII_REGISTER_MAX 31
> +
> +/**
> + * Read a 16-bit value from an MII register.
> + */
> +static int ep93xx_miiphy_read(char * const dev, unsigned char const addr,
> + unsigned char const reg, unsigned short * const
> value)
> +{
> + struct mac_regs *mac = (struct mac_regs *)MAC_BASE;
> + int ret = -1;
> + uint32_t self_ctl;
> +
> + debug("+ep93xx_miiphy_read");
> +
> + /* Parameter checks */
> + BUG_ON(dev == NULL);
> + BUG_ON(addr > MII_ADDRESS_MAX);
> + BUG_ON(reg > MII_REGISTER_MAX);
> + BUG_ON(value == NULL);
> +
> + /*
> + * Save the current SelfCTL register value. Set MAC to suppress
> + * preamble bits. Wait for any previous MII command to complete
> + * before issuing the new command.
> + */
> + self_ctl = readl(&mac->selfctl);
> +#if defined(CONFIG_MII_SUPPRESS_PREAMBLE)
> + writel(self_ctl & ~(1 << 8), &mac->selfctl);
> +#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
> +
> + while (readl(&mac->miists) & MIISTS_BUSY)
> + ; /* noop */
> +
> + /*
> + * Issue the MII 'read' command. Wait for the command to complete.
> + * Read the MII data value.
> + */
> + writel(MIICMD_OPCODE_READ | ((uint32_t)addr << 5) | (uint32_t)reg,
> + &mac->miicmd);
> + while (readl(&mac->miists) & MIISTS_BUSY)
> + ; /* noop */
> +
> + *value = (unsigned short)readl(&mac->miidata);
> +
> + /* Restore the saved SelfCTL value and return. */
> + writel(self_ctl, &mac->selfctl);
> +
> + ret = 0;
> + /* Fall through */
> +
> + debug("-ep93xx_miiphy_read");
> + return ret;
> +}
> +
> +/**
> + * Write a 16-bit value to an MII register.
> + */
> +static int ep93xx_miiphy_write(char * const dev, unsigned char const addr,
> + unsigned char const reg, unsigned short const
> value)
> +{
> + struct mac_regs *mac = (struct mac_regs *)MAC_BASE;
> + int ret = -1;
> + uint32_t self_ctl;
> +
> + debug("+ep93xx_miiphy_write");
> +
> + /* Parameter checks */
> + BUG_ON(dev == NULL);
> + BUG_ON(addr > MII_ADDRESS_MAX);
> + BUG_ON(reg > MII_REGISTER_MAX);
> +
> + /*
> + * Save the current SelfCTL register value. Set MAC to suppress
> + * preamble bits. Wait for any previous MII command to complete
> + * before issuing the new command.
> + */
> + self_ctl = readl(&mac->selfctl);
> +#if defined(CONFIG_MII_SUPPRESS_PREAMBLE)
> + writel(self_ctl & ~(1 << 8), &mac->selfctl);
> +#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
> +
> + while (readl(&mac->miists) & MIISTS_BUSY)
> + ; /* noop */
> +
> + /* Issue the MII 'write' command. Wait for the command to
> complete. */
> + writel((uint32_t)value, &mac->miidata);
> + writel(MIICMD_OPCODE_WRITE | ((uint32_t)addr << 5) | (uint32_t)reg,
> + &mac->miicmd);
> + while (readl(&mac->miists) & MIISTS_BUSY)
> + ; /* noop */
> +
> + /* Restore the saved SelfCTL value and return. */
> + writel(self_ctl, &mac->selfctl);
> +
> + ret = 0;
> + /* Fall through */
> +
> + debug("-ep93xx_miiphy_write");
> + return ret;
> +}
> +#endif /* defined(CONFIG_MII) */
> diff --git a/drivers/net/ep93xx_eth.h b/drivers/net/ep93xx_eth.h
> new file mode 100644
> index 0000000..5f7bf13
> --- /dev/null
> +++ b/drivers/net/ep93xx_eth.h
> @@ -0,0 +1,144 @@
> +/*
> + * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
> + *
> + * Copyright (C) 2004, 2005
> + * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + *
> + */
> +
> +#ifndef _ETH_H
> +#define _ETH_H
>
This should have a more specific namespace
> +
> +#include <net.h>
> +
> +/**
> + * #define this to dump device status and queue info during initialization
> and
> + * following errors.
> + */
> +#undef EP93XX_MAC_DEBUG
> +
> +/**
> + * Number of descriptor and status entries in our RX queues.
> + * It must be power of 2 !
> + */
> +#define NUMRXDESC PKTBUFSRX
> +
> +/**
> + * Number of descriptor and status entries in our TX queues.
> + */
> +#define NUMTXDESC 1
> +
> +/**
> + * 944 = (1024 - 64) - 16, Fifo size - Minframesize - 16 (Chip FACT)
> + */
> +#define TXSTARTMAX 944
> +
> +/**
> + * Receive descriptor queue entry
> + */
> +struct rx_descriptor {
> + uint32_t word1;
> + uint32_t word2;
> +};
> +
> +/**
> + * Receive status queue entry
> + */
> +struct rx_status {
> + uint32_t word1;
> + uint32_t word2;
> +};
> +
> +#define RX_STATUS_RWE(rx_status) ((rx_status->word1 >> 30) & 0x01)
> +#define RX_STATUS_RFP(rx_status) ((rx_status->word1 >> 31) & 0x01)
> +#define RX_STATUS_FRAME_LEN(rx_status) (rx_status->word2 & 0xFFFF)
> +
> +/**
> + * Transmit descriptor queue entry
> + */
> +struct tx_descriptor {
> + uint32_t word1;
> + uint32_t word2;
> +};
> +
> +#define TX_DESC_EOF (1 << 31)
> +
> +/**
> + * Transmit status queue entry
> + */
> +struct tx_status {
> + uint32_t word1;
> +};
> +
> +#define TX_STATUS_TXWE(tx_status) (((tx_status)->word1 >> 30) & 0x01)
> +#define TX_STATUS_TXFP(tx_status) (((tx_status)->word1 >> 31) & 0x01)
> +
> +/**
> + * Transmit descriptor queue
> + */
> +struct tx_descriptor_queue {
> + struct tx_descriptor *base;
> + struct tx_descriptor *current;
> + struct tx_descriptor *end;
> +};
> +
> +/**
> + * Transmit status queue
> + */
> +struct tx_status_queue {
> + struct tx_status *base;
> + volatile struct tx_status *current;
> + struct tx_status *end;
> +};
> +
> +/**
> + * Receive descriptor queue
> + */
> +struct rx_descriptor_queue {
> + struct rx_descriptor *base;
> + struct rx_descriptor *current;
> + struct rx_descriptor *end;
> +};
> +
> +/**
> + * Receive status queue
> + */
> +struct rx_status_queue {
> + struct rx_status *base;
> + volatile struct rx_status *current;
> + struct rx_status *end;
> +};
> +
> +/**
> + * EP93xx MAC private data structure
> + */
> +struct ep93xx_priv {
> + struct rx_descriptor_queue rx_dq;
> + struct rx_status_queue rx_sq;
> + void *rx_buffer[NUMRXDESC];
> +
> + struct tx_descriptor_queue tx_dq;
> + struct tx_status_queue tx_sq;
> +
> + struct mac_regs *regs;
> +};
> +
> +#endif
> diff --git a/include/common.h b/include/common.h
> index f2a7067..c0dfc45 100644
> --- a/include/common.h
> +++ b/include/common.h
> @@ -123,6 +123,11 @@ typedef volatile unsigned char vu_char;
> #define debugX(level,fmt,args...)
> #endif /* DEBUG */
>
> +#define error(fmt, args...) do { \
> + printf("ERROR: " fmt "\nat %s:%d/%s()\n", \
> + ##args, __FILE__, __LINE__, __func__); \
> +} while (0)
> +
> #ifndef BUG
> #define BUG() do { \
> printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__,
> __FUNCTION__); \
> diff --git a/include/netdev.h b/include/netdev.h
> index a9d5ec9..1e0484f 100644
> --- a/include/netdev.h
> +++ b/include/netdev.h
> @@ -49,6 +49,7 @@ int davinci_emac_initialize(void);
> int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
> int e1000_initialize(bd_t *bis);
> int eepro100_initialize(bd_t *bis);
> +int ep93xx_eth_initialize(u8 dev_num, int base_addr);
> int eth_3com_initialize (bd_t * bis);
> int fec_initialize (bd_t *bis);
> int fecmxc_initialize (bd_t *bis);
>
regards,
Ben
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH 3/3] Add support for EDB93xx boards
[not found] <cover.1264955406.git.matthias@kaehlcke.net>
@ 2010-01-31 16:39 ` Matthias Kaehlcke
0 siblings, 0 replies; 12+ messages in thread
From: Matthias Kaehlcke @ 2010-01-31 16:39 UTC (permalink / raw)
To: u-boot
Added support for the following EDB93xx boards:
EDB9301
EDB9302
EDB9302A
EDB9307
EDB9307A
EDB93012
EDB9315
EDB9315A
Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
---
MAINTAINERS | 10 ++
MAKEALL | 8 ++
Makefile | 10 ++
board/edb93xx/Makefile | 50 ++++++++
board/edb93xx/config.mk | 33 +++++
board/edb93xx/early_udelay.h | 34 +++++
board/edb93xx/edb93xx.c | 109 +++++++++++++++++
board/edb93xx/flash_cfg.c | 38 ++++++
board/edb93xx/pll_cfg.c | 58 +++++++++
board/edb93xx/pll_cfg.h | 72 +++++++++++
board/edb93xx/sdram_cfg.c | 117 ++++++++++++++++++
board/edb93xx/sdram_cfg.h | 144 ++++++++++++++++++++++
include/configs/edb93xx.h | 273 ++++++++++++++++++++++++++++++++++++++++++
13 files changed, 956 insertions(+), 0 deletions(-)
create mode 100644 board/edb93xx/Makefile
create mode 100644 board/edb93xx/config.mk
create mode 100644 board/edb93xx/early_udelay.h
create mode 100644 board/edb93xx/edb93xx.c
create mode 100644 board/edb93xx/flash_cfg.c
create mode 100644 board/edb93xx/pll_cfg.c
create mode 100644 board/edb93xx/pll_cfg.h
create mode 100644 board/edb93xx/sdram_cfg.c
create mode 100644 board/edb93xx/sdram_cfg.h
create mode 100644 include/configs/edb93xx.h
diff --git a/MAINTAINERS b/MAINTAINERS
index e8ba4bc..12a742e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -598,6 +598,16 @@ Gary Jennejohn <garyj@denx.de>
smdk2400 ARM920T
trab ARM920T
+Matthias Kaehlcke <matthias@kaehlcke.net>
+ edb9301 ARM920T (EP9301)
+ edb9302 ARM920T (EP9302)
+ edb9302a ARM920T (EP9302)
+ edb9307 ARM920T (EP9307)
+ edb9307a ARM920T (EP9307)
+ edb9312 ARM920T (EP9312)
+ edb9315 ARM920T (EP9315)
+ edb9315a ARM920T (EP9315)
+
Konstantin Kletschke <kletschke@synertronixx.de>
scb9328 ARM920T
diff --git a/MAKEALL b/MAKEALL
index afdc1b5..95e0843 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -554,6 +554,14 @@ LIST_ARM9=" \
cp946es \
cp966 \
da830evm \
+ edb9301 \
+ edb9302 \
+ edb9302a \
+ edb9307 \
+ edb9307a \
+ edb9312 \
+ edb9315 \
+ edb9315a \
imx27lite \
lpd7a400 \
mv88f6281gtw_ge \
diff --git a/Makefile b/Makefile
index 0f60925..5b4ab56 100644
--- a/Makefile
+++ b/Makefile
@@ -2412,6 +2412,16 @@ caddy2_config \
vme8349_config: unconfig
@$(MKCONFIG) -t $(@:_config=) vme8349 ppc mpc83xx vme8349 esd
+edb9301_config \
+edb9302_config \
+edb9302a_config \
+edb9307_config \
+edb9307a_config \
+edb9312_config \
+edb9315_config \
+edb9315a_config: unconfig
+ @$(MKCONFIG) -t $(@:_config=) edb93xx arm arm920t edb93xx NULL ep93xx
+
#########################################################################
## MPC85xx Systems
#########################################################################
diff --git a/board/edb93xx/Makefile b/board/edb93xx/Makefile
new file mode 100644
index 0000000..e2e2636
--- /dev/null
+++ b/board/edb93xx/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := edb93xx.o flash_cfg.o pll_cfg.o sdram_cfg.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/edb93xx/config.mk b/board/edb93xx/config.mk
new file mode 100644
index 0000000..b2fc6fa
--- /dev/null
+++ b/board/edb93xx/config.mk
@@ -0,0 +1,33 @@
+LDSCRIPT := $(SRCTREE)/cpu/arm920t/ep93xx/u-boot.lds
+
+ifdef CONFIG_EDB9301
+TEXT_BASE = 0x05700000
+endif
+
+ifdef CONFIG_EDB9302
+TEXT_BASE = 0x05700000
+endif
+
+ifdef CONFIG_EDB9302A
+TEXT_BASE = 0xc5700000
+endif
+
+ifdef CONFIG_EDB9307
+TEXT_BASE = 0x01f00000
+endif
+
+ifdef CONFIG_EDB9307A
+TEXT_BASE = 0xc1f00000
+endif
+
+ifdef CONFIG_EDB9312
+TEXT_BASE = 0x01f00000
+endif
+
+ifdef CONFIG_EDB9315
+TEXT_BASE = 0x01f00000
+endif
+
+ifdef CONFIG_EDB9315A
+TEXT_BASE = 0xc1f00000
+endif
diff --git a/board/edb93xx/early_udelay.h b/board/edb93xx/early_udelay.h
new file mode 100644
index 0000000..3b26b3f
--- /dev/null
+++ b/board/edb93xx/early_udelay.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* delay execution before timers are initialized */
+static inline void early_udelay(uint32_t usecs)
+{
+ /* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */
+ register uint32_t loops = (usecs * 1000) / 20;
+
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0" (loops));
+}
diff --git a/board/edb93xx/edb93xx.c b/board/edb93xx/edb93xx.c
new file mode 100644
index 0000000..52ec259
--- /dev/null
+++ b/board/edb93xx/edb93xx.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * (C) Copyright 2002 2003
+ * Network Audio Technologies, Inc. <www.netaudiotech.com>
+ * Adam Bezanson <bezanson@netaudiotech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MAX_BANK_SIZE 0x04000000 /* 64 MB */
+
+static ulong const bank_addr[CONFIG_NR_DRAM_BANKS] = {
+ PHYS_SDRAM_1,
+#ifdef PHYS_SDRAM_2
+ PHYS_SDRAM_2,
+#endif
+#ifdef PHYS_SDRAM_3
+ PHYS_SDRAM_3,
+#endif
+#ifdef PHYS_SDRAM_4
+ PHYS_SDRAM_4
+#endif
+};
+
+int board_init(void)
+{
+ struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+ icache_enable();
+
+#ifdef USE_920T_MMU
+ dcache_enable();
+#endif
+
+ /*
+ * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of
+ * 14.7456/2 MHz
+ */
+ uint32_t value = readl(&syscon->pwrcnt);
+ value |= SYSCON_PWRCNT_UART_BAUD;
+ writel(value, &syscon->pwrcnt);
+
+ /* Machine number, as defined in linux/arch/arm/tools/mach-types */
+ gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+ /* We have a console */
+ gd->have_console = 1;
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+ return ep93xx_eth_initialize(0, MAC_BASE);
+}
+
+int dram_init(void)
+{
+ unsigned int *src, *dst;
+ int i;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ const ulong bank_size = get_ram_size((long *)bank_addr[i],
+ MAX_BANK_SIZE);
+ if (bank_size) {
+ gd->bd->bi_dram[i].start = bank_addr[i];
+ gd->bd->bi_dram[i].size = bank_size;
+ }
+ }
+
+ /* copy exception vectors */
+ src = (unsigned int *)_armboot_start;
+
+#ifdef CONFIG_EDB93XX_SDCS3
+ dst = (unsigned int *)0x00000000;
+#else
+ dst = (unsigned int *)0xc0000000;
+#endif
+ memcpy(dst, src, 16 * sizeof(unsigned int));
+
+ return 0;
+}
diff --git a/board/edb93xx/flash_cfg.c b/board/edb93xx/flash_cfg.c
new file mode 100644
index 0000000..24ea210
--- /dev/null
+++ b/board/edb93xx/flash_cfg.c
@@ -0,0 +1,38 @@
+/*
+ * Flash setup for Cirrus edb93xx boards
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+
+#define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \
+ SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \
+ 1 << SMC_BCR_MW_SHIFT)
+
+void flash_cfg(void)
+{
+ struct smc_regs *smc = (struct smc_regs *)SMC_BASE;
+
+ writel(SMC_BCR6_VALUE, &smc->bcr6);
+}
diff --git a/board/edb93xx/pll_cfg.c b/board/edb93xx/pll_cfg.c
new file mode 100644
index 0000000..a687af0
--- /dev/null
+++ b/board/edb93xx/pll_cfg.c
@@ -0,0 +1,58 @@
+/*
+ * PLL setup for Cirrus edb93xx boards
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include "pll_cfg.h"
+#include "early_udelay.h"
+
+void pll_cfg(void)
+{
+ struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+ /* setup PLL1 */
+ writel(CLKSET1_VAL, &syscon->clkset1);
+
+ /*
+ * flush the pipeline
+ * writing to CLKSET1 causes the EP93xx to enter standby for between
+ * 8 ms to 16 ms, until PLL1 stabilizes
+ */
+ asm("nop");
+ asm("nop");
+ asm("nop");
+ asm("nop");
+ asm("nop");
+
+ /* setup PLL2 */
+ writel(CLKSET2_VAL, &syscon->clkset2);
+
+ /*
+ * the user's guide recommends to wait at least 1 ms for PLL2 to
+ * stabilize
+ */
+ early_udelay(1000);
+}
diff --git a/board/edb93xx/pll_cfg.h b/board/edb93xx/pll_cfg.h
new file mode 100644
index 0000000..8001e01
--- /dev/null
+++ b/board/edb93xx/pll_cfg.h
@@ -0,0 +1,72 @@
+/*
+ * PLL register values for Cirrus edb93xx boards
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/ep93xx.h>
+
+#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \
+ defined(CONFIG_EDB9302A)
+/*
+ * fclk_div: 2, nbyp1: 1, hclk_div: 5, pclk_div: 2
+ * pll1_x1: 294912000.000000, pll1_x2ip: 36864000.000000,
+ * pll1_x2: 331776000.000000, pll1_out: 331776000.000000
+ */
+#define CLKSET1_VAL (7 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
+ 8 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
+ 19 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
+ 1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \
+ 3 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \
+ SYSCON_CLKSET1_NBYP1 | \
+ 1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT)
+#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) ||\
+ defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) ||\
+ defined(CONFIG_EDB9315A)
+/*
+ * fclk_div: 2, nbyp1: 1, hclk_div: 4, pclk_div: 2
+ * pll1_x1: 3096576000.000000, pll1_x2ip: 129024000.000000,
+ * pll1_x2: 3999744000.000000, pll1_out: 1999872000.000000
+ */
+#define CLKSET1_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
+ 30 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
+ 20 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
+ 1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \
+ 2 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \
+ SYSCON_CLKSET1_NBYP1 | \
+ 1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT)
+#else
+#error "Undefined board"
+#endif
+
+/*
+ * usb_div: 4, nbyp2: 1, pll2_en: 1
+ * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000,
+ * pll2_x2: 384000000.000000, pll2_out: 192000000.000000
+ */
+#define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
+ 24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
+ 24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
+ 1 << SYSCON_CLKSET_PLL_PS_SHIFT | \
+ SYSCON_CLKSET2_PLL2_EN | \
+ SYSCON_CLKSET2_NBYP2 | \
+ 3 << SYSCON_CLKSET2_USB_DIV_SHIFT)
diff --git a/board/edb93xx/sdram_cfg.c b/board/edb93xx/sdram_cfg.c
new file mode 100644
index 0000000..201390b
--- /dev/null
+++ b/board/edb93xx/sdram_cfg.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/io.h>
+#include "sdram_cfg.h"
+#include "early_udelay.h"
+
+#define PROGRAM_MODE_REG(bank) (*(volatile uint32_t *) \
+ (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank | SDRAM_MODE_REG_VAL))
+
+#define PRECHARGE_BANK(bank) (*(volatile uint32_t *) \
+ (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank))
+
+static void force_precharge(void);
+static void setup_refresh_timer(void);
+static void program_mode_registers(void);
+
+void sdram_cfg(void)
+{
+ struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
+
+ writel(SDRAM_DEVCFG_VAL, &sdram->SDRAM_DEVCFG_REG);
+
+ /* Issue continous NOP commands */
+ writel(GLCONFIG_INIT | GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig);
+
+ early_udelay(200);
+
+ force_precharge();
+
+ setup_refresh_timer();
+
+ program_mode_registers();
+
+ /* Select normal operation mode */
+ writel(GLCONFIG_CKE, &sdram->glconfig);
+}
+
+static void force_precharge(void)
+{
+ /*
+ * Errata most EP93xx revisions say that PRECHARGE ALL isn't always
+ * issued.
+ *
+ * Do a read from each bank to make sure they're precharged
+ */
+
+ PRECHARGE_BANK(0);
+ PRECHARGE_BANK(1);
+ PRECHARGE_BANK(2);
+ PRECHARGE_BANK(3);
+}
+
+static void setup_refresh_timer(void)
+{
+ struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
+
+ /* Load refresh timer with 10 to issue refresh every 10 cycles */
+ writel(0x0a, &sdram->refrshtimr);
+
+ /*
+ * Wait at least 80 clock cycles to provide 8 refresh cycles
+ * to all SDRAMs
+ */
+ early_udelay(1);
+
+ /*
+ * Program refresh timer with normal value
+ * We need 8192 refresh cycles every 64ms
+ * at 15ns (HCLK >= 66MHz) per cycle:
+ * 64ms / 8192 = 7.8125us
+ * 7.8125us / 15ns = 520 (0x208)
+ */
+ /*
+ * TODO: redboot uses 0x1e0 for the slowest possible device
+ * but i don't understand how this value is calculated
+ */
+ writel(0x208, &sdram->refrshtimr);
+}
+
+static void program_mode_registers(void)
+{
+ PROGRAM_MODE_REG(0);
+
+#if (CONFIG_NR_DRAM_BANKS >= 2)
+ PROGRAM_MODE_REG(1);
+#endif
+
+#if (CONFIG_NR_DRAM_BANKS >= 3)
+ PROGRAM_MODE_REG(2);
+#endif
+
+#if (CONFIG_NR_DRAM_BANKS == 4)
+ PROGRAM_MODE_REG(3);
+#endif
+}
diff --git a/board/edb93xx/sdram_cfg.h b/board/edb93xx/sdram_cfg.h
new file mode 100644
index 0000000..983ff83
--- /dev/null
+++ b/board/edb93xx/sdram_cfg.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/ep93xx.h>
+
+#define SDRAM_BASE_ADDR PHYS_SDRAM_1
+
+#ifdef CONFIG_EDB93XX_SDCS0
+#define SDRAM_DEVCFG_REG devcfg0
+#elif defined(CONFIG_EDB93XX_SDCS3)
+#define SDRAM_DEVCFG_REG devcfg3
+#else
+#error "SDRAM bank configuration"
+#endif
+
+#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) ||\
+ defined(CONFIG_EDB9302A)
+/*
+ * 1x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM
+ *
+ * CLK cycle time min:
+ * @ CAS latency = 3: 7.5ns
+ * @ CAS latency = 2: 10ns
+ * We're running at 66MHz (15ns cycle time) external bus speed (HCLK),
+ * so it's safe to use CAS latency = 2
+ *
+ * RAS-to-CAS delay min:
+ * 20ns
+ * At 15ns cycle time, we use RAS-to-CAS delay = 2
+ *
+ * SROMLL = 1: Swap BA[1:0] with A[13:12], making the SDRAM appear
+ * as four blocks of 8MB size, instead of eight blocks of 4MB size:
+ *
+ * EDB9301/EDB9302:
+ *
+ * 0x00000000 - 0x007fffff
+ * 0x01000000 - 0x017fffff
+ * 0x04000000 - 0x047fffff
+ * 0x05000000 - 0x057fffff
+ *
+ *
+ * EDB9302a:
+ *
+ * 0xc0000000 - 0xc07fffff
+ * 0xc1000000 - 0xc17fffff
+ * 0xc4000000 - 0xc47fffff
+ * 0xc5000000 - 0xc57fffff
+ *
+ * BANKCOUNT = 1: This is a device with four banks
+ */
+
+#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT | \
+ SDRAM_DEVCFG_SROMLL | \
+ SDRAM_DEVCFG_CASLAT_2 | \
+ SDRAM_DEVCFG_RASTOCAS_2 | \
+ SDRAM_DEVCFG_EXTBUSWIDTH)
+
+/*
+ * 16 bit ext. bus
+ *
+ * A[22:09] is output as SYA[13:0]
+ * CAS latency: 2
+ * Burst type: sequential
+ * Burst length: 8 (required for 16 bit ext. bus)
+ * SYA[13:0] = 0x0023
+ */
+#define SDRAM_MODE_REG_VAL 0x4600
+
+#define SDRAM_BANK_SEL_0 0x00000000 /* A[22:21] = b00 */
+#define SDRAM_BANK_SEL_1 0x00200000 /* A[22:21] = b01 */
+#define SDRAM_BANK_SEL_2 0x00400000 /* A[22:21] = b10 */
+#define SDRAM_BANK_SEL_3 0x00600000 /* A[22:21] = b11 */
+
+#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) ||\
+ defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) ||\
+ defined(CONFIG_EDB9315A)
+/*
+ * 2x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM
+ *
+ * CLK cycle time min:
+ * @ CAS latency = 3: 7.5ns
+ * @ CAS latency = 2: 10ns
+ * We're running at 100MHz (10ns cycle time) external bus speed (HCLK),
+ * so it's safe to use CAS latency = 2
+ *
+ * RAS-to-CAS delay min:
+ * 20ns
+ * At 10ns cycle time, we use RAS-to-CAS delay = 2
+ *
+ * EDB9307, EDB9312, EDB9315:
+ *
+ * 0x00000000 - 0x01ffffff
+ * 0x04000000 - 0x05ffffff
+ *
+ *
+ * EDB9307a, EDB9315a:
+ *
+ * 0xc0000000 - 0xc1ffffff
+ * 0xc4000000 - 0xc5ffffff
+ */
+
+#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT | \
+ SDRAM_DEVCFG_SROMLL | \
+ SDRAM_DEVCFG_CASLAT_2 | \
+ SDRAM_DEVCFG_RASTOCAS_2)
+
+/*
+ * 32 bit ext. bus
+ *
+ * A[23:10] is output as SYA[13:0]
+ * CAS latency: 2
+ * Burst type: sequential
+ * Burst length: 4
+ * SYA[13:0] = 0x0022
+ */
+#define SDRAM_MODE_REG_VAL 0x8800
+
+#define SDRAM_BANK_SEL_0 0x00000000 /* A[23:22] = b00 */
+#define SDRAM_BANK_SEL_1 0x00400000 /* A[23:22] = b01 */
+#define SDRAM_BANK_SEL_2 0x00800000 /* A[23:22] = b10 */
+#define SDRAM_BANK_SEL_3 0x00c00000 /* A[23:22] = b11 */
+#endif
diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h
new file mode 100644
index 0000000..fec21c8
--- /dev/null
+++ b/include/configs/edb93xx.h
@@ -0,0 +1,273 @@
+/*
+ * U-boot - Configuration file for Cirrus Logic EDB93xx boards
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_MK_edb9301
+#define CONFIG_EDB9301
+#elif defined(CONFIG_MK_edb9302)
+#define CONFIG_EDB9302
+#elif defined(CONFIG_MK_edb9302a)
+#define CONFIG_EDB9302A
+#elif defined(CONFIG_MK_edb9307)
+#define CONFIG_EDB9307
+#elif defined(CONFIG_MK_edb9307a)
+#define CONFIG_EDB9307A
+#elif defined(CONFIG_MK_edb9312)
+#define CONFIG_EDB9312
+#elif defined(CONFIG_MK_edb9315)
+#define CONFIG_EDB9315
+#elif defined(CONFIG_MK_edb9315a)
+#define CONFIG_EDB9315A
+#else
+#error "no board defined"
+#endif
+
+/* Initial environment and monitor configuration options. */
+#define CONFIG_BOOTDELAY 2
+#define CONFIG_CMDLINE_TAG 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_BOOTARGS "root=/dev/nfs console=ttyAM0,115200 ip=dhcp"
+#define CONFIG_BOOTFILE "edb93xx.img"
+
+#define CONFIG_SYS_HUSH_PARSER 1
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#ifdef CONFIG_EDB9301
+#define CONFIG_EP9301
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9301
+#define CONFIG_SYS_PROMPT "EDB9301> "
+#define CONFIG_ENV_SECT_SIZE 0x00020000
+#elif defined(CONFIG_EDB9302)
+#define CONFIG_EP9302
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302
+#define CONFIG_SYS_PROMPT "EDB9302> "
+#define CONFIG_ENV_SECT_SIZE 0x00020000
+#elif defined(CONFIG_EDB9302A)
+#define CONFIG_EP9302
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302A
+#define CONFIG_SYS_PROMPT "EDB9302A> "
+#define CONFIG_ENV_SECT_SIZE 0x00020000
+#elif defined(CONFIG_EDB9307)
+#define CONFIG_EP9307
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307
+#define CONFIG_SYS_PROMPT "EDB9307> "
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#elif defined(CONFIG_EDB9307A)
+#define CONFIG_EP9307
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307A
+#define CONFIG_SYS_PROMPT "EDB9307A> "
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#elif defined(CONFIG_EDB9312)
+#define CONFIG_EP9312
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9312
+#define CONFIG_SYS_PROMPT "EDB9312> "
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#elif defined(CONFIG_EDB9315)
+#define CONFIG_EP9315
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315
+#define CONFIG_SYS_PROMPT "EDB9315> "
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#elif defined(CONFIG_EDB9315A)
+#define CONFIG_EP9315
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315A
+#define CONFIG_SYS_PROMPT "EDB9315A> "
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#else
+#error "no board defined"
+#endif
+
+/* High-level configuration options */
+#define CONFIG_ARM920T 1 /* This is an ARM920T core... */
+#define CONFIG_EP93XX 1 /* in a Cirrus Logic 93xx SoC */
+
+#define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456 clock */
+#define CONFIG_SYS_HZ 1000 /* decr freq: 1 ms ticks */
+#undef CONFIG_USE_IRQ /* Don't need IRQ/FIQ */
+
+/* Monitor configuration */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#undef CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+
+#define CONFIG_SYS_LONGHELP /* Enable "long" help in mon */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
+/* Print buffer size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+/* Boot argument buffer size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
+
+/* Serial port hardware configuration */
+#define CONFIG_PL010_SERIAL
+#define CONFIG_CONS_INDEX 0
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+#define CONFIG_SYS_SERIAL0 0x808C0000
+#define CONFIG_SYS_SERIAL1 0x808D0000
+#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
+ (void *)CONFIG_SYS_SERIAL1}
+
+/* Status LED */
+#define CONFIG_STATUS_LED 1 /* Status LED enabled */
+#define CONFIG_BOARD_SPECIFIC_LED 1
+#define STATUS_LED_GREEN 0
+#define STATUS_LED_RED 1
+/* Green */
+#define STATUS_LED_BIT STATUS_LED_GREEN
+#define STATUS_LED_STATE STATUS_LED_ON
+#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
+/* Red */
+#define STATUS_LED_BIT1 STATUS_LED_RED
+#define STATUS_LED_STATE1 STATUS_LED_OFF
+#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
+/* Optional value */
+#define STATUS_LED_BOOT STATUS_LED_BIT
+
+/* Network hardware configuration */
+#define CONFIG_DRIVER_EP93XX_MAC
+#define CONFIG_MII_SUPPRESS_PREAMBLE
+#define CONFIG_MII
+#define CONFIG_PHY_ADDR 1
+#define CONFIG_NET_MULTI
+#undef CONFIG_NETCONSOLE
+
+/* SDRAM configuration */
+#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302)
+/*
+ * EDB9301/2 has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
+ * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
+ * the SROMLL bit on the processor, resulting in this non-contiguous memory map.
+ */
+#define CONFIG_NR_DRAM_BANKS 4
+#define PHYS_SDRAM_1 0x00000000
+#define PHYS_SDRAM_SIZE_1 0x00800000
+#define PHYS_SDRAM_2 0x01000000
+#define PHYS_SDRAM_SIZE_2 0x00800000
+#define PHYS_SDRAM_3 0x04000000
+#define PHYS_SDRAM_SIZE_3 0x00800000
+#define PHYS_SDRAM_4 0x05000000
+#define PHYS_SDRAM_SIZE_4 0x00800000
+#define CONFIG_EDB93XX_SDCS3
+#define CONFIG_SYS_MEMTEST_START 0x00100000
+#define CONFIG_SYS_MEMTEST_END 0x007fffff
+
+#elif defined(CONFIG_EDB9302A)
+/*
+ * EDB9302a has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
+ * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
+ * the SROMLL bit on the processor, resulting in this non-contiguous memory map.
+ */
+#define CONFIG_NR_DRAM_BANKS 4
+#define PHYS_SDRAM_1 0xc0000000
+#define PHYS_SDRAM_SIZE_1 0x00800000
+#define PHYS_SDRAM_2 0xc1000000
+#define PHYS_SDRAM_SIZE_2 0x00800000
+#define PHYS_SDRAM_3 0xc4000000
+#define PHYS_SDRAM_SIZE_3 0x00800000
+#define PHYS_SDRAM_4 0xc5000000
+#define PHYS_SDRAM_SIZE_4 0x00800000
+#define CONFIG_EDB93XX_SDCS0
+#define CONFIG_SYS_MEMTEST_START 0xc0100000
+#define CONFIG_SYS_MEMTEST_END 0xc07fffff
+
+#elif defined(CONFIG_EDB9307) || defined CONFIG_EDB9312 || \
+ defined(CONFIG_EDB9315)
+/*
+ * The EDB9307, EDB9312, and EDB9315 have 2 banks of SDRAM consisting of
+ * 2x Samsung K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of
+ * 64 MB of SDRAM.
+ */
+#define CONFIG_NR_DRAM_BANKS 2
+#define PHYS_SDRAM_1 0x00000000
+#define PHYS_SDRAM_SIZE_1 0x02000000
+#define PHYS_SDRAM_2 0x04000000
+#define PHYS_SDRAM_SIZE_2 0x02000000
+#define CONFIG_EDB93XX_SDCS3
+#define CONFIG_SYS_MEMTEST_START 0x00100000
+#define CONFIG_SYS_MEMTEST_END 0x01e00000
+
+#elif defined(CONFIG_EDB9307A) || defined(CONFIG_EDB9315A)
+/*
+ * The EDB9307A and EDB9315A have 2 banks of SDRAM consisting of 2x Samsung
+ * K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of 64 MB of SDRAM.
+ */
+#define CONFIG_NR_DRAM_BANKS 2
+#define PHYS_SDRAM_1 0xc0000000
+#define PHYS_SDRAM_SIZE_1 0x02000000
+#define PHYS_SDRAM_2 0xc4000000
+#define PHYS_SDRAM_SIZE_2 0x02000000
+#define CONFIG_EDB93XX_SDCS0
+#define CONFIG_SYS_MEMTEST_START 0xc0100000
+#define CONFIG_SYS_MEMTEST_END 0xc1e00000
+#endif
+
+#if defined(CONFIG_EDB93XX_SDCS3)
+#define CONFIG_SYS_LOAD_ADDR 0x01000000 /* Default load address */
+#elif defined(CONFIG_EDB93XX_SDCS0)
+#define CONFIG_SYS_LOAD_ADDR 0xc1000000 /* Default load address */
+#endif
+
+/* Must match kernel config */
+#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
+
+/* Run-time memory allocatons */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+#define CONFIG_STACKSIZE (128 * 1024)
+
+#if defined(CONFIG_USE_IRQ)
+#define CONFIG_STACKSIZE_IRQ (4 * 1024)
+#define CONFIG_STACKSIZE_FIQ (4 * 1024)
+#endif
+
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
+
+/* -----------------------------------------------------------------------------
+ * FLASH and environment organization
+ *
+ * The EDB9301 and EDB9302(a) have 1 bank of flash memory at 0x60000000
+ * consisting of 1x Intel TE28F128J3C-150 128 Mbit flash on a 16-bit data bus,
+ * for a total of 16 MB of CFI-compatible flash.
+ *
+ * The EDB9307(a), EDB9312, and EDB9315(a) have 1 bank of flash memory at
+ * 0x60000000 consisting of 2x Micron MT28F128J3-12 128 Mbit flash on a 32-bit
+ * data bus, for a total of 32 MB of CFI-compatible flash.
+ *
+ * EDB9301/02(a) EDB9307(a)/12/15(a)
+ * 0x60000000 - 0x0003FFFF u-boot u-boot
+ * 0x60040000 - 0x0005FFFF environment #1 environment #1
+ * 0x60060000 - 0x0007FFFF environment #2 environment #1 (continued)
+ * 0x60080000 - 0x0009FFFF unused environment #2
+ * 0x600A0000 - 0x000BFFFF unused environment #2 (continued)
+ * 0x600C0000 - 0x00FFFFFF unused unused
+ * 0x61000000 - 0x01FFFFFF not present unused
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 128
+
+#define PHYS_FLASH_1 0x60000000
+#define CONFIG_SYS_FLASH_BASE (PHYS_FLASH_1)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+
+#define CONFIG_ENV_OVERWRITE /* Vendor params unprotected */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR 0x60040000
+
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+#endif /* !defined (__CONFIG_H) */
--
1.6.5
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH 1/3] ARM: Add support for EP93xx SoCs
2010-01-24 16:56 ` [U-Boot] [PATCH 1/3] ARM: Add support for EP93xx SoCs Matthias Kaehlcke
@ 2010-01-31 18:53 ` Tom
2010-02-01 7:24 ` Matthias Kaehlcke
0 siblings, 1 reply; 12+ messages in thread
From: Tom @ 2010-01-31 18:53 UTC (permalink / raw)
To: u-boot
Matthias Kaehlcke wrote:
> Add support for the Cirrus EP93xx platform
>
> Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
> ---
> cpu/arm920t/ep93xx/Makefile | 56 ++++
> cpu/arm920t/ep93xx/cpu.c | 51 +++
> cpu/arm920t/ep93xx/led.c | 101 ++++++
> cpu/arm920t/ep93xx/lowlevel_init.S | 65 ++++
> cpu/arm920t/ep93xx/speed.c | 110 +++++++
> cpu/arm920t/ep93xx/timer.c | 168 ++++++++++
> cpu/arm920t/ep93xx/u-boot.lds | 59 ++++
> include/asm-arm/arch-ep93xx/ep93xx.h | 595 ++++++++++++++++++++++++++++++++++
> include/common.h | 3 +-
> 9 files changed, 1207 insertions(+), 1 deletions(-)
> create mode 100644 cpu/arm920t/ep93xx/Makefile
> create mode 100644 cpu/arm920t/ep93xx/cpu.c
> create mode 100644 cpu/arm920t/ep93xx/led.c
> create mode 100644 cpu/arm920t/ep93xx/lowlevel_init.S
> create mode 100644 cpu/arm920t/ep93xx/speed.c
> create mode 100644 cpu/arm920t/ep93xx/timer.c
> create mode 100644 cpu/arm920t/ep93xx/u-boot.lds
> create mode 100644 include/asm-arm/arch-ep93xx/ep93xx.h
This looks good.
Ack-ed.
Tom
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH 3/3] Add support for EDB93xx boards
2010-01-24 16:56 ` [U-Boot] [PATCH 3/3] Add support for EDB93xx boards Matthias Kaehlcke
@ 2010-01-31 19:00 ` Tom
0 siblings, 0 replies; 12+ messages in thread
From: Tom @ 2010-01-31 19:00 UTC (permalink / raw)
To: u-boot
Matthias Kaehlcke wrote:
> Added support for the following EDB93xx boards:
>
> EDB9301
> EDB9302
> EDB9302A
> EDB9307
> EDB9307A
> EDB93012
> EDB9315
> EDB9315A
>
> Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
> ---
> MAINTAINERS | 10 ++
> MAKEALL | 8 ++
> Makefile | 10 ++
> board/edb93xx/Makefile | 50 ++++++++
> board/edb93xx/config.mk | 33 +++++
> board/edb93xx/early_udelay.h | 34 +++++
> board/edb93xx/edb93xx.c | 109 +++++++++++++++++
> board/edb93xx/flash_cfg.c | 38 ++++++
> board/edb93xx/pll_cfg.c | 58 +++++++++
> board/edb93xx/pll_cfg.h | 72 +++++++++++
> board/edb93xx/sdram_cfg.c | 117 ++++++++++++++++++
> board/edb93xx/sdram_cfg.h | 144 ++++++++++++++++++++++
> include/configs/edb93xx.h | 273 ++++++++++++++++++++++++++++++++++++++++++
> 13 files changed, 956 insertions(+), 0 deletions(-)
> create mode 100644 board/edb93xx/Makefile
> create mode 100644 board/edb93xx/config.mk
> create mode 100644 board/edb93xx/early_udelay.h
> create mode 100644 board/edb93xx/edb93xx.c
> create mode 100644 board/edb93xx/flash_cfg.c
> create mode 100644 board/edb93xx/pll_cfg.c
> create mode 100644 board/edb93xx/pll_cfg.h
> create mode 100644 board/edb93xx/sdram_cfg.c
> create mode 100644 board/edb93xx/sdram_cfg.h
> create mode 100644 include/configs/edb93xx.h
>
<snip>
> --- a/MAKEALL
> +++ b/MAKEALL
> @@ -554,6 +554,14 @@ LIST_ARM9=" \
> cp946es \
> cp966 \
> da830evm \
> + edb9301 \
> + edb9302 \
> + edb9302a \
> + edb9307 \
> + edb9307a \
ws trailing space
> + edb9312 \
> + edb9315 \
> + edb9315a \
<snip>
> +
> +int dram_init(void)
> +{
> + unsigned int *src, *dst;
> + int i;
> +
> + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
> + const ulong bank_size = get_ram_size((long *)bank_addr[i],
> + MAX_BANK_SIZE);
> + if (bank_size) {
> + gd->bd->bi_dram[i].start = bank_addr[i];
> + gd->bd->bi_dram[i].size = bank_size;
> + }
> + }
> +
> + /* copy exception vectors */
> + src = (unsigned int *)_armboot_start;
> +
> +#ifdef CONFIG_EDB93XX_SDCS3
> + dst = (unsigned int *)0x00000000;
> +#else
> + dst = (unsigned int *)0xc0000000;
> +#endif
This could be reduced to
dst = (unsigned int *)PHYS_SDRAM_1;
> + memcpy(dst, src, 16 * sizeof(unsigned int));
> +
> + return 0;
> +}
<snip>
> --- /dev/null
> +++ b/board/edb93xx/pll_cfg.h
> @@ -0,0 +1,72 @@
> +/*
> + * PLL register values for Cirrus edb93xx boards
> + *
> + * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <config.h>
> +#include <asm/arch/ep93xx.h>
> +
> +#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \
> + defined(CONFIG_EDB9302A)
> +/*
> + * fclk_div: 2, nbyp1: 1, hclk_div: 5, pclk_div: 2
> + * pll1_x1: 294912000.000000, pll1_x2ip: 36864000.000000,
> + * pll1_x2: 331776000.000000, pll1_out: 331776000.000000
> + */
> +#define CLKSET1_VAL (7 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
> + 8 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
> + 19 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
> + 1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \
> + 3 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \
> + SYSCON_CLKSET1_NBYP1 | \
> + 1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT)
ws trailing spaces
Other macros have similar issues
> +#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) ||\
> + defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) ||\
> + defined(CONFIG_EDB9315A)
> +/*
> + * fclk_div: 2, nbyp1: 1, hclk_div: 4, pclk_div: 2
> + * pll1_x1: 3096576000.000000, pll1_x2ip: 129024000.000000,
> + * pll1_x2: 3999744000.000000, pll1_out: 1999872000.000000
> + */
<snip>
> +static void setup_refresh_timer(void)
> +{
> + struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
> +
> + /* Load refresh timer with 10 to issue refresh every 10 cycles */
> + writel(0x0a, &sdram->refrshtimr);
> +
> + /*
> + * Wait at least 80 clock cycles to provide 8 refresh cycles
> + * to all SDRAMs
> + */
> + early_udelay(1);
> +
> + /*
> + * Program refresh timer with normal value
> + * We need 8192 refresh cycles every 64ms
> + * at 15ns (HCLK >= 66MHz) per cycle:
> + * 64ms / 8192 = 7.8125us
> + * 7.8125us / 15ns = 520 (0x208)
> + */
Good comment!
> + /*
> + * TODO: redboot uses 0x1e0 for the slowest possible device
> + * but i don't understand how this value is calculated
> + */
> + writel(0x208, &sdram->refrshtimr);
> +}
> +
> +static void program_mode_registers(void)
> +{
> + PROGRAM_MODE_REG(0);
> +
It looks like all this macros is doing is reading memory.
Is this correct ?
If so, please add a comment
> +#if (CONFIG_NR_DRAM_BANKS >= 2)
> + PROGRAM_MODE_REG(1);
> +#endif
> +
> +#if (CONFIG_NR_DRAM_BANKS >= 3)
> + PROGRAM_MODE_REG(2);
> +#endif
> +
> +#if (CONFIG_NR_DRAM_BANKS == 4)
> + PROGRAM_MODE_REG(3);
> +#endif
> +}
<snip>
> +#define CONFIG_SYS_MEMTEST_START 0xc0100000
> +#define CONFIG_SYS_MEMTEST_END 0xc1e00000
> +#endif
> +
> +#if defined(CONFIG_EDB93XX_SDCS3)
> +#define CONFIG_SYS_LOAD_ADDR 0x01000000 /* Default load address */
> +#elif defined(CONFIG_EDB93XX_SDCS0)
> +#define CONFIG_SYS_LOAD_ADDR 0xc1000000 /* Default load address */
> +#endif
This could be reduced to
+#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x01000000) /* Default load address */
Tom
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH 1/3] ARM: Add support for EP93xx SoCs
2010-01-31 18:53 ` Tom
@ 2010-02-01 7:24 ` Matthias Kaehlcke
0 siblings, 0 replies; 12+ messages in thread
From: Matthias Kaehlcke @ 2010-02-01 7:24 UTC (permalink / raw)
To: u-boot
El Sun, Jan 31, 2010 at 12:53:37PM -0600 Tom ha dit:
> Matthias Kaehlcke wrote:
> >Add support for the Cirrus EP93xx platform
> >
> >Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
> >---
> > cpu/arm920t/ep93xx/Makefile | 56 ++++
> > cpu/arm920t/ep93xx/cpu.c | 51 +++
> > cpu/arm920t/ep93xx/led.c | 101 ++++++
> > cpu/arm920t/ep93xx/lowlevel_init.S | 65 ++++
> > cpu/arm920t/ep93xx/speed.c | 110 +++++++
> > cpu/arm920t/ep93xx/timer.c | 168 ++++++++++
> > cpu/arm920t/ep93xx/u-boot.lds | 59 ++++
> > include/asm-arm/arch-ep93xx/ep93xx.h | 595 ++++++++++++++++++++++++++++++++++
> > include/common.h | 3 +-
> > 9 files changed, 1207 insertions(+), 1 deletions(-)
> > create mode 100644 cpu/arm920t/ep93xx/Makefile
> > create mode 100644 cpu/arm920t/ep93xx/cpu.c
> > create mode 100644 cpu/arm920t/ep93xx/led.c
> > create mode 100644 cpu/arm920t/ep93xx/lowlevel_init.S
> > create mode 100644 cpu/arm920t/ep93xx/speed.c
> > create mode 100644 cpu/arm920t/ep93xx/timer.c
> > create mode 100644 cpu/arm920t/ep93xx/u-boot.lds
> > create mode 100644 include/asm-arm/arch-ep93xx/ep93xx.h
>
> This looks good.
> Ack-ed.
great :)
thanks for reviewing all these patches!
this week i'll respond with a patch to the issues you raised about the
board patch
--
Matthias Kaehlcke
Embedded Linux Developer
Barcelona
We can't solve problems by using the same kind
of thinking we used when we created them
(Albert Einstein)
.''`.
using free software / Debian GNU/Linux | http://debian.org : :' :
`. `'`
gpg --keyserver pgp.mit.edu --recv-keys 47D8E5D4 `-
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH 3/3] Add support for EDB93xx boards
[not found] <cover.1265053904.git.matthias@kaehlcke.net>
@ 2010-02-01 20:29 ` Matthias Kaehlcke
0 siblings, 0 replies; 12+ messages in thread
From: Matthias Kaehlcke @ 2010-02-01 20:29 UTC (permalink / raw)
To: u-boot
Added support for the following EDB93xx boards:
EDB9301
EDB9302
EDB9302A
EDB9307
EDB9307A
EDB93012
EDB9315
EDB9315A
Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
---
Changes with respect to rev5:
* fixed whitespace issues
* simplified copying of exception vectors in dram_init()
* added comment about programming of SDRAM mode registers
* simplified definition of CONFIG_SYS_LOAD_ADDR
MAINTAINERS | 10 ++
MAKEALL | 8 ++
Makefile | 10 ++
board/edb93xx/Makefile | 50 ++++++++
board/edb93xx/config.mk | 33 +++++
board/edb93xx/early_udelay.h | 34 ++++++
board/edb93xx/edb93xx.c | 104 ++++++++++++++++
board/edb93xx/flash_cfg.c | 38 ++++++
board/edb93xx/pll_cfg.c | 58 +++++++++
board/edb93xx/pll_cfg.h | 72 +++++++++++
board/edb93xx/sdram_cfg.c | 123 +++++++++++++++++++
board/edb93xx/sdram_cfg.h | 144 ++++++++++++++++++++++
include/configs/edb93xx.h | 270 ++++++++++++++++++++++++++++++++++++++++++
13 files changed, 954 insertions(+), 0 deletions(-)
create mode 100644 board/edb93xx/Makefile
create mode 100644 board/edb93xx/config.mk
create mode 100644 board/edb93xx/early_udelay.h
create mode 100644 board/edb93xx/edb93xx.c
create mode 100644 board/edb93xx/flash_cfg.c
create mode 100644 board/edb93xx/pll_cfg.c
create mode 100644 board/edb93xx/pll_cfg.h
create mode 100644 board/edb93xx/sdram_cfg.c
create mode 100644 board/edb93xx/sdram_cfg.h
create mode 100644 include/configs/edb93xx.h
diff --git a/MAINTAINERS b/MAINTAINERS
index e8ba4bc..12a742e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -598,6 +598,16 @@ Gary Jennejohn <garyj@denx.de>
smdk2400 ARM920T
trab ARM920T
+Matthias Kaehlcke <matthias@kaehlcke.net>
+ edb9301 ARM920T (EP9301)
+ edb9302 ARM920T (EP9302)
+ edb9302a ARM920T (EP9302)
+ edb9307 ARM920T (EP9307)
+ edb9307a ARM920T (EP9307)
+ edb9312 ARM920T (EP9312)
+ edb9315 ARM920T (EP9315)
+ edb9315a ARM920T (EP9315)
+
Konstantin Kletschke <kletschke@synertronixx.de>
scb9328 ARM920T
diff --git a/MAKEALL b/MAKEALL
index afdc1b5..864f1fe 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -554,6 +554,14 @@ LIST_ARM9=" \
cp946es \
cp966 \
da830evm \
+ edb9301 \
+ edb9302 \
+ edb9302a \
+ edb9307 \
+ edb9307a \
+ edb9312 \
+ edb9315 \
+ edb9315a \
imx27lite \
lpd7a400 \
mv88f6281gtw_ge \
diff --git a/Makefile b/Makefile
index 0f60925..5b4ab56 100644
--- a/Makefile
+++ b/Makefile
@@ -2412,6 +2412,16 @@ caddy2_config \
vme8349_config: unconfig
@$(MKCONFIG) -t $(@:_config=) vme8349 ppc mpc83xx vme8349 esd
+edb9301_config \
+edb9302_config \
+edb9302a_config \
+edb9307_config \
+edb9307a_config \
+edb9312_config \
+edb9315_config \
+edb9315a_config: unconfig
+ @$(MKCONFIG) -t $(@:_config=) edb93xx arm arm920t edb93xx NULL ep93xx
+
#########################################################################
## MPC85xx Systems
#########################################################################
diff --git a/board/edb93xx/Makefile b/board/edb93xx/Makefile
new file mode 100644
index 0000000..e2e2636
--- /dev/null
+++ b/board/edb93xx/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := edb93xx.o flash_cfg.o pll_cfg.o sdram_cfg.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/edb93xx/config.mk b/board/edb93xx/config.mk
new file mode 100644
index 0000000..b2fc6fa
--- /dev/null
+++ b/board/edb93xx/config.mk
@@ -0,0 +1,33 @@
+LDSCRIPT := $(SRCTREE)/cpu/arm920t/ep93xx/u-boot.lds
+
+ifdef CONFIG_EDB9301
+TEXT_BASE = 0x05700000
+endif
+
+ifdef CONFIG_EDB9302
+TEXT_BASE = 0x05700000
+endif
+
+ifdef CONFIG_EDB9302A
+TEXT_BASE = 0xc5700000
+endif
+
+ifdef CONFIG_EDB9307
+TEXT_BASE = 0x01f00000
+endif
+
+ifdef CONFIG_EDB9307A
+TEXT_BASE = 0xc1f00000
+endif
+
+ifdef CONFIG_EDB9312
+TEXT_BASE = 0x01f00000
+endif
+
+ifdef CONFIG_EDB9315
+TEXT_BASE = 0x01f00000
+endif
+
+ifdef CONFIG_EDB9315A
+TEXT_BASE = 0xc1f00000
+endif
diff --git a/board/edb93xx/early_udelay.h b/board/edb93xx/early_udelay.h
new file mode 100644
index 0000000..3b26b3f
--- /dev/null
+++ b/board/edb93xx/early_udelay.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* delay execution before timers are initialized */
+static inline void early_udelay(uint32_t usecs)
+{
+ /* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */
+ register uint32_t loops = (usecs * 1000) / 20;
+
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0" (loops));
+}
diff --git a/board/edb93xx/edb93xx.c b/board/edb93xx/edb93xx.c
new file mode 100644
index 0000000..4df2246
--- /dev/null
+++ b/board/edb93xx/edb93xx.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * (C) Copyright 2002 2003
+ * Network Audio Technologies, Inc. <www.netaudiotech.com>
+ * Adam Bezanson <bezanson@netaudiotech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MAX_BANK_SIZE 0x04000000 /* 64 MB */
+
+static ulong const bank_addr[CONFIG_NR_DRAM_BANKS] = {
+ PHYS_SDRAM_1,
+#ifdef PHYS_SDRAM_2
+ PHYS_SDRAM_2,
+#endif
+#ifdef PHYS_SDRAM_3
+ PHYS_SDRAM_3,
+#endif
+#ifdef PHYS_SDRAM_4
+ PHYS_SDRAM_4
+#endif
+};
+
+int board_init(void)
+{
+ struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+ icache_enable();
+
+#ifdef USE_920T_MMU
+ dcache_enable();
+#endif
+
+ /*
+ * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of
+ * 14.7456/2 MHz
+ */
+ uint32_t value = readl(&syscon->pwrcnt);
+ value |= SYSCON_PWRCNT_UART_BAUD;
+ writel(value, &syscon->pwrcnt);
+
+ /* Machine number, as defined in linux/arch/arm/tools/mach-types */
+ gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+ /* We have a console */
+ gd->have_console = 1;
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+ return ep93xx_eth_initialize(0, MAC_BASE);
+}
+
+int dram_init(void)
+{
+ unsigned int *src, *dst;
+ int i;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ const ulong bank_size = get_ram_size((long *)bank_addr[i],
+ MAX_BANK_SIZE);
+ if (bank_size) {
+ gd->bd->bi_dram[i].start = bank_addr[i];
+ gd->bd->bi_dram[i].size = bank_size;
+ }
+ }
+
+ /* copy exception vectors */
+ src = (unsigned int *)_armboot_start;
+ dst = (unsigned int *)PHYS_SDRAM_1;
+ memcpy(dst, src, 16 * sizeof(unsigned int));
+
+ return 0;
+}
diff --git a/board/edb93xx/flash_cfg.c b/board/edb93xx/flash_cfg.c
new file mode 100644
index 0000000..a4c2048
--- /dev/null
+++ b/board/edb93xx/flash_cfg.c
@@ -0,0 +1,38 @@
+/*
+ * Flash setup for Cirrus edb93xx boards
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+
+#define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \
+ SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \
+ 1 << SMC_BCR_MW_SHIFT)
+
+void flash_cfg(void)
+{
+ struct smc_regs *smc = (struct smc_regs *)SMC_BASE;
+
+ writel(SMC_BCR6_VALUE, &smc->bcr6);
+}
diff --git a/board/edb93xx/pll_cfg.c b/board/edb93xx/pll_cfg.c
new file mode 100644
index 0000000..a687af0
--- /dev/null
+++ b/board/edb93xx/pll_cfg.c
@@ -0,0 +1,58 @@
+/*
+ * PLL setup for Cirrus edb93xx boards
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include "pll_cfg.h"
+#include "early_udelay.h"
+
+void pll_cfg(void)
+{
+ struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+ /* setup PLL1 */
+ writel(CLKSET1_VAL, &syscon->clkset1);
+
+ /*
+ * flush the pipeline
+ * writing to CLKSET1 causes the EP93xx to enter standby for between
+ * 8 ms to 16 ms, until PLL1 stabilizes
+ */
+ asm("nop");
+ asm("nop");
+ asm("nop");
+ asm("nop");
+ asm("nop");
+
+ /* setup PLL2 */
+ writel(CLKSET2_VAL, &syscon->clkset2);
+
+ /*
+ * the user's guide recommends to wait at least 1 ms for PLL2 to
+ * stabilize
+ */
+ early_udelay(1000);
+}
diff --git a/board/edb93xx/pll_cfg.h b/board/edb93xx/pll_cfg.h
new file mode 100644
index 0000000..0b6f469
--- /dev/null
+++ b/board/edb93xx/pll_cfg.h
@@ -0,0 +1,72 @@
+/*
+ * PLL register values for Cirrus edb93xx boards
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/ep93xx.h>
+
+#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \
+ defined(CONFIG_EDB9302A)
+/*
+ * fclk_div: 2, nbyp1: 1, hclk_div: 5, pclk_div: 2
+ * pll1_x1: 294912000.000000, pll1_x2ip: 36864000.000000,
+ * pll1_x2: 331776000.000000, pll1_out: 331776000.000000
+ */
+#define CLKSET1_VAL (7 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
+ 8 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
+ 19 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
+ 1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \
+ 3 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \
+ SYSCON_CLKSET1_NBYP1 | \
+ 1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT)
+#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) || \
+ defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) || \
+ defined(CONFIG_EDB9315A)
+/*
+ * fclk_div: 2, nbyp1: 1, hclk_div: 4, pclk_div: 2
+ * pll1_x1: 3096576000.000000, pll1_x2ip: 129024000.000000,
+ * pll1_x2: 3999744000.000000, pll1_out: 1999872000.000000
+ */
+#define CLKSET1_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
+ 30 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
+ 20 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
+ 1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \
+ 2 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \
+ SYSCON_CLKSET1_NBYP1 | \
+ 1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT)
+#else
+#error "Undefined board"
+#endif
+
+/*
+ * usb_div: 4, nbyp2: 1, pll2_en: 1
+ * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000,
+ * pll2_x2: 384000000.000000, pll2_out: 192000000.000000
+ */
+#define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
+ 24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
+ 24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
+ 1 << SYSCON_CLKSET_PLL_PS_SHIFT | \
+ SYSCON_CLKSET2_PLL2_EN | \
+ SYSCON_CLKSET2_NBYP2 | \
+ 3 << SYSCON_CLKSET2_USB_DIV_SHIFT)
diff --git a/board/edb93xx/sdram_cfg.c b/board/edb93xx/sdram_cfg.c
new file mode 100644
index 0000000..6155f0e
--- /dev/null
+++ b/board/edb93xx/sdram_cfg.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/io.h>
+#include "sdram_cfg.h"
+#include "early_udelay.h"
+
+#define PROGRAM_MODE_REG(bank) (*(volatile uint32_t *) \
+ (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank | SDRAM_MODE_REG_VAL))
+
+#define PRECHARGE_BANK(bank) (*(volatile uint32_t *) \
+ (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank))
+
+static void force_precharge(void);
+static void setup_refresh_timer(void);
+static void program_mode_registers(void);
+
+void sdram_cfg(void)
+{
+ struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
+
+ writel(SDRAM_DEVCFG_VAL, &sdram->SDRAM_DEVCFG_REG);
+
+ /* Issue continous NOP commands */
+ writel(GLCONFIG_INIT | GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig);
+
+ early_udelay(200);
+
+ force_precharge();
+
+ setup_refresh_timer();
+
+ program_mode_registers();
+
+ /* Select normal operation mode */
+ writel(GLCONFIG_CKE, &sdram->glconfig);
+}
+
+static void force_precharge(void)
+{
+ /*
+ * Errata most EP93xx revisions say that PRECHARGE ALL isn't always
+ * issued.
+ *
+ * Do a read from each bank to make sure they're precharged
+ */
+
+ PRECHARGE_BANK(0);
+ PRECHARGE_BANK(1);
+ PRECHARGE_BANK(2);
+ PRECHARGE_BANK(3);
+}
+
+static void setup_refresh_timer(void)
+{
+ struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
+
+ /* Load refresh timer with 10 to issue refresh every 10 cycles */
+ writel(0x0a, &sdram->refrshtimr);
+
+ /*
+ * Wait at least 80 clock cycles to provide 8 refresh cycles
+ * to all SDRAMs
+ */
+ early_udelay(1);
+
+ /*
+ * Program refresh timer with normal value
+ * We need 8192 refresh cycles every 64ms
+ * at 15ns (HCLK >= 66MHz) per cycle:
+ * 64ms / 8192 = 7.8125us
+ * 7.8125us / 15ns = 520 (0x208)
+ */
+ /*
+ * TODO: redboot uses 0x1e0 for the slowest possible device
+ * but i don't understand how this value is calculated
+ */
+ writel(0x208, &sdram->refrshtimr);
+}
+
+static void program_mode_registers(void)
+{
+ /*
+ * The mode registers are programmed by performing a read from each
+ * SDRAM bank. The value of the address that is read defines the value
+ * that is written into the mode register
+ */
+
+ PROGRAM_MODE_REG(0);
+
+#if (CONFIG_NR_DRAM_BANKS >= 2)
+ PROGRAM_MODE_REG(1);
+#endif
+
+#if (CONFIG_NR_DRAM_BANKS >= 3)
+ PROGRAM_MODE_REG(2);
+#endif
+
+#if (CONFIG_NR_DRAM_BANKS == 4)
+ PROGRAM_MODE_REG(3);
+#endif
+}
diff --git a/board/edb93xx/sdram_cfg.h b/board/edb93xx/sdram_cfg.h
new file mode 100644
index 0000000..757b63c
--- /dev/null
+++ b/board/edb93xx/sdram_cfg.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/ep93xx.h>
+
+#define SDRAM_BASE_ADDR PHYS_SDRAM_1
+
+#ifdef CONFIG_EDB93XX_SDCS0
+#define SDRAM_DEVCFG_REG devcfg0
+#elif defined(CONFIG_EDB93XX_SDCS3)
+#define SDRAM_DEVCFG_REG devcfg3
+#else
+#error "SDRAM bank configuration"
+#endif
+
+#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \
+ defined(CONFIG_EDB9302A)
+/*
+ * 1x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM
+ *
+ * CLK cycle time min:
+ * @ CAS latency = 3: 7.5ns
+ * @ CAS latency = 2: 10ns
+ * We're running at 66MHz (15ns cycle time) external bus speed (HCLK),
+ * so it's safe to use CAS latency = 2
+ *
+ * RAS-to-CAS delay min:
+ * 20ns
+ * At 15ns cycle time, we use RAS-to-CAS delay = 2
+ *
+ * SROMLL = 1: Swap BA[1:0] with A[13:12], making the SDRAM appear
+ * as four blocks of 8MB size, instead of eight blocks of 4MB size:
+ *
+ * EDB9301/EDB9302:
+ *
+ * 0x00000000 - 0x007fffff
+ * 0x01000000 - 0x017fffff
+ * 0x04000000 - 0x047fffff
+ * 0x05000000 - 0x057fffff
+ *
+ *
+ * EDB9302a:
+ *
+ * 0xc0000000 - 0xc07fffff
+ * 0xc1000000 - 0xc17fffff
+ * 0xc4000000 - 0xc47fffff
+ * 0xc5000000 - 0xc57fffff
+ *
+ * BANKCOUNT = 1: This is a device with four banks
+ */
+
+#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT | \
+ SDRAM_DEVCFG_SROMLL | \
+ SDRAM_DEVCFG_CASLAT_2 | \
+ SDRAM_DEVCFG_RASTOCAS_2 | \
+ SDRAM_DEVCFG_EXTBUSWIDTH)
+
+/*
+ * 16 bit ext. bus
+ *
+ * A[22:09] is output as SYA[13:0]
+ * CAS latency: 2
+ * Burst type: sequential
+ * Burst length: 8 (required for 16 bit ext. bus)
+ * SYA[13:0] = 0x0023
+ */
+#define SDRAM_MODE_REG_VAL 0x4600
+
+#define SDRAM_BANK_SEL_0 0x00000000 /* A[22:21] = b00 */
+#define SDRAM_BANK_SEL_1 0x00200000 /* A[22:21] = b01 */
+#define SDRAM_BANK_SEL_2 0x00400000 /* A[22:21] = b10 */
+#define SDRAM_BANK_SEL_3 0x00600000 /* A[22:21] = b11 */
+
+#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) || \
+ defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) || \
+ defined(CONFIG_EDB9315A)
+/*
+ * 2x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM
+ *
+ * CLK cycle time min:
+ * @ CAS latency = 3: 7.5ns
+ * @ CAS latency = 2: 10ns
+ * We're running at 100MHz (10ns cycle time) external bus speed (HCLK),
+ * so it's safe to use CAS latency = 2
+ *
+ * RAS-to-CAS delay min:
+ * 20ns
+ * At 10ns cycle time, we use RAS-to-CAS delay = 2
+ *
+ * EDB9307, EDB9312, EDB9315:
+ *
+ * 0x00000000 - 0x01ffffff
+ * 0x04000000 - 0x05ffffff
+ *
+ *
+ * EDB9307a, EDB9315a:
+ *
+ * 0xc0000000 - 0xc1ffffff
+ * 0xc4000000 - 0xc5ffffff
+ */
+
+#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT | \
+ SDRAM_DEVCFG_SROMLL | \
+ SDRAM_DEVCFG_CASLAT_2 | \
+ SDRAM_DEVCFG_RASTOCAS_2)
+
+/*
+ * 32 bit ext. bus
+ *
+ * A[23:10] is output as SYA[13:0]
+ * CAS latency: 2
+ * Burst type: sequential
+ * Burst length: 4
+ * SYA[13:0] = 0x0022
+ */
+#define SDRAM_MODE_REG_VAL 0x8800
+
+#define SDRAM_BANK_SEL_0 0x00000000 /* A[23:22] = b00 */
+#define SDRAM_BANK_SEL_1 0x00400000 /* A[23:22] = b01 */
+#define SDRAM_BANK_SEL_2 0x00800000 /* A[23:22] = b10 */
+#define SDRAM_BANK_SEL_3 0x00c00000 /* A[23:22] = b11 */
+#endif
diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h
new file mode 100644
index 0000000..4b00391
--- /dev/null
+++ b/include/configs/edb93xx.h
@@ -0,0 +1,270 @@
+/*
+ * U-boot - Configuration file for Cirrus Logic EDB93xx boards
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_MK_edb9301
+#define CONFIG_EDB9301
+#elif defined(CONFIG_MK_edb9302)
+#define CONFIG_EDB9302
+#elif defined(CONFIG_MK_edb9302a)
+#define CONFIG_EDB9302A
+#elif defined(CONFIG_MK_edb9307)
+#define CONFIG_EDB9307
+#elif defined(CONFIG_MK_edb9307a)
+#define CONFIG_EDB9307A
+#elif defined(CONFIG_MK_edb9312)
+#define CONFIG_EDB9312
+#elif defined(CONFIG_MK_edb9315)
+#define CONFIG_EDB9315
+#elif defined(CONFIG_MK_edb9315a)
+#define CONFIG_EDB9315A
+#else
+#error "no board defined"
+#endif
+
+/* Initial environment and monitor configuration options. */
+#define CONFIG_BOOTDELAY 2
+#define CONFIG_CMDLINE_TAG 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_BOOTARGS "root=/dev/nfs console=ttyAM0,115200 ip=dhcp"
+#define CONFIG_BOOTFILE "edb93xx.img"
+
+#define CONFIG_SYS_HUSH_PARSER 1
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#ifdef CONFIG_EDB9301
+#define CONFIG_EP9301
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9301
+#define CONFIG_SYS_PROMPT "EDB9301> "
+#define CONFIG_ENV_SECT_SIZE 0x00020000
+#elif defined(CONFIG_EDB9302)
+#define CONFIG_EP9302
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302
+#define CONFIG_SYS_PROMPT "EDB9302> "
+#define CONFIG_ENV_SECT_SIZE 0x00020000
+#elif defined(CONFIG_EDB9302A)
+#define CONFIG_EP9302
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302A
+#define CONFIG_SYS_PROMPT "EDB9302A> "
+#define CONFIG_ENV_SECT_SIZE 0x00020000
+#elif defined(CONFIG_EDB9307)
+#define CONFIG_EP9307
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307
+#define CONFIG_SYS_PROMPT "EDB9307> "
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#elif defined(CONFIG_EDB9307A)
+#define CONFIG_EP9307
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307A
+#define CONFIG_SYS_PROMPT "EDB9307A> "
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#elif defined(CONFIG_EDB9312)
+#define CONFIG_EP9312
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9312
+#define CONFIG_SYS_PROMPT "EDB9312> "
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#elif defined(CONFIG_EDB9315)
+#define CONFIG_EP9315
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315
+#define CONFIG_SYS_PROMPT "EDB9315> "
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#elif defined(CONFIG_EDB9315A)
+#define CONFIG_EP9315
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315A
+#define CONFIG_SYS_PROMPT "EDB9315A> "
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#else
+#error "no board defined"
+#endif
+
+/* High-level configuration options */
+#define CONFIG_ARM920T 1 /* This is an ARM920T core... */
+#define CONFIG_EP93XX 1 /* in a Cirrus Logic 93xx SoC */
+
+#define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456 clock */
+#define CONFIG_SYS_HZ 1000 /* decr freq: 1 ms ticks */
+#undef CONFIG_USE_IRQ /* Don't need IRQ/FIQ */
+
+/* Monitor configuration */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#undef CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+
+#define CONFIG_SYS_LONGHELP /* Enable "long" help in mon */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
+/* Print buffer size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+/* Boot argument buffer size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
+
+/* Serial port hardware configuration */
+#define CONFIG_PL010_SERIAL
+#define CONFIG_CONS_INDEX 0
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+#define CONFIG_SYS_SERIAL0 0x808C0000
+#define CONFIG_SYS_SERIAL1 0x808D0000
+#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
+ (void *)CONFIG_SYS_SERIAL1}
+
+/* Status LED */
+#define CONFIG_STATUS_LED 1 /* Status LED enabled */
+#define CONFIG_BOARD_SPECIFIC_LED 1
+#define STATUS_LED_GREEN 0
+#define STATUS_LED_RED 1
+/* Green */
+#define STATUS_LED_BIT STATUS_LED_GREEN
+#define STATUS_LED_STATE STATUS_LED_ON
+#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
+/* Red */
+#define STATUS_LED_BIT1 STATUS_LED_RED
+#define STATUS_LED_STATE1 STATUS_LED_OFF
+#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
+/* Optional value */
+#define STATUS_LED_BOOT STATUS_LED_BIT
+
+/* Network hardware configuration */
+#define CONFIG_DRIVER_EP93XX_MAC
+#define CONFIG_MII_SUPPRESS_PREAMBLE
+#define CONFIG_MII
+#define CONFIG_PHY_ADDR 1
+#define CONFIG_NET_MULTI
+#undef CONFIG_NETCONSOLE
+
+/* SDRAM configuration */
+#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302)
+/*
+ * EDB9301/2 has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
+ * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
+ * the SROMLL bit on the processor, resulting in this non-contiguous memory map.
+ */
+#define CONFIG_NR_DRAM_BANKS 4
+#define PHYS_SDRAM_1 0x00000000
+#define PHYS_SDRAM_SIZE_1 0x00800000
+#define PHYS_SDRAM_2 0x01000000
+#define PHYS_SDRAM_SIZE_2 0x00800000
+#define PHYS_SDRAM_3 0x04000000
+#define PHYS_SDRAM_SIZE_3 0x00800000
+#define PHYS_SDRAM_4 0x05000000
+#define PHYS_SDRAM_SIZE_4 0x00800000
+#define CONFIG_EDB93XX_SDCS3
+#define CONFIG_SYS_MEMTEST_START 0x00100000
+#define CONFIG_SYS_MEMTEST_END 0x007fffff
+
+#elif defined(CONFIG_EDB9302A)
+/*
+ * EDB9302a has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
+ * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
+ * the SROMLL bit on the processor, resulting in this non-contiguous memory map.
+ */
+#define CONFIG_NR_DRAM_BANKS 4
+#define PHYS_SDRAM_1 0xc0000000
+#define PHYS_SDRAM_SIZE_1 0x00800000
+#define PHYS_SDRAM_2 0xc1000000
+#define PHYS_SDRAM_SIZE_2 0x00800000
+#define PHYS_SDRAM_3 0xc4000000
+#define PHYS_SDRAM_SIZE_3 0x00800000
+#define PHYS_SDRAM_4 0xc5000000
+#define PHYS_SDRAM_SIZE_4 0x00800000
+#define CONFIG_EDB93XX_SDCS0
+#define CONFIG_SYS_MEMTEST_START 0xc0100000
+#define CONFIG_SYS_MEMTEST_END 0xc07fffff
+
+#elif defined(CONFIG_EDB9307) || defined CONFIG_EDB9312 || \
+ defined(CONFIG_EDB9315)
+/*
+ * The EDB9307, EDB9312, and EDB9315 have 2 banks of SDRAM consisting of
+ * 2x Samsung K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of
+ * 64 MB of SDRAM.
+ */
+#define CONFIG_NR_DRAM_BANKS 2
+#define PHYS_SDRAM_1 0x00000000
+#define PHYS_SDRAM_SIZE_1 0x02000000
+#define PHYS_SDRAM_2 0x04000000
+#define PHYS_SDRAM_SIZE_2 0x02000000
+#define CONFIG_EDB93XX_SDCS3
+#define CONFIG_SYS_MEMTEST_START 0x00100000
+#define CONFIG_SYS_MEMTEST_END 0x01e00000
+
+#elif defined(CONFIG_EDB9307A) || defined(CONFIG_EDB9315A)
+/*
+ * The EDB9307A and EDB9315A have 2 banks of SDRAM consisting of 2x Samsung
+ * K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of 64 MB of SDRAM.
+ */
+#define CONFIG_NR_DRAM_BANKS 2
+#define PHYS_SDRAM_1 0xc0000000
+#define PHYS_SDRAM_SIZE_1 0x02000000
+#define PHYS_SDRAM_2 0xc4000000
+#define PHYS_SDRAM_SIZE_2 0x02000000
+#define CONFIG_EDB93XX_SDCS0
+#define CONFIG_SYS_MEMTEST_START 0xc0100000
+#define CONFIG_SYS_MEMTEST_END 0xc1e00000
+#endif
+
+/* Default load address */
+#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x01000000)
+
+/* Must match kernel config */
+#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
+
+/* Run-time memory allocatons */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+#define CONFIG_STACKSIZE (128 * 1024)
+
+#if defined(CONFIG_USE_IRQ)
+#define CONFIG_STACKSIZE_IRQ (4 * 1024)
+#define CONFIG_STACKSIZE_FIQ (4 * 1024)
+#endif
+
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
+
+/* -----------------------------------------------------------------------------
+ * FLASH and environment organization
+ *
+ * The EDB9301 and EDB9302(a) have 1 bank of flash memory at 0x60000000
+ * consisting of 1x Intel TE28F128J3C-150 128 Mbit flash on a 16-bit data bus,
+ * for a total of 16 MB of CFI-compatible flash.
+ *
+ * The EDB9307(a), EDB9312, and EDB9315(a) have 1 bank of flash memory at
+ * 0x60000000 consisting of 2x Micron MT28F128J3-12 128 Mbit flash on a 32-bit
+ * data bus, for a total of 32 MB of CFI-compatible flash.
+ *
+ * EDB9301/02(a) EDB9307(a)/12/15(a)
+ * 0x60000000 - 0x0003FFFF u-boot u-boot
+ * 0x60040000 - 0x0005FFFF environment #1 environment #1
+ * 0x60060000 - 0x0007FFFF environment #2 environment #1 (continued)
+ * 0x60080000 - 0x0009FFFF unused environment #2
+ * 0x600A0000 - 0x000BFFFF unused environment #2 (continued)
+ * 0x600C0000 - 0x00FFFFFF unused unused
+ * 0x61000000 - 0x01FFFFFF not present unused
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 128
+
+#define PHYS_FLASH_1 0x60000000
+#define CONFIG_SYS_FLASH_BASE (PHYS_FLASH_1)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+
+#define CONFIG_ENV_OVERWRITE /* Vendor params unprotected */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR 0x60040000
+
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+#endif /* !defined (__CONFIG_H) */
--
1.6.5
^ permalink raw reply related [flat|nested] 12+ messages in thread
end of thread, other threads:[~2010-02-01 20:29 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
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[not found] <cover.1264351928.git.matthias@kaehlcke.net>
2010-01-24 16:56 ` [U-Boot] [PATCH 1/3] ARM: Add support for EP93xx SoCs Matthias Kaehlcke
2010-01-31 18:53 ` Tom
2010-02-01 7:24 ` Matthias Kaehlcke
2010-01-24 16:56 ` [U-Boot] [PATCH 2/3] Add EP93xx ethernet driver Matthias Kaehlcke
2010-01-25 4:09 ` Ben Warren
2010-01-24 16:56 ` [U-Boot] [PATCH 3/3] Add support for EDB93xx boards Matthias Kaehlcke
2010-01-31 19:00 ` Tom
[not found] <cover.1265053904.git.matthias@kaehlcke.net>
2010-02-01 20:29 ` Matthias Kaehlcke
[not found] <cover.1264955406.git.matthias@kaehlcke.net>
2010-01-31 16:39 ` Matthias Kaehlcke
[not found] <cover.1263903884.git.matthias@kaehlcke.net>
2010-01-19 19:16 ` Matthias Kaehlcke
2010-01-19 21:58 ` Wolfgang Denk
2009-12-23 19:26 [U-Boot] [PATCH 3/3] Add support for EDB93XX boards Matthias Kaehlcke
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