From: Alessandro Rubini <rubini-list@gnudd.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH RFC 0/2] dcache on ARM
Date: Tue, 26 Jan 2010 22:50:10 +0100 [thread overview]
Message-ID: <20100126215010.GA26452@morgana.gnudd.com> (raw)
In-Reply-To: <4B5F22A8.1000804@ge.com>
Hello Nick.
> On TI DA830, the 1.0 & 1.1 revision of the silicon have a data caching
> bug. You can use data caching, but only in write thru' mode.
I see. So instead of both C and B you just need to C bit set in the
page table, and no B.
I propose to allow an extra option for write-back, leaving
write-through as the default. This matches the blackfin, which has
CONFIG_DCACHE_WB as an option, and leaves a safer default for those
who won't explicitly require WB policy.
Could you please confirm my patch works on that board after changing
the magic bits from 0x1e to 0x1a ? (I'll use symbolic constants
anyways in V2, this was just a quick RFC to see if the approach is
acceptable).
/alessandro
next prev parent reply other threads:[~2010-01-26 21:50 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-01-26 16:16 [U-Boot] [PATCH RFC 0/2] dcache on ARM Alessandro Rubini
2010-01-26 17:13 ` Nick Thompson
2010-01-26 21:50 ` Alessandro Rubini [this message]
2010-01-26 17:21 ` Armando VISCONTI
2010-01-26 17:36 ` Alessandro Rubini
2010-01-26 17:59 ` Armando VISCONTI
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