[U-Boot] [PATCH] ppc4xx: Corrected EBC register bit definitions

[U-Boot] [PATCH] ppc4xx: Corrected EBC register bit definitions

[Eugene O'Brien]

Corrected the bit field positions of the external master priority low
and the external master priority high values in the EBC configuration
register.

Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
---
 include/asm-ppc/ppc4xx-ebc.h |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/asm-ppc/ppc4xx-ebc.h b/include/asm-ppc/ppc4xx-ebc.h
index 9680f70..697a916 100644
--- a/include/asm-ppc/ppc4xx-ebc.h
+++ b/include/asm-ppc/ppc4xx-ebc.h
@@ -143,10 +143,10 @@
 #define EBC_CFG_EBTC_MASK	PPC_REG_VAL(0, 0x1)
 #define EBC_CFG_EBTC_HI		PPC_REG_VAL(0, 0x0)
 #define EBC_CFG_EBTC_DRIVEN	PPC_REG_VAL(0, 0x1)
-#define EBC_CFG_EMPH_MASK	PPC_REG_VAL(6, 0x3)
-#define EBC_CFG_EMPH_ENCODE(n)	PPC_REG_VAL(6, (static_cast(u32, n)) &
0x3)
-#define EBC_CFG_EMPL_MASK	PPC_REG_VAL(8, 0x3)
-#define EBC_CFG_EMPL_ENCODE(n)	PPC_REG_VAL(8, (static_cast(u32, n)) &
0x3)
+#define EBC_CFG_EMPL_MASK	PPC_REG_VAL(6, 0x3)
+#define EBC_CFG_EMPL_ENCODE(n)	PPC_REG_VAL(6, (static_cast(u32, n)) &
0x3)
+#define EBC_CFG_EMPH_MASK	PPC_REG_VAL(8, 0x3)
+#define EBC_CFG_EMPH_ENCODE(n)	PPC_REG_VAL(8, (static_cast(u32, n)) &
0x3)
 #define EBC_CFG_CSTC_MASK	PPC_REG_VAL(9, 0x1)
 #define EBC_CFG_CSTC_HI		PPC_REG_VAL(9, 0x0)
 #define EBC_CFG_CSTC_DRIVEN	PPC_REG_VAL(9, 0x1)
-- 
1.7.0.rc1.10.gb8bb

[U-Boot] [PATCH] ppc4xx: Corrected EBC register bit definitions

[Wolfgang Denk]

Dear "Eugene O'Brien",

In message <8B3930FEA8618C44B48EB06B5D33A06E01CCE3DF@satmail.Advantech.ca> you wrote:
> 
> Corrected the bit field positions of the external master priority low
> and the external master priority high values in the EBC configuration
> register.
> 
> Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
> ---
>  include/asm-ppc/ppc4xx-ebc.h |    8 ++++----
>  1 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/include/asm-ppc/ppc4xx-ebc.h b/include/asm-ppc/ppc4xx-ebc.h
> index 9680f70..697a916 100644
> --- a/include/asm-ppc/ppc4xx-ebc.h
> +++ b/include/asm-ppc/ppc4xx-ebc.h
> @@ -143,10 +143,10 @@
>  #define EBC_CFG_EBTC_MASK	PPC_REG_VAL(0, 0x1)
>  #define EBC_CFG_EBTC_HI		PPC_REG_VAL(0, 0x0)
>  #define EBC_CFG_EBTC_DRIVEN	PPC_REG_VAL(0, 0x1)
> -#define EBC_CFG_EMPH_MASK	PPC_REG_VAL(6, 0x3)
> -#define EBC_CFG_EMPH_ENCODE(n)	PPC_REG_VAL(6, (static_cast(u32, n)) &
> 0x3)

Your patch is line-wrapped.

Please use git-send-email to send patches, or fix your mailer
configuration.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
All I ask is a chance to prove that money can't make me happy.

[U-Boot] [PATCH] ppc4xx: Corrected EBC register bit definitions

[Stefan Roese]

Eugene,

On Tuesday 23 February 2010 22:19:04 Eugene O'Brien wrote:
> Corrected the bit field positions of the external master priority low
> and the external master priority high values in the EBC configuration
> register.

In addition to Wolfgangs comment (patch is line wrapped): I just checked the 
440EP and the 440EPx users manual, and it seems that the original bit masks 
are correct. Which PPC4xx variant are you using? Please double check again if 
you your patch is correct.
 
Thanks.

Cheers,
Stefan

--
DENX Software Engineering GmbH,      MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de

[U-Boot] [PATCH] ppc4xx: Corrected EBC register bit definitions

[Eugene O'Brien]

Hello Stefan,

> In addition to Wolfgangs comment (patch is line wrapped): I just
checked the
> 440EP and the 440EPx users manual, and it seems that the original bit
masks
> are correct. Which PPC4xx variant are you using? Please double check
again if
> you your patch is correct.
> 

I am working on another platform based on the PPC405GPr. You are correct
in your observation and my patch is incorrect. The original bit masks
are correct for the PPC440EP and PPC440EPx but **not** for the PPC405GPr
so a correction is required. 

According to the AMCC documentation, the EMPL, EMPH bit positions are as
you defined them for the PPC440 processors and they are as I define them
for the PPC405 processors (in the group of processors defined as
CONFIG_EBC_PPC4xx_IBM_VER1). The PPC405EP is an exception since it does
not seem to allow external bus mastering and these bits are reserved.
Therefore a proper patch needs to set the bit position of the EMPL and
EMPH fields differently with the CONFIG_EBC_PPC4xx_IBM_VER1 group
accordingly. I can attempt a patch for that if you like.

My apologies for the line wrapping mistake (I believe my email client is
not line wrapping but it got line wrapped somewhere else... possibly in
the Microsoft exchange server).

Regards,
Eugene

[U-Boot] [PATCH] ppc4xx: Corrected EBC register bit definitions

[Stefan Roese]

Hi Eugene,

On Wednesday 24 February 2010 16:12:48 Eugene O'Brien wrote:
> I am working on another platform based on the PPC405GPr. You are correct
> in your observation and my patch is incorrect. The original bit masks
> are correct for the PPC440EP and PPC440EPx but **not** for the PPC405GPr
> so a correction is required.

I see.
 
> According to the AMCC documentation, the EMPL, EMPH bit positions are as
> you defined them for the PPC440 processors and they are as I define them
> for the PPC405 processors (in the group of processors defined as
> CONFIG_EBC_PPC4xx_IBM_VER1). The PPC405EP is an exception since it does
> not seem to allow external bus mastering and these bits are reserved.
> Therefore a proper patch needs to set the bit position of the EMPL and
> EMPH fields differently with the CONFIG_EBC_PPC4xx_IBM_VER1 group
> accordingly. I can attempt a patch for that if you like.

Yes, please do so. Thanks.

Cheers,
Stefan

--
DENX Software Engineering GmbH,      MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de

[U-Boot] [PATCH] ppc4xx: Corrected EBC register bit definitions

[Eugene O'Brien]

Corrected the bit field positions of the external master priority low
and the external master priority high values in the EBC configuration
register. These bit field positions differ between PPC405 and PPC440
processors

Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
---
 include/asm-ppc/ppc4xx-ebc.h |   24 ++++++++++++++++++------
 1 files changed, 18 insertions(+), 6 deletions(-)

diff --git a/include/asm-ppc/ppc4xx-ebc.h b/include/asm-ppc/ppc4xx-ebc.h
index 9680f70..9c17e46 100644
--- a/include/asm-ppc/ppc4xx-ebc.h
+++ b/include/asm-ppc/ppc4xx-ebc.h
@@ -25,14 +25,24 @@
 #define _PPC4xx_EBC_H_
 
 /*
- * Currently there are two register layout versions for the
- * IBM EBC core used on 4xx PPC's:
+ * Currently there are two register layout versions for the IBM EBC core
+ * used on 4xx PPC's. The following grouping lists the first layout.
+ * Within this group there is a slight variation concerning the bit field
+ * position of the EMPL and EMPH fields:
  */
 #if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \
     defined(CONFIG_405EP) || \
     defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define CONFIG_EBC_PPC4xx_IBM_VER1
+#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \
+    defined(CONFIG_405EP)
+#define EBC_CFG_EMPH_POS	8
+#define EBC_CFG_EMPL_POS	6
+#else
+#define EBC_CFG_EMPH_POS	6
+#define EBC_CFG_EMPL_POS	8
+#endif
 #endif
 
 /*
@@ -143,10 +153,12 @@
 #define EBC_CFG_EBTC_MASK	PPC_REG_VAL(0, 0x1)
 #define EBC_CFG_EBTC_HI		PPC_REG_VAL(0, 0x0)
 #define EBC_CFG_EBTC_DRIVEN	PPC_REG_VAL(0, 0x1)
-#define EBC_CFG_EMPH_MASK	PPC_REG_VAL(6, 0x3)
-#define EBC_CFG_EMPH_ENCODE(n)	PPC_REG_VAL(6, (static_cast(u32, n)) & 0x3)
-#define EBC_CFG_EMPL_MASK	PPC_REG_VAL(8, 0x3)
-#define EBC_CFG_EMPL_ENCODE(n)	PPC_REG_VAL(8, (static_cast(u32, n)) & 0x3)
+#define EBC_CFG_EMPH_MASK	PPC_REG_VAL(EBC_CFG_EMPH_POS, 0x3)
+#define EBC_CFG_EMPH_ENCODE(n)	PPC_REG_VAL(EBC_CFG_EMPH_POS, \
+						(static_cast(u32, n)) & 0x3)
+#define EBC_CFG_EMPL_MASK	PPC_REG_VAL(EBC_CFG_EMPL_POS, 0x3)
+#define EBC_CFG_EMPL_ENCODE(n)	PPC_REG_VAL(EBC_CFG_EMPH_POS, \
+						(static_cast(u32, n)) & 0x3)
 #define EBC_CFG_CSTC_MASK	PPC_REG_VAL(9, 0x1)
 #define EBC_CFG_CSTC_HI		PPC_REG_VAL(9, 0x0)
 #define EBC_CFG_CSTC_DRIVEN	PPC_REG_VAL(9, 0x1)
-- 
1.7.0.rc1.10.gb8bb

[U-Boot] [PATCH] ppc4xx: Corrected EBC register bit definitions

[Stefan Roese]

On Wednesday 24 February 2010 20:10:24 Eugene O'Brien wrote:
> Corrected the bit field positions of the external master priority low
> and the external master priority high values in the EBC configuration
> register. These bit field positions differ between PPC405 and PPC440
> processors

Applied to u-boot-ppc4xx/master. Thanks.
 
Cheers,
Stefan

--
DENX Software Engineering GmbH,      MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de