From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefan Roese Date: Wed, 24 Feb 2010 17:15:19 +0100 Subject: [U-Boot] [PATCH] ppc4xx: Corrected EBC register bit definitions In-Reply-To: <8B3930FEA8618C44B48EB06B5D33A06E01CCE3E2@satmail.Advantech.ca> References: <8B3930FEA8618C44B48EB06B5D33A06E01CCE3DF@satmail.Advantech.ca> <201002240830.36465.sr@denx.de> <8B3930FEA8618C44B48EB06B5D33A06E01CCE3E2@satmail.Advantech.ca> Message-ID: <201002241715.19869.sr@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Eugene, On Wednesday 24 February 2010 16:12:48 Eugene O'Brien wrote: > I am working on another platform based on the PPC405GPr. You are correct > in your observation and my patch is incorrect. The original bit masks > are correct for the PPC440EP and PPC440EPx but **not** for the PPC405GPr > so a correction is required. I see. > According to the AMCC documentation, the EMPL, EMPH bit positions are as > you defined them for the PPC440 processors and they are as I define them > for the PPC405 processors (in the group of processors defined as > CONFIG_EBC_PPC4xx_IBM_VER1). The PPC405EP is an exception since it does > not seem to allow external bus mastering and these bits are reserved. > Therefore a proper patch needs to set the bit position of the EMPL and > EMPH fields differently with the CONFIG_EBC_PPC4xx_IBM_VER1 group > accordingly. I can attempt a patch for that if you like. Yes, please do so. Thanks. Cheers, Stefan -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de