[U-Boot] [PATCH] Add support for Indefia Nimbus Cloud Board

[Stefan Roese <sr@denx.de>]

Hi Wolfgang, Hi Semih,

On Tuesday 23 March 2010 21:01:12 Wolfgang Denk wrote:
> > It's not possible to simply disable caching for 0x0 region. It can be
> > achieved using paging, but it's more complicated.
> 
> I have three specific questions:
> 
> * Is it technically possible to set up the AVR32 memory controller
>   such that the memory region at 0x0 is mapped uncached?
> 
>   I am asking if it is possible to configure a system such that cahces
>   are completely turned off.
> 
> * Assuming this is possible, then is there a way to reprogram (in the
>   running system) the AVR32 memory controller from one mode (cached)
>   to the other one (uncached) ?
> 
> * Does the AVR32 memory controller support anything like a
>   "write-through" cache mode?

I had a quick glance at the AVR32 architecture manual. And it really seems 
that 2GB starting at address 0 are *always* cached. What I couldn't find out 
quickly is, if it is possible to turn on write-though support for this address 
range. Perhaps an AVR32 expert could enlighten us here?
 
> > If we go with Stefan's option a, then we need to put some #ifdefs or
> > function calls in the flash code to enable/disable cache, right?
> 
> Function calls, yes. But ideally we can use write-through, and I
> expect that we eventually might kept this mode always switched on.

Option a) is using write-though, so the cache should always stay on in this 
mode (used in combination with cache flush and invalidate calls). Option b) is 
the alternative with temporarily disabling the caches for the erase/write 
operations. But since disabling cache isn't possible on AVR32, this isn't an 
option here.

This leads us back to these questions:

- Is it possible to turn on write-though support for the memory area
  starting at 0?

- Is it possible to flush and/or invalidate address ranges in this area?
 
Cheers,
Stefan

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