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From: Stefan Roese <sr@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] Nor Flash SST39VF6402B cfi compliant support
Date: Mon, 19 Jul 2010 11:23:21 +0200	[thread overview]
Message-ID: <201007191123.21356.sr@denx.de> (raw)
In-Reply-To: <201007191104.35328.fabio.giovagnini@aurion-tech.com>

On Monday 19 July 2010 11:04:34 Fabio Giovagnini wrote:
> I Stefan. I did teh following upgrade of the fileyou suggestied to me.
> 
> #define SST39VF6402B	0x236c
> ...
> #ifdef CONFIG_SYS_FLASH_LEGACY_4Mx16
> 	{
> 		.mfr_id		= (u16)SST_MANUFACT,
> 		.dev_id		= SST39VF6402B,
> 		.name		= "SST 39VF6402B",
> 		.uaddr		= {
> 			[1] = MTD_UADDR_0x0555_0x02AA /* x16 */
> 		},
> 		.DevSize	= SIZE_4MiB,
> 		.CmdSet		= CFI_CMDSET_AMD_LEGACY,
> 		.NumEraseRegions= 1,
> 		.regions	= {
> 			ERASEINFO(0x10000,128),
> 		}
> 	},
> #endif
> 
> The flash works, but not properly.

What's exactly not working?

> My conention is A1 mcp Bus cocceted to A0 of flash chip to have 16 bit
> width for data bus. The flash datasheet tells the flash os organized in
> 128 32kword of esare sectors. So I think my setting is not correct. Is it?

Could be. IIRC, then the SST parts have 2 different erase regions, the 
"normal" ones and the smaller ones (4k???). Not sure which one is used by this 
command set. I suggest you investigate here further.
 
Cheers,
Stefan

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  reply	other threads:[~2010-07-19  9:23 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-07-15  9:55 [U-Boot] Nor Flash SST39VF6402B cfi compliant support Fabio Giovagnini
2010-07-19  7:52 ` Stefan Roese
2010-07-19  9:04   ` Fabio Giovagnini
2010-07-19  9:23     ` Stefan Roese [this message]
     [not found]       ` <201007191127.50865.fabio.giovagnini@aurion-tech.com>
2010-07-19  9:33         ` Stefan Roese
2010-07-19 10:26           ` Fabio Giovagnini
2010-07-19 13:57             ` Fabio Giovagnini
2010-07-19 14:19               ` Stefan Roese
2010-07-19 15:13                 ` Fabio Giovagnini

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