From mboxrd@z Thu Jan  1 00:00:00 1970
From: Wolfgang Denk <wd@denx.de>
Date: Sat, 14 Aug 2010 23:49:10 +0200
Subject: [U-Boot] Struct SoC access
In-Reply-To: <4C6700E5.2070009@emk-elektronik.de>
References: <4C665CB9.2040406@emk-elektronik.de>
	<20100814143009.A18461606A5@gemini.denx.de>
	<4C66CCCF.9080303@emk-elektronik.de>
	<20100814184641.981AC1606A5@gemini.denx.de>
	<4C66EECA.5020509@emk-elektronik.de>
	<20100814194117.982C71606A5@gemini.denx.de>
	<4C66F54D.2060701@emk-elektronik.de>
	<4C6700E5.2070009@emk-elektronik.de>
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To: u-boot@lists.denx.de

Dear Reinhard Meyer,

In message <4C6700E5.2070009@emk-elektronik.de> you wrote:
> > Would the toolchain "gulp" when one defines the whole 4 GB that way?
> 
> In fact, a rather novel approach (just theorizing here):
> 
> #define SRAM_BASE offsetof(soc.sram)
> #define SRAM_SIZE sizeof(soc.sram)
> 
> dbu_t *dbu = (dbu_t *)offsetof(soc.dbu);
> 
> without ever assigning soc the address 0...

Urgh... that's a log of pretty heavy assumptions, and not exactly
readable / understandable code either.  I gues your're not targeting
the next IOCCC?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
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