[U-Boot] [PATCH 1/7] fix dma for 36bit addressing

[U-Boot] [PATCH 1/7] fix dma for 36bit addressing

[York Sun]

Use more bits to support 36-bit addressing

Signed-off-by: York Sun <yorksun@freescale.com>
---
 drivers/dma/fsl_dma.c |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c
index df33e7a..09c18c1 100644
--- a/drivers/dma/fsl_dma.c
+++ b/drivers/dma/fsl_dma.c
@@ -114,8 +114,12 @@ int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) {
 	while (count) {
 		xfer_size = MIN(FSL_DMA_MAX_SIZE, count);
 
-		out_dma32(&dma->dar, (uint) dest);
-		out_dma32(&dma->sar, (uint) src);
+		out_dma32(&dma->dar, (u32) (dest & 0xFFFFFFFF));
+		out_dma32(&dma->sar, (u32) (src & 0xFFFFFFFF));
+		out_dma32(&dma->satr,
+			in_dma32(&dma->satr) | (u32)((u64)src >> 32));
+		out_dma32(&dma->datr,
+			in_dma32(&dma->datr) | (u32)((u64)dest >> 32));
 		out_dma32(&dma->bcr, xfer_size);
 		dma_sync();
 
-- 
1.7.0.4

[U-Boot] [PATCH 2/7] Expand POST memory test to support arch-depended implementation.

[York Sun]

Add progress indicator for slow test. It is useful when the testing
takes too longer to finish. The indicator is reused from flash
programming.

Hwconfig is used to turn on slow test when not enabled by flag.

Signed-off-by: York Sun <yorksun@freescale.com>
---
 post/drivers/memory.c |  211 +++++++++++++++++++++++++++++++++++++++---------
 1 files changed, 171 insertions(+), 40 deletions(-)

diff --git a/post/drivers/memory.c b/post/drivers/memory.c
index 0062360..4020fc2 100644
--- a/post/drivers/memory.c
+++ b/post/drivers/memory.c
@@ -22,7 +22,7 @@
  */
 
 #include <common.h>
-
+#include <hwconfig.h>
 /* Memory test
  *
  * General observations:
@@ -172,6 +172,21 @@ DECLARE_GLOBAL_DATA_PTR;
 #warning "Injecting address line errors for testing purposes"
 #endif
 
+#define TOTAL_PROGRESS_DOTS 45
+#define TOTAL_PROGRESS_NUMBERS 9
+#define PROGRESS_DOTS_PER_NUMBER (TOTAL_PROGRESS_DOTS/TOTAL_PROGRESS_NUMBERS)
+#define TEST_SHOW_PROGRESS(scale, dots, digit, dots_sub) \
+{ \
+	dots -= (dots_sub); \
+	if ((scale > 0) && (dots <= 0)) { \
+		if ((digit % PROGRESS_DOTS_PER_NUMBER) == 0) \
+			printf("%d", digit / PROGRESS_DOTS_PER_NUMBER); \
+		else \
+			putc('.'); \
+		digit--; \
+		dots += (scale); \
+	} \
+}
 
 /*
  * This function performs a double word move from the data at
@@ -291,21 +306,34 @@ static int memory_post_addrline(ulong *testaddr, ulong *base, ulong size)
 	return ret;
 }
 
-static int memory_post_test1 (unsigned long start,
+static int memory_post_test1(unsigned long start,
 			      unsigned long size,
-			      unsigned long val)
+			      unsigned long val,
+			      int fast)
 {
 	unsigned long i;
 	ulong *mem = (ulong *) start;
 	ulong readback;
 	int ret = 0;
+	int digit, dots;
+	int scale;
+
+	scale = (int)(((size >> 22) + TOTAL_PROGRESS_DOTS - 1) /
+		TOTAL_PROGRESS_DOTS);
+	digit = TOTAL_PROGRESS_DOTS;
+	dots  = 0;
 
 	for (i = 0; i < size / sizeof (ulong); i++) {
 		mem[i] = val;
 		if (i % 1024 == 0)
 			WATCHDOG_RESET ();
+		if (!fast && (i & 0xFFFFF) == 0)
+			TEST_SHOW_PROGRESS(scale, dots, digit, 1);
 	}
-
+	if (!fast)
+		printf("Filled with 0x%lx\n", val);
+	digit = TOTAL_PROGRESS_DOTS;
+	dots  = 0;
 	for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
 		readback = mem[i];
 		if (readback != val) {
@@ -318,24 +346,45 @@ static int memory_post_test1 (unsigned long start,
 		}
 		if (i % 1024 == 0)
 			WATCHDOG_RESET ();
+		if (!fast && (i & 0xFFFFF) == 0)
+			TEST_SHOW_PROGRESS(scale, dots, digit, 1);
+	}
+	if (!fast) {
+		if (ret == 0)
+			puts("Verified OK.\n\n");
+		else
+			puts("\nFailed!\n\n");
 	}
-
 	return ret;
 }
 
-static int memory_post_test2 (unsigned long start, unsigned long size)
+static int memory_post_test2(unsigned long start, unsigned long size, int fast)
 {
 	unsigned long i;
 	ulong *mem = (ulong *) start;
 	ulong readback;
 	int ret = 0;
+	int digit, dots;
+	int scale;
+
+	scale = (int)(((size >> 22) + TOTAL_PROGRESS_DOTS - 1) /
+		TOTAL_PROGRESS_DOTS);
+	digit = TOTAL_PROGRESS_DOTS;
+	dots  = 0;
 
 	for (i = 0; i < size / sizeof (ulong); i++) {
 		mem[i] = 1 << (i % 32);
 		if (i % 1024 == 0)
 			WATCHDOG_RESET ();
+		if (!fast && (i & 0xFFFFF) == 0)
+			TEST_SHOW_PROGRESS(scale, dots, digit, 1);
 	}
 
+	if (!fast)
+		printf("Filled with bit-flip pattern\n");
+	digit = TOTAL_PROGRESS_DOTS;
+	dots  = 0;
+
 	for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
 		readback = mem[i];
 		if (readback != (1 << (i % 32))) {
@@ -348,24 +397,45 @@ static int memory_post_test2 (unsigned long start, unsigned long size)
 		}
 		if (i % 1024 == 0)
 			WATCHDOG_RESET ();
+		if (!fast && (i & 0xFFFFF) == 0)
+			TEST_SHOW_PROGRESS(scale, dots, digit, 1);
+	}
+	if (!fast) {
+		if (ret == 0)
+			puts("Verified OK.\n\n");
+		else
+			puts("\nFailed!\n\n");
 	}
-
 	return ret;
 }
 
-static int memory_post_test3 (unsigned long start, unsigned long size)
+static int memory_post_test3(unsigned long start, unsigned long size, int fast)
 {
 	unsigned long i;
 	ulong *mem = (ulong *) start;
 	ulong readback;
 	int ret = 0;
+	int digit, dots;
+	int scale;
+
+	scale = (int)(((size >> 22) + TOTAL_PROGRESS_DOTS - 1) /
+		TOTAL_PROGRESS_DOTS);
+	digit = TOTAL_PROGRESS_DOTS;
+	dots  = 0;
 
 	for (i = 0; i < size / sizeof (ulong); i++) {
 		mem[i] = i;
 		if (i % 1024 == 0)
 			WATCHDOG_RESET ();
+		if (!fast && (i & 0xFFFFF) == 0)
+			TEST_SHOW_PROGRESS(scale, dots, digit, 1);
 	}
 
+	if (!fast)
+		printf("Filled with address pattern\n");
+	digit = TOTAL_PROGRESS_DOTS;
+	dots  = 0;
+
 	for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
 		readback = mem[i];
 		if (readback != i) {
@@ -378,24 +448,45 @@ static int memory_post_test3 (unsigned long start, unsigned long size)
 		}
 		if (i % 1024 == 0)
 			WATCHDOG_RESET ();
+		if (!fast && (i & 0xFFFFF) == 0)
+			TEST_SHOW_PROGRESS(scale, dots, digit, 1);
+	}
+	if (!fast) {
+		if (ret == 0)
+			puts("Verified OK.\n\n");
+		else
+			puts("\nFailed!\n\n");
 	}
-
 	return ret;
 }
 
-static int memory_post_test4 (unsigned long start, unsigned long size)
+static int memory_post_test4(unsigned long start, unsigned long size, int fast)
 {
 	unsigned long i;
 	ulong *mem = (ulong *) start;
 	ulong readback;
 	int ret = 0;
+	int digit, dots;
+	int scale;
+
+	scale = (int)(((size >> 22) + TOTAL_PROGRESS_DOTS - 1) /
+		TOTAL_PROGRESS_DOTS);
+	digit = TOTAL_PROGRESS_DOTS;
+	dots  = 0;
 
 	for (i = 0; i < size / sizeof (ulong); i++) {
 		mem[i] = ~i;
 		if (i % 1024 == 0)
 			WATCHDOG_RESET ();
+		if (!fast && (i & 0xFFFFF) == 0)
+			TEST_SHOW_PROGRESS(scale, dots, digit, 1);
 	}
 
+	if (!fast)
+		printf("Filled with address complement pattern\n");
+	digit = TOTAL_PROGRESS_DOTS;
+	dots  = 0;
+
 	for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
 		readback = mem[i];
 		if (readback != ~i) {
@@ -408,75 +499,115 @@ static int memory_post_test4 (unsigned long start, unsigned long size)
 		}
 		if (i % 1024 == 0)
 			WATCHDOG_RESET ();
+		if (!fast && (i & 0xFFFFF) == 0)
+			TEST_SHOW_PROGRESS(scale, dots, digit, 1);
+	}
+	if (!fast) {
+		if (ret == 0)
+			puts("Verified OK.\n\n");
+		else
+			puts("\nFailed!\n\n");
 	}
-
 	return ret;
 }
 
-static int memory_post_tests (unsigned long start, unsigned long size)
+static int memory_post_tests(unsigned long start, unsigned long size, int fast)
 {
 	int ret = 0;
 
 	if (ret == 0)
-		ret = memory_post_dataline ((unsigned long long *)start);
+		ret = memory_post_dataline((unsigned long long *)start);
 	WATCHDOG_RESET ();
 	if (ret == 0)
-		ret = memory_post_addrline ((ulong *)start, (ulong *)start, size);
+		ret = memory_post_addrline((ulong *)start, (ulong *)start, size);
 	WATCHDOG_RESET ();
 	if (ret == 0)
-		ret = memory_post_addrline ((ulong *)(start + size - 8),
+		ret = memory_post_addrline((ulong *)(start + size - 8),
 					    (ulong *)start, size);
 	WATCHDOG_RESET ();
 	if (ret == 0)
-		ret = memory_post_test1 (start, size, 0x00000000);
+		ret = memory_post_test1(start, size, 0x00000000, fast);
 	WATCHDOG_RESET ();
 	if (ret == 0)
-		ret = memory_post_test1 (start, size, 0xffffffff);
+		ret = memory_post_test1(start, size, 0xffffffff, fast);
 	WATCHDOG_RESET ();
 	if (ret == 0)
-		ret = memory_post_test1 (start, size, 0x55555555);
+		ret = memory_post_test1(start, size, 0x55555555, fast);
 	WATCHDOG_RESET ();
 	if (ret == 0)
-		ret = memory_post_test1 (start, size, 0xaaaaaaaa);
+		ret = memory_post_test1(start, size, 0xaaaaaaaa, fast);
 	WATCHDOG_RESET ();
 	if (ret == 0)
-		ret = memory_post_test2 (start, size);
+		ret = memory_post_test2(start, size, fast);
 	WATCHDOG_RESET ();
 	if (ret == 0)
-		ret = memory_post_test3 (start, size);
+		ret = memory_post_test3(start, size, fast);
 	WATCHDOG_RESET ();
 	if (ret == 0)
-		ret = memory_post_test4 (start, size);
+		ret = memory_post_test4(start, size, fast);
 	WATCHDOG_RESET ();
 
 	return ret;
 }
 
-int memory_post_test (int flags)
+__attribute__((weak))
+int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
 {
-	int ret = 0;
 	bd_t *bd = gd->bd;
-	unsigned long memsize = (bd->bi_memsize >= 256 << 20 ?
-				 256 << 20 : bd->bi_memsize) - (1 << 20);
-
+	*vstart = CONFIG_SYS_SDRAM_BASE;
+	*size = (bd->bi_memsize >= 256 << 20 ?
+			256 << 20 : bd->bi_memsize) - (1 << 20);
 	/* Limit area to be tested with the board info struct */
-	if (CONFIG_SYS_SDRAM_BASE + memsize > (ulong)bd)
-		memsize = (ulong)bd - CONFIG_SYS_SDRAM_BASE;
+	if ((*vstart) + (*size) > (ulong)bd)
+		*size = (ulong)bd - CONFIG_SYS_SDRAM_BASE;
+	return 0;
+}
+
+__attribute__((weak))
+int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+	return 1;
+}
 
-	if (flags & POST_SLOWTEST) {
-		ret = memory_post_tests (CONFIG_SYS_SDRAM_BASE, memsize);
-	} else {			/* POST_NORMAL */
+__attribute__((weak))
+int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+	return 0;
+}
 
-		unsigned long i;
+__attribute__((weak))
+void arch_memory_failure_handle(void)
+{
+	return;
+}
 
-		for (i = 0; i < (memsize >> 20) && ret == 0; i++) {
-			if (ret == 0)
-				ret = memory_post_tests (i << 20, 0x800);
-			if (ret == 0)
-				ret = memory_post_tests ((i << 20) + 0xff800, 0x800);
+int memory_post_test(int flags)
+{
+	int fast, ret = 0;
+	phys_addr_t phys_offset = 0;
+	u32 memsize, vstart;
+	if (hwconfig("memtest"))
+		fast = !hwconfig_arg_cmp("memtest", "slow");
+	else
+		fast = 1;
+
+	arch_memory_test_prepare(&vstart, &memsize, &phys_offset);
+	do {
+		if ((!fast) || (flags & POST_SLOWTEST)) {
+			ret = memory_post_tests(vstart, memsize, fast);
+		} else {			/* POST_NORMAL */
+			unsigned long i;
+			for (i = 0; i < (memsize >> 20) && ret == 0; i++) {
+				if (ret == 0)
+					ret = memory_post_tests(i << 20, 0x800, fast);
+				if (ret == 0)
+					ret = memory_post_tests((i << 20) + 0xff800, 0x800, fast);
+			}
 		}
-	}
-
+	} while (!ret && !arch_memory_test_advance(&vstart, &memsize, &phys_offset));
+	arch_memory_test_cleanup(&vstart, &memsize, &phys_offset);
+	if (ret)
+		arch_memory_failure_handle();
 	return ret;
 }
 
-- 
1.7.0.4

[U-Boot] [PATCH 2/7] Expand POST memory test to support arch-depended implementation.

[Wolfgang Denk]

Dear York Sun,

In message <1282944356-4020-2-git-send-email-yorksun@freescale.com> you wrote:
> Add progress indicator for slow test. It is useful when the testing
> takes too longer to finish. The indicator is reused from flash
> programming.
> 
> Hwconfig is used to turn on slow test when not enabled by flag.

NAK.

POST is supposed to be an automatic, unmonitored functionality.
Results are suposed to be reported through a mechanism compatible to
Linux' syslog system.

There is no place for progress indicators here.


Please note that your subject "support arch-depended implementation"
and the commit message "Add progress indicator" are seriously out of
sync as well.  Another reason for a NAK.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Voodoo Programming: Things programmers do that  they  know  shouldn't
work  but they try anyway, and which sometimes actually work, such as
recompiling everything.                             - Karl Lehenbauer

[U-Boot] [PATCH 2/7] Expand POST memory test to support arch-depended implementation.

[Scott Wood]

On Sun, 29 Aug 2010 10:56:47 +0200
Wolfgang Denk <wd@denx.de> wrote:

> Dear York Sun,
> 
> In message <1282944356-4020-2-git-send-email-yorksun@freescale.com> you wrote:
> > Add progress indicator for slow test. It is useful when the testing
> > takes too longer to finish. The indicator is reused from flash
> > programming.
> > 
> > Hwconfig is used to turn on slow test when not enabled by flag.
> 
> NAK.
> 
> POST is supposed to be an automatic, unmonitored functionality.
> Results are suposed to be reported through a mechanism compatible to
> Linux' syslog system.
> 
> There is no place for progress indicators here.

Why did you insist that he use the POST subsystem if you don't consider
it appropriate for what he's doing?

Or is it your opinion that it's absolutely useless to have a progress
indicator on a memory test[1], or that such things have no place
anywhere in U-Boot?

-Scott

[1] I don't care how automatic it is, if something is taking more than a few
seconds during boot, I'm going to be "monitoring" it as I sit there
twiddling my thumbs -- and if it takes that long, I'd rather it not be
automatic at all.

[U-Boot] [PATCH 2/7] Expand POST memory test to support arch-depended implementation.

[Wolfgang Denk]

Dear Scott Wood,

In message <20100830144648.10446b6b@schlenkerla.am.freescale.net> you wrote:
>
> > POST is supposed to be an automatic, unmonitored functionality.
> > Results are suposed to be reported through a mechanism compatible to
> > Linux' syslog system.
> > 
> > There is no place for progress indicators here.
> 
> Why did you insist that he use the POST subsystem if you don't consider
> it appropriate for what he's doing?

But I do consider it appropriate for the purpose; I just don't like
what the patch added.

> Or is it your opinion that it's absolutely useless to have a progress
> indicator on a memory test[1], or that such things have no place
> anywhere in U-Boot?

I do not think that progress indicators are useless. But I consider
this to be a separate set oif changes, that should be split into a
separate commit. And if we add such progress indicators, then we have
to make sure it integrates well with existing use.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
I have yet to add the ESP-driver to the kernel to read  the  mind  of
the user...                                       - Linus Torvalds in
      <Pine.LNX.3.91.960426110644.24860I-100000@linux.cs.Helsinki.FI>

[U-Boot] [PATCH 2/7] Expand POST memory test to support arch-depended implementation.

[Bas Mevissen]

On Thu, 02 Sep 2010 09:48:06 +0200, Wolfgang Denk <wd@denx.de> wrote:

> And if we add such progress indicators, then we have
> to make sure it integrates well with existing use.
> 

One could define a global environment variable or command to enable or
disable progress indicators. Just like "hash on" and "hash off" in the
FTP control protocol.

-- 
Bas

[U-Boot] [PATCH 3/7] Add memory test feature for mpc85xx POST.

[York Sun]

If enabled in config file and hwconfig, the memory test is performed
after DDR initialization when U-boot stills runs in flash and cache.
Whole memory is testable. It is mapped 2GB at a time using a sliding
TLB window. After the testing, DDR is remapped with up to 2GB memory
from the lowest address as normal.

Memory testing has different patterns which may be improved later.

If memory test fails, DDR DIMM SPD and DDR controller registers are
dumped. All zero values are omitted for better viewing.

A worker function __setup_ddr_tlbs() is introduced to implement more
control on physical address mapping.

Signed-off-by: York Sun <yorksun@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/cpu.c |  195 ++++++++++++++++++++++++++++++++++++++++
 arch/powerpc/cpu/mpc85xx/tlb.c |   16 ++--
 doc/README.fsl-ddr             |   21 ++++-
 3 files changed, 225 insertions(+), 7 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 00696f8..634a0cd 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -34,6 +34,9 @@
 #include <asm/io.h>
 #include <asm/mmu.h>
 #include <asm/fsl_law.h>
+#include <post.h>
+#include <asm/processor.h>
+#include <asm/fsl_ddr_sdram.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -282,3 +285,195 @@ void mpc85xx_reginfo(void)
 	print_laws();
 	print_lbc_regs();
 }
+
+#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
+
+/* Board-specific functions defined in each board's ddr.c */
+void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
+	unsigned int ctrl_num);
+void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
+		       phys_addr_t *rpn);
+unsigned int __setup_ddr_tlbs(phys_addr_t p_addr, unsigned int memsize_in_meg);
+
+static void dump_spd_ddr_reg(void)
+{
+	int i, j, k, m;
+	u8 *p_8;
+	u32 *p_32;
+	ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS];
+	generic_spd_eeprom_t
+	   spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
+
+	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
+		fsl_ddr_get_spd(spd[i], i);
+	puts("SPD data of all dimms (zero vaule is omitted)...\n");
+	puts("Byte (hex)  ");
+	k = 1;
+	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
+		for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
+			printf("Dimm%d ", k++);
+	puts("\n");
+	for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
+		m = 0;
+		printf("%3d (0x%02x)  ", k, k);
+		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
+				p_8 = (u8 *) &spd[i][j];
+				if (p_8[k]) {
+					printf("0x%02x  ", p_8[k]);
+					m++;
+				} else
+					puts("      ");
+			}
+		}
+		if (m)
+			puts("\n");
+		else
+			puts("\r");
+	}
+
+	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+		switch (i) {
+		case 0:
+			ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+			break;
+#ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR
+		case 1:
+			ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
+			break;
+#endif
+		default:
+			printf("%s unexpected controller number = %u\n",
+				__func__, i);
+			return;
+		}
+	}
+	printf("DDR registers dump for all controllers "
+		"(zero vaule is omitted)...\n");
+	puts("Offset (hex)   ");
+	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
+		printf("     Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
+	puts("\n");
+	for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) {
+		m = 0;
+		printf("%6d (0x%04x)", k * 4, k * 4);
+		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+			p_32 = (u32 *) ddr[i];
+			if (p_32[k]) {
+				printf("        0x%08x", p_32[k]);
+				m++;
+			} else
+				puts("                  ");
+		}
+		if (m)
+			puts("\n");
+		else
+			puts("\r");
+	}
+	puts("\n");
+}
+
+static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
+{
+	u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
+	unsigned long epn;
+	u32 tsize, valid, ptr;
+	phys_addr_t rpn = 0;
+	int ddr_esel;
+
+	ptr = vstart;
+	while (ptr < (vstart + size)) {
+		ddr_esel = find_tlb_idx((void *)ptr, 1);
+		if (ddr_esel != -1) {
+			read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
+			disable_tlb(ddr_esel);
+		}
+		ptr += TSIZE_TO_BYTES(tsize);
+	}
+	/* Setup new tlb to cover the physical address */
+	__setup_ddr_tlbs(p_addr, size>>20);
+
+	ptr = vstart;
+	ddr_esel = find_tlb_idx((void *)ptr, 1);
+	if (ddr_esel != -1) {
+		read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
+	} else {
+		printf("TLB error in function %s\n", __func__);
+		return -1;
+	}
+	return 0;
+}
+
+int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+	phys_addr_t test_cap, p_addr;
+	phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
+#if !defined(CONFIG_PHYS_64BIT) || \
+    !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
+	(CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
+		test_cap = p_size;
+#else
+		test_cap = gd->ram_size;
+#endif
+	p_addr = (*vstart) + (*size) + (*phys_offset);
+	if (p_addr < test_cap - 1) {
+		p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
+		if (reset_tlb(p_addr, p_size, phys_offset) == -1)
+			return -1;
+		*vstart = CONFIG_SYS_DDR_SDRAM_BASE;
+		*size = (u32) p_size;
+		printf("Testing 0x%08llx - 0x%08llx\n",
+			(u64)(*vstart) + (*phys_offset),
+			(u64)(*vstart) + (*phys_offset) + (*size) - 1);
+	} else
+		return 1;
+	return 0;
+}
+
+int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+	phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
+	*vstart = CONFIG_SYS_DDR_SDRAM_BASE;
+	*size = (u32) p_size;	/* CONFIG_MAX_MEM_MAPPED < 4G */
+	*phys_offset = 0;
+#if !defined(CONFIG_PHYS_64BIT) || \
+    !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
+	(CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
+		if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
+			puts("Cannot test more than ");
+			print_size(CONFIG_MAX_MEM_MAPPED,
+				" without proper 36BIT support.\n");
+		}
+#endif
+	printf("Testing 0x%08llx - 0x%08llx\n",
+		(u64)(*vstart) + (*phys_offset),
+		(u64)(*vstart) + (*phys_offset) + (*size) - 1);
+	return 0;
+}
+int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+	unsigned long epn;
+	u32 tsize, valid, ptr;
+	phys_addr_t rpn = 0;
+	int ddr_esel;
+	/* disable the TLBs for this testing */
+	ptr = *vstart;
+	while (ptr < (*vstart) + (*size)) {
+		ddr_esel = find_tlb_idx((void *)ptr, 1);
+		if (ddr_esel != -1) {
+			read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
+			disable_tlb(ddr_esel);
+		}
+		ptr += TSIZE_TO_BYTES(tsize);
+	}
+	puts("Remap DDR ");
+	setup_ddr_tlbs(gd->ram_size>>20);
+	puts("\n");
+	return 0;
+}
+
+void arch_memory_failure_handle(void)
+{
+	dump_spd_ddr_reg();
+}
+#endif
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index f2833a5..019fab7 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -245,7 +245,8 @@ void init_addr_map(void)
 }
 #endif
 
-unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
+unsigned int
+__setup_ddr_tlbs(phys_addr_t p_addr, unsigned int memsize_in_meg)
 {
 	int i;
 	unsigned int tlb_size;
@@ -275,21 +276,24 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
 
 		tlb_size = (camsize - 10) / 2;
 
-		set_tlb(1, ram_tlb_address, ram_tlb_address,
+		set_tlb(1, ram_tlb_address, p_addr,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, ram_tlb_index, tlb_size, 1);
 
 		size -= 1ULL << camsize;
 		memsize -= 1ULL << camsize;
 		ram_tlb_address += 1UL << camsize;
+		p_addr += 1UL << camsize;
 	}
 
 	if (memsize)
 		print_size(memsize, " left unmapped\n");
-
-	/*
-	 * Confirm that the requested amount of memory was mapped.
-	 */
 	return memsize_in_meg;
 }
+
+unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
+{
+	return
+		__setup_ddr_tlbs(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
+}
 #endif /* !CONFIG_NAND_SPL */
diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr
index e108a0d..20f531d 100644
--- a/doc/README.fsl-ddr
+++ b/doc/README.fsl-ddr
@@ -78,9 +78,28 @@ If the DDR controller supports address hashing, it can be enabled by hwconfig.
 Syntax is:
 hwconfig=fsl_ddr:addr_hash=true
 
+
+Memory testing options for mpc85xx
+==================================
+1. Memory test can be done one U-boot prompt comes up using mtest, or
+2. Memory test can be done with Power-On-Self-Test function, activated@compile time
+   and by hwconfig.
+
+   In order to enable the POST memory test, CONFIG_POST needs to be
+   defined in board configuraiton header file. By default, POST memory test performs
+   a fast test. A slow test can be enabled by changing the flag, or hwconfig can
+   be used to active slow test. To test memory bigger than 2GB, 36BIT support is
+   needed. Memory is tested within a 2GB window. TLBs are used to map the virtual
+   2GB window to physical address so that all physical memory can be tested.
+
+   Syntax of hwconfig
+   hwconfig=memtest:slow      or
+   hwconfig=memtest:fast
+
 Combination of hwconfig
 =======================
 Hwconfig can be combined with multiple parameters, for example, on a supported
 platform
 
-hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3
+hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,;memtest=slow
+
-- 
1.7.0.4

[U-Boot] [PATCH 3/7] Add memory test feature for mpc85xx POST.

[Wolfgang Denk]

Dear York Sun,

In message <1282944356-4020-3-git-send-email-yorksun@freescale.com> you wrote:
> If enabled in config file and hwconfig, the memory test is performed

POST memory testing is not controlled through hwconfig, but through
it's own set of environment variable settings.  Please don't mix
these.

NAK for the current implementation.


> after DDR initialization when U-boot stills runs in flash and cache.
> Whole memory is testable. It is mapped 2GB at a time using a sliding
> TLB window. After the testing, DDR is remapped with up to 2GB memory
> from the lowest address as normal.
> 
> Memory testing has different patterns which may be improved later.

What does that mean?


> If memory test fails, DDR DIMM SPD and DDR controller registers are
> dumped. All zero values are omitted for better viewing.

Do yoxpu consider this a good idea? I don't.

> A worker function __setup_ddr_tlbs() is introduced to implement more
> control on physical address mapping.
> 
> Signed-off-by: York Sun <yorksun@freescale.com>
> ---
>  arch/powerpc/cpu/mpc85xx/cpu.c |  195 ++++++++++++++++++++++++++++++++++++++++
>  arch/powerpc/cpu/mpc85xx/tlb.c |   16 ++--
>  doc/README.fsl-ddr             |   21 ++++-
>  3 files changed, 225 insertions(+), 7 deletions(-)

Should the code not live in the post/ directory?


> diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
> index 00696f8..634a0cd 100644
> --- a/arch/powerpc/cpu/mpc85xx/cpu.c
> +++ b/arch/powerpc/cpu/mpc85xx/cpu.c
> @@ -34,6 +34,9 @@
>  #include <asm/io.h>
>  #include <asm/mmu.h>
>  #include <asm/fsl_law.h>
> +#include <post.h>
> +#include <asm/processor.h>
> +#include <asm/fsl_ddr_sdram.h>
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> @@ -282,3 +285,195 @@ void mpc85xx_reginfo(void)
>  	print_laws();
>  	print_lbc_regs();
>  }
> +
> +#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
> +
> +/* Board-specific functions defined in each board's ddr.c */
> +void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
> +	unsigned int ctrl_num);
> +void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
> +		       phys_addr_t *rpn);
> +unsigned int __setup_ddr_tlbs(phys_addr_t p_addr, unsigned int memsize_in_meg);
> +
> +static void dump_spd_ddr_reg(void)
> +{
> +	int i, j, k, m;
> +	u8 *p_8;
> +	u32 *p_32;
> +	ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS];
> +	generic_spd_eeprom_t
> +	   spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];

Indentation by TABs only, please.

Blank line between declarations and code.

> +	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
> +		fsl_ddr_get_spd(spd[i], i);

Blank line here, too.

> +	puts("SPD data of all dimms (zero vaule is omitted)...\n");
> +	puts("Byte (hex)  ");
> +	k = 1;
> +	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
> +		for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
> +			printf("Dimm%d ", k++);

Need braces for multiline statements.

> +   In order to enable the POST memory test, CONFIG_POST needs to be
> +   defined in board configuraiton header file. By default, POST memory test performs
> +   a fast test. A slow test can be enabled by changing the flag, or hwconfig can
> +   be used to active slow test. To test memory bigger than 2GB, 36BIT support is

NAK. We provide exactly one way to control the POST system.  hwconfig
has nothing to do with that, so please don't pull that in here.


> -hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3
> +hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,;memtest=slow

NAK.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Software suppliers are trying to make their  software  packages  more
``user-friendly''.  .  .  .  Their best approach, so far, has been to
take all the old brochures, and stamp the words, ``user-friendly'' on
the cover.                                               - Bill Gates

[U-Boot] [PATCH 4/7] Enabled POST for generic mpc85xx

[York Sun]

Using PIC TFRR register for post word load/store for generic.
Fix post_word_store, post_word_load offset for mpc85xx with cpm

Signed-off-by: York Sun <yorksun@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/commproc.c |    4 ++--
 arch/powerpc/cpu/mpc85xx/cpu.c      |   17 +++++++++++++++++
 2 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/commproc.c b/arch/powerpc/cpu/mpc85xx/commproc.c
index f0fd1cb..1671b5e 100644
--- a/arch/powerpc/cpu/mpc85xx/commproc.c
+++ b/arch/powerpc/cpu/mpc85xx/commproc.c
@@ -189,7 +189,7 @@ m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel)
 void post_word_store (ulong a)
 {
 	volatile ulong *save_addr =
-		(volatile ulong *)(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR);
+		(volatile ulong *)(CONFIG_SYS_MPC85xx_CPM_ADDR + CPM_POST_WORD_ADDR);
 
 	*save_addr = a;
 }
@@ -197,7 +197,7 @@ void post_word_store (ulong a)
 ulong post_word_load (void)
 {
 	volatile ulong *save_addr =
-		(volatile ulong *)(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR);
+		(volatile ulong *)(CONFIG_SYS_MPC85xx_CPM_ADDR + CPM_POST_WORD_ADDR);
 
 	return *save_addr;
 }
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 634a0cd..9f3aa99 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -286,6 +286,23 @@ void mpc85xx_reginfo(void)
 	print_lbc_regs();
 }
 
+#ifdef CONFIG_POST
+
+__attribute__((weak))
+void post_word_store(ulong a)
+{
+	void *save_addr = (void *)(CONFIG_SYS_POST_WORD_ADDR);
+	out_be32(save_addr, a);
+}
+__attribute__((weak))
+ulong post_word_load(void)
+{
+	void *save_addr = (void *)(CONFIG_SYS_POST_WORD_ADDR);
+	return in_be32(save_addr);
+}
+
+#endif /* CONFIG_POST */
+
 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
 
 /* Board-specific functions defined in each board's ddr.c */
-- 
1.7.0.4

[U-Boot] [PATCH 4/7] Enabled POST for generic mpc85xx

[Wolfgang Denk]

Dear York Sun,

In message <1282944356-4020-4-git-send-email-yorksun@freescale.com> you wrote:
> Using PIC TFRR register for post word load/store for generic.
> Fix post_word_store, post_word_load offset for mpc85xx with cpm

Subject and commit messsage don't match.  Please fix.  Probably you
want to split this into two commits.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
PUBLIC NOTICE AS REQUIRED BY LAW:  Any Use of This  Product,  in  Any
Manner  Whatsoever,  Will  Increase  the  Amount  of  Disorder in the
Universe. Although No Liability Is Implied Herein,  the  Consumer  Is
Warned  That  This  Process Will Ultimately Lead to the Heat Death of
the Universe.

[U-Boot] [PATCH 5/7] Enable POST memory test for corenet_ds

[York Sun]

Signed-off-by: York Sun <yorksun@freescale.com>
---
 include/configs/corenet_ds.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index cf316e0..627f851 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -87,6 +87,7 @@
 #define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
 #endif
 
+#define CONFIG_POST CONFIG_SYS_POST_MEMORY	/* test POST memory test */
 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x00400000
 #define CONFIG_SYS_ALT_MEMTEST
@@ -272,6 +273,7 @@
 
 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_MPC85xx_PIC_ADDR + offsetof(ccsr_pic_t, tfrr))
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
-- 
1.7.0.4

[U-Boot] [PATCH 5/7] Enable POST memory test for corenet_ds

[Wolfgang Denk]

Dear York Sun,

In message <1282944356-4020-5-git-send-email-yorksun@freescale.com> you wrote:
> Signed-off-by: York Sun <yorksun@freescale.com>
> ---
>  include/configs/corenet_ds.h |    2 ++
>  1 files changed, 2 insertions(+), 0 deletions(-)
> 
> diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
> index cf316e0..627f851 100644
> --- a/include/configs/corenet_ds.h
> +++ b/include/configs/corenet_ds.h
> @@ -87,6 +87,7 @@
>  #define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
>  #endif
>  
> +#define CONFIG_POST CONFIG_SYS_POST_MEMORY	/* test POST memory test */
>  #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
>  #define CONFIG_SYS_MEMTEST_END		0x00400000
>  #define CONFIG_SYS_ALT_MEMTEST
> @@ -272,6 +273,7 @@
>  
>  #define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
>  #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
> +#define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_MPC85xx_PIC_ADDR + offsetof(ccsr_pic_t, tfrr))

The previous patch suggested that you were "Using PIC TFRR register
for post word load/store for generic" - then no such define should be
needed for any 85xx board.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
That Microsoft, the Trabant of the operating  system  world,  may  be
glancing  over the Berlin Wall at the Audis and BMWs and Mercedes. In
their own universe Trabants and Ladas were mainstream too...
                                                   -- Evan Leibovitch

[U-Boot] [PATCH 6/7] Enable POST memory test for P2020DS

[York Sun]

Signed-off-by: York Sun <yorksun@freescale.com>
---
 include/configs/P2020DS.h |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
index ee21d8b..8b76057 100644
--- a/include/configs/P2020DS.h
+++ b/include/configs/P2020DS.h
@@ -73,8 +73,9 @@
 #define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
 #endif
 
-#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x7fffffff
+#define CONFIG_POST CONFIG_SYS_POST_MEMORY	/* test POST memory test */
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
 
 /*
@@ -270,6 +271,7 @@
 
 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_MPC85xx_PIC_ADDR + offsetof(ccsr_pic_t, tfrr))
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
-- 
1.7.0.4

[U-Boot] [PATCH 7/7] Fix parameters to support RDIMM for P2020DS

[York Sun]

Signed-off-by: York Sun <yorksun@freescale.com>
---
 arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c |    1 +
 board/freescale/p2020ds/ddr.c            |    4 ++--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index dccb7aa..e82082e 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -613,6 +613,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 #if defined(CONFIG_FSL_DDR3)
 	md_en = popts->mirrored_dimm;
 #endif
+	rcw_en = popts->registered_dimm_en;
 	qd_en = popts->quad_rank_present ? 1 : 0;
 	ddr->ddr_sdram_cfg_2 = (0
 		| ((frc_sr & 0x1) << 31)
diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c
index 30d640f..9a1b075 100644
--- a/board/freescale/p2020ds/ddr.c
+++ b/board/freescale/p2020ds/ddr.c
@@ -68,7 +68,7 @@ const board_specific_parameters_t board_specific_parameters[][20] = {
 		{550, 680,    1,    4,   0x1f,    3,  0},
 		{681, 850,    1,    4,   0x1f,    4,  0}
 #else
-		{  0, 850,    2,    4,   0x1f,    4,  0},
+		{  0, 850,    2,    6,   0x1f,    4,  0},
 		{  0, 850,    1,    4,   0x1f,    4,  0}
 #endif
 	},
@@ -120,7 +120,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 	/* Write leveling override */
 	popts->wrlvl_override = 1;
 	popts->wrlvl_sample = 0xa;
-	popts->wrlvl_start = 0x7;
+	popts->wrlvl_start = 0x8;
 	/* Rtt and Rtt_WR override */
 	popts->rtt_override = 1;
 	popts->rtt_override_value = DDR3_RTT_120_OHM;
-- 
1.7.0.4

[U-Boot] [PATCH 7/7] Fix parameters to support RDIMM for P2020DS

[Kumar Gala]

On Aug 27, 2010, at 4:25 PM, York Sun wrote:

> Signed-off-by: York Sun <yorksun@freescale.com>
> ---
> arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c |    1 +
> board/freescale/p2020ds/ddr.c            |    4 ++--
> 2 files changed, 3 insertions(+), 2 deletions(-)

applied

- K

[U-Boot] [PATCH 1/7] fix dma for 36bit addressing

[Kumar Gala]

On Aug 27, 2010, at 4:25 PM, York Sun wrote:

> Use more bits to support 36-bit addressing
> 
> Signed-off-by: York Sun <yorksun@freescale.com>
> ---
> drivers/dma/fsl_dma.c |    8 ++++++--
> 1 files changed, 6 insertions(+), 2 deletions(-)

applied

- K