[U-Boot] [PATCH v2 1/2] APM82xxx: Add CPU and other peripheral support

[U-Boot] [PATCH v2 1/2] APM82xxx: Add CPU and other peripheral support

[tmarri at apm.com]

From: Tirumala Marri <tmarri@apm.com>

APM82XXX is a new line of SoCs which are derivatives of
PPC44X family of processors.

This patch adds support of CPU, cache,
tlb, 32k ocm, bootstraps, PLB AHB bus, DDR and
Some common register definitions.

Signed-off-by: Tirumala R Marri <tmarri@apm.com>
---
 V1:
  * Squash some of the patches.
  * add space between "||" and "\".
  * Add spaces around operators.
  * Unsigned int to u32.
  * Add empty line which was removed.
  * remove warning "unused variable" in cpu_init.c
 V2:
  * Removed Defines added to 405ex.
---
 arch/powerpc/cpu/ppc4xx/cpu.c           |   35 ++++++++++++-
 arch/powerpc/cpu/ppc4xx/cpu_init.c      |    8 ++-
 arch/powerpc/cpu/ppc4xx/speed.c         |   85 ++++++++++++++++++++++++++++++-
 arch/powerpc/cpu/ppc4xx/start.S         |   10 +++-
 arch/powerpc/include/asm/ppc4xx-ebc.h   |    4 ++
 arch/powerpc/include/asm/ppc4xx-isram.h |    8 ++-
 arch/powerpc/include/asm/ppc4xx-sdram.h |   12 ++--
 arch/powerpc/include/asm/ppc4xx-uic.h   |    5 +-
 arch/powerpc/include/asm/processor.h    |    1 +
 include/ppc440.h                        |   57 ++++++++++++++++++++-
 include/ppc4xx.h                        |    7 ++-
 11 files changed, 207 insertions(+), 25 deletions(-)

diff --git a/arch/powerpc/cpu/ppc4xx/cpu.c b/arch/powerpc/cpu/ppc4xx/cpu.c
index 851065c..5fe5d8c 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu.c
@@ -80,7 +80,8 @@ static int pci_async_enabled(void)
 #endif /* CONFIG_PCI */
 
 #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
-    !defined(CONFIG_405) && !defined(CONFIG_405EX)
+    !defined(CONFIG_405) && !defined(CONFIG_405EX) && \
+    !defined(CONFIG_APM82XXX)
 int pci_arbiter_enabled(void)
 {
 #if defined(CONFIG_405GP)
@@ -250,6 +251,21 @@ static char *bootstrap_str[] = {
 };
 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
 #endif
+#if defined(CONFIG_APM82XXX)
+#define SDR0_PINSTP_SHIFT       29
+static char *bootstrap_str[] = {
+	"RESERVED",
+	"RESERVED",
+	"RESERVED",
+	"NAND (8 bits)",
+	"NOR  (8 bits)",
+	"NOR  (8 bits) w/PLL Bypassed",
+	"I2C (Addr 0x54)",
+	"I2C (Addr 0x52)",
+};
+static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
+#endif
+
 
 #if defined(SDR0_PINSTP_SHIFT)
 static int bootstrap_option(void)
@@ -285,7 +301,7 @@ int checkcpu (void)
 	uint pvr = get_pvr();
 	ulong clock = gd->cpu_clk;
 	char buf[32];
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || defined(CONFIG_APM82XXX)
 	u32 reg;
 #endif
 
@@ -304,6 +320,8 @@ int checkcpu (void)
 
 #if defined(CONFIG_XILINX_440)
 	puts("IBM PowerPC 4");
+#elif defined(CONFIG_APM82XXX)
+	puts("APM PowerPC APM82");
 #else
 	puts("AMCC PowerPC 4");
 #endif
@@ -316,7 +334,7 @@ int checkcpu (void)
 #if defined(CONFIG_440)
 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
 	puts("60");
-#else
+#elif !defined(CONFIG_APM82XXX)
 	puts("40");
 #endif
 #endif
@@ -598,7 +616,18 @@ int checkcpu (void)
 		puts("GX Rev. A");
 		strcpy(addstr, "No Security support");
 		break;
+#if defined(CONFIG_APM82XXX)
+	case PVR_APM82XXX_RA:
+		mfsdr(SDR0_ECID3, reg);
+		if (reg & 0x00200000)
+			puts("181 Rev. A");
 
+		if (reg & 0x00100000)
+			strcpy(addstr, "No Security support");
+		else
+			strcpy(addstr, "Security support");
+		break;
+#endif
 	case PVR_VIRTEX5:
 		puts("x5 VIRTEX5");
 		break;
diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c
index c04eede..8765059 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu_init.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c
@@ -222,13 +222,15 @@ void reconfigure_pll(u32 new_cpu_freq)
 void
 cpu_init_f (void)
 {
-#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX)
+#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || \
+	defined(CONFIG_460EX)
 	u32 val;
 #endif
 
 	reconfigure_pll(CONFIG_SYS_PLL_RECONFIG);
 
-#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CONFIG_SYS_4xx_GPIO_TABLE)
+#if (defined(CONFIG_405EP) || defined(CONFIG_405EX)) && \
+	!defined(CONFIG_SYS_4xx_GPIO_TABLE) && !defined(CONFIG_APM82XXX)
 	/*
 	 * GPIO0 setup (select GPIO or alternate function)
 	 */
@@ -384,7 +386,7 @@ cpu_init_f (void)
 #if defined(CONFIG_405EX) || \
     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)  || \
-    defined(CONFIG_460SX)
+    defined(CONFIG_460SX) || defined(CONFIG_APM82XXX)
 	/*
 	 * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
 	 */
diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c
index 906face..b613275 100644
--- a/arch/powerpc/cpu/ppc4xx/speed.c
+++ b/arch/powerpc/cpu/ppc4xx/speed.c
@@ -189,7 +189,7 @@ ulong get_PCI_freq (void)
 #elif defined(CONFIG_440)
 
 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_460SX)
+    defined(CONFIG_460SX) || defined(CONFIG_APM82XXX)
 static u8 pll_fwdv_multi_bits[] = {
 	/* values for:  1 - 16 */
 	0x00, 0x01, 0x0f, 0x04, 0x09, 0x0a, 0x0d, 0x0e, 0x03, 0x0c,
@@ -250,6 +250,88 @@ u32 get_cpr0_fbdv(unsigned long cpr_reg_fbdv)
 	return 0;
 }
 
+#if defined(CONFIG_APM82XXX)
+
+/*
+ * Specific for APM82XXX
+ * Change:
+ *	PLL registers reflect the current PLL setting of the chip.
+ *	So unlike previous implementation that reads bootstrap
+ *	registers to determine system clocking information, this
+ *	implementation directly extracts the information from
+ *	current PLL registers values.
+ */
+void get_sys_info(sys_info_t *sysInfo)
+{
+	unsigned long plld;
+	unsigned long temp;
+	unsigned long mul;
+	unsigned long cpudv;
+	unsigned long plb2dv;
+	unsigned long ddr2dv;
+
+	/* Calculate Forward divisor A and Feeback divisor */
+	mfcpr(CPR0_PLLD, plld);
+
+	temp = CPR0_PLLD_FWDVA(plld);
+	sysInfo->pllFwdDivA = get_cpr0_fwdv(temp);
+
+	temp = CPR0_PLLD_FDV(plld);
+	sysInfo->pllFbkDiv = get_cpr0_fbdv(temp);
+
+	/* Calculate OPB clock divisor */
+	mfcpr(CPR0_OPBD, temp);
+	temp = CPR0_OPBD_OPBDV(temp);
+	sysInfo->pllOpbDiv = temp ? temp : 4;
+
+	/* Calculate Peripheral clock divisor */
+	mfcpr(CPR0_PERD, temp);
+	temp = CPR0_PERD_PERDV(temp);
+	sysInfo->pllExtBusDiv = temp ? temp : 4;
+
+	/* Calculate CPU clock divisor */
+	mfcpr(CPR0_CPUD, temp);
+	temp = CPR0_CPUD_CPUDV(temp);
+	cpudv = temp ? temp : 8;
+
+	/* Calculate PLB2 clock divisor */
+	mfcpr(CPR0_PLB2D, temp);
+	temp = CPR0_PLB2D_PLB2DV(temp);
+	plb2dv = temp ? temp : 4;
+
+	/* Calculate DDR2 clock divisor */
+	mfcpr(CPR0_DDR2D, temp);
+	temp = CPR0_DDR2D_DDR2DV(temp);
+	ddr2dv = temp ? temp : 4;
+
+	/* Calculate 'M' based on feedback source */
+	mfcpr(CPR0_PLLC, temp);
+	temp = CPR0_PLLC_SEL(temp);
+	if (temp == 0) {
+		/* PLL internal feedback */
+		mul = sysInfo->pllFbkDiv;
+	} else {
+		/* PLL PerClk feedback */
+		mul = sysInfo->pllFwdDivA * sysInfo->pllFbkDiv * cpudv
+			* plb2dv * 2 * sysInfo->pllOpbDiv *
+			  sysInfo->pllExtBusDiv;
+	}
+
+	/* Now calculate the individual clocks */
+	sysInfo->freqVCOMhz = (mul * CONFIG_SYS_CLK_FREQ) + (mul >> 1);
+	sysInfo->freqProcessor = sysInfo->freqVCOMhz /
+		sysInfo->pllFwdDivA / cpudv;
+	sysInfo->freqPLB = sysInfo->freqVCOMhz /
+		sysInfo->pllFwdDivA / cpudv / plb2dv / 2;
+	sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv;
+	sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv;
+	sysInfo->freqDDR = sysInfo->freqVCOMhz /
+		sysInfo->pllFwdDivA / cpudv / ddr2dv / 2;
+	sysInfo->freqUART = sysInfo->freqPLB;
+}
+
+#else
+
 /*
  * AMCC_TODO: verify this routine against latest EAS, cause stuff changed
  *            with latest EAS
@@ -307,6 +389,7 @@ void get_sys_info (sys_info_t * sysInfo)
 
 	return;
 }
+#endif
 
 #elif defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index 5296dad..e3210b0 100644
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -700,7 +700,8 @@ _start:
     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
     defined(CONFIG_460SX)
 	mtdcr	L2_CACHE_CFG,r0		/* Ensure L2 Cache is off */
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+      defined(CONFIG_APM82XXX)
 	lis	r1, 0x0000
 	ori	r1,r1,0x0008		/* Set L2_CACHE_CFG[RDBW]=1 */
 	mtdcr	L2_CACHE_CFG,r1
@@ -728,7 +729,8 @@ _start:
 	lis	r1, 0x8003
 	ori	r1,r1, 0x0980		/* fourth 64k */
 	mtdcr	ISRAM0_SB3CR,r1
-#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \
+      defined(CONFIG_460GT) || defined(CONFIG_APM82XXX)
 	lis	r1,0x0000		/* BAS = X_0000_0000 */
 	ori	r1,r1,0x0984		/* first 64k */
 	mtdcr	ISRAM0_SB0CR,r1
@@ -752,7 +754,11 @@ _start:
 	mtdcr	ISRAM1_PMEG,r1
 
 	lis	r1,0x0004		/* BAS = 4_0004_0000 */
+#if defined(CONFIG_APM82XXX) /* APM82XXX only has 32KB of OCM */
+	ori     r1,r1,0x0784            /* 32k */
+#else
 	ori	r1,r1,0x0984		/* 64k */
+#endif
 	mtdcr	ISRAM1_SB0CR,r1
 #endif
 #elif defined(CONFIG_460SX)
diff --git a/arch/powerpc/include/asm/ppc4xx-ebc.h b/arch/powerpc/include/asm/ppc4xx-ebc.h
index 9c17e46..245e487 100644
--- a/arch/powerpc/include/asm/ppc4xx-ebc.h
+++ b/arch/powerpc/include/asm/ppc4xx-ebc.h
@@ -73,6 +73,10 @@
 #define EBC_NUM_BANKS	3
 #endif
 
+#if defined(CONFIG_APM82XXX)
+#define EBC_NUM_BANKS   3
+#endif
+
 /* Bank Configuration Register */
 #define EBC_BXCR(n)		(n)
 #define EBC_BXCR_BANK_SIZE(n)	(0x100000 << (((n) & EBC_BXCR_BS_MASK) >> 17))
diff --git a/arch/powerpc/include/asm/ppc4xx-isram.h b/arch/powerpc/include/asm/ppc4xx-isram.h
index d6d17ac..fa9e164 100644
--- a/arch/powerpc/include/asm/ppc4xx-isram.h
+++ b/arch/powerpc/include/asm/ppc4xx-isram.h
@@ -25,7 +25,8 @@
 /*
  * Internal SRAM
  */
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_APM82XXX)
 #define ISRAM0_DCR_BASE 0x380
 #else
 #define ISRAM0_DCR_BASE 0x020
@@ -42,7 +43,8 @@
 #define ISRAM0_REVID	(ISRAM0_DCR_BASE+0x09)	/* SRAM bus revision id reg */
 #define ISRAM0_DPC	(ISRAM0_DCR_BASE+0x0a)	/* SRAM data parity check reg */
 
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_APM82XXX)
 #define ISRAM1_DCR_BASE 0x0B0
 #define ISRAM1_SB0CR	(ISRAM1_DCR_BASE+0x00)	/* SRAM1 bank config 0*/
 #define ISRAM1_BEAR	(ISRAM1_DCR_BASE+0x04)	/* SRAM1 bus error addr reg */
@@ -60,7 +62,7 @@
 #if defined (CONFIG_440GX) || \
     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_460SX)
+    defined(CONFIG_460SX) || defined(CONFIG_APM82XXX)
 #define L2_CACHE_BASE	0x030
 #define L2_CACHE_CFG	(L2_CACHE_BASE+0x00)	/* L2 Cache Config      */
 #define L2_CACHE_CMD	(L2_CACHE_BASE+0x01)	/* L2 Cache Command     */
diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h
index 4ec1ef8..fcda187 100644
--- a/arch/powerpc/include/asm/ppc4xx-sdram.h
+++ b/arch/powerpc/include/asm/ppc4xx-sdram.h
@@ -292,7 +292,7 @@
  */
 #if defined(CONFIG_440SPE) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_460SX)
+    defined(CONFIG_460SX) || defined(CONFIG_APM82XXX)
 #define SDRAM_RXBAS_SDBA_MASK		0xFFE00000	/* Base address	*/
 #define SDRAM_RXBAS_SDBA_ENCODE(n)	((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000))
 #define SDRAM_RXBAS_SDBA_DECODE(n)	((((phys_size_t)(n)) & 0xFFE00000) << 2)
@@ -365,7 +365,7 @@
 /*
  * Memory controller registers
  */
-#ifdef CONFIG_405EX
+#if defined(CONFIG_405EX) || defined(CONFIG_APM82XXX)
 #define SDRAM_BESR	0x00	/* PLB bus error status (read/clear)         */
 #define SDRAM_BESRT	0x01	/* PLB bus error status (test/set)           */
 #define SDRAM_BEARL	0x02	/* PLB bus error address low                 */
@@ -375,9 +375,9 @@
 #define SDRAM_PLBOPT	0x08	/* PLB slave options                         */
 #define SDRAM_PUABA	0x09	/* PLB upper address base                    */
 #define SDRAM_MCSTAT	0x1F	/* memory controller status                  */
-#else /* CONFIG_405EX */
+#else /* CONFIG_405EX || CONFIG_APM82XXX */
 #define SDRAM_MCSTAT	0x14	/* memory controller status                  */
-#endif /* CONFIG_405EX */
+#endif /* CONFIG_405EX || CONFIG_APM82XXX */
 #define SDRAM_MCOPT1	0x20	/* memory controller options 1               */
 #define SDRAM_MCOPT2	0x21	/* memory controller options 2               */
 #define SDRAM_MODT0	0x22	/* on die termination for bank 0             */
@@ -423,12 +423,12 @@
 #define SDRAM_MEMODE	0x89	/* memory extended mode                      */
 #define SDRAM_ECCES	0x98	/* ECC error status                          */
 #define SDRAM_CID	0xA4	/* core ID                                   */
-#ifndef CONFIG_405EX
+#if !defined(CONFIG_405EX) && !defined(CONFIG_APM82XXX)
 #define SDRAM_RID	0xA8	/* revision ID                               */
 #endif
 #define SDRAM_FCSR	0xB0	/* feedback calibration status               */
 #define SDRAM_RTSR	0xB1	/* run time status tracking                  */
-#ifdef CONFIG_405EX
+#if  defined(CONFIG_405EX) || defined(CONFIG_APM82XXX)
 #define SDRAM_RID	0xF8	/* revision ID                               */
 #endif
 
diff --git a/arch/powerpc/include/asm/ppc4xx-uic.h b/arch/powerpc/include/asm/ppc4xx-uic.h
index 782d045..787e9f7 100644
--- a/arch/powerpc/include/asm/ppc4xx-uic.h
+++ b/arch/powerpc/include/asm/ppc4xx-uic.h
@@ -31,7 +31,7 @@
  */
 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_460SX)
+    defined(CONFIG_460SX) || defined(CONFIG_APM82XXX)
 #define UIC_MAX		4
 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_405EX)
@@ -252,7 +252,8 @@
 #define VECNUM_ETH0		(32 + 28)
 #endif /* CONFIG_440SPE */
 
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_APM82XXX)
 /* UIC 0 */
 #define VECNUM_UIC2NCI		10
 #define VECNUM_UIC2CI		11
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 84a1e2e..c58492d 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -916,6 +916,7 @@
 #define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */
 #define PVR_460GX_RA    0x13541802 /* 460GX rev A                   */
 #define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */
+#define PVR_APM82XXX_RA 0x12C41C80 /* APM82XXX rev A */
 #define PVR_601		0x00010000
 #define PVR_602		0x00050000
 #define PVR_603		0x00030000
diff --git a/include/ppc440.h b/include/ppc440.h
index c807dda..b5c1832 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -58,6 +58,25 @@
  | Clocking Controller
  +----------------------------------------------------------------------------*/
 /* values for clkcfga register - indirect addressing of these regs */
+#if defined(CONFIG_APM82XXX)
+#define CPR0_CLKUPD      0x0020
+#define CPR0_PLLC        0x0040
+#define CPR0_PLLC_SEL(pllc)      (((pllc) & 0x01000000) >> 24)
+#define CPR0_PLLD        0x0060
+#define CPR0_PLLD_FDV(plld)     (((plld) & 0xff000000) >> 24)
+#define CPR0_PLLD_FWDVA(plld)    (((plld) & 0x000f0000) >> 16)
+#define CPR0_CPUD        0x0080
+#define CPR0_CPUD_CPUDV(cpud)    (((cpud) & 0x07000000) >> 24)
+#define CPR0_PLB2D       0x00a0
+#define CPR0_PLB2D_PLB2DV(plb2d) (((plb2d) & 0x06000000) >> 25)
+#define CPR0_OPBD        0x00c0
+#define CPR0_OPBD_OPBDV(opbd)    (((opbd) & 0x03000000) >> 24)
+#define CPR0_PERD       0x00e0
+#define CPR0_PERD_PERDV(perd)    (((perd) & 0x03000000) >> 24)
+#define CPR0_DDR2D      0x0100
+#define CPR0_DDR2D_DDR2DV(ddr2d) (((ddr2d) & 0x06000000) >> 25)
+#define CLK_ICFG	0x0140
+#else
 #define CPR0_PLLC	0x0040
 #define CPR0_PLLD	0x0060
 #define CPR0_PRIMAD0	0x0080
@@ -67,6 +86,7 @@
 #define CPR0_MALD	0x0100
 #define CPR0_SPCID	0x0120
 #define CPR0_ICFG	0x0140
+#endif /*if defined(CONFIG_APM82XXX) */
 
 /* 440EPX boot strap options */
 #define BOOT_STRAP_OPTION_A	0x00000000
@@ -1275,7 +1295,36 @@
 #define SDR0_AHB_CFG		0x370
 #define SDR0_USB2HOST_CFG	0x371
 #endif /* CONFIG_460EX || CONFIG_460GT */
+#if defined(CONFIG_APM82XXX)
+
+#define SDR0_DDR0			0x00E1
+#define SDR0_DDR0_DDRM_ENCODE(n)	((((u32)(n)) & 0x03) << 29)
+#define SDR0_DDR0_DDRM_DECODE(n)	((((u32)(n)) >> 29) & 0x03)
+#define SDR0_DDR0_TUNE_ENCODE(n)	((((u32)(n)) & 0x2FF) <<0)
+#define SDR0_DDR0_TUNE_DECODE(n)	((((u32)(n)) >> 0) & 0x2FF)
+
+#define SDR_SDSTP1_RL_DECODE(x) (((x) & 0x000C0000) >> 18)
+#define SDR_SDSTP1_RL_EBC       0x0
+#define SDR_SDSTP1_RL_NDFC      0x2
+
+/* ECID */
+#define SDR0_ECID0             0x0080
+#define SDR0_ECID1             0x0081
+#define SDR0_ECID2             0x0082
+#define SDR0_ECID3             0x0083
+
+/* AHB config. */
+#define AHB_TOP                 0xA4
+#define AHB_BOT                 0xA5
+#define SDR0_AHB_CFG            0x370
+
+/* DDR SDRAM Controller clock (CPR register)*/
+#define SDR0_DDRCE                     0x00E0 /* SDR register */
+#define CPR0_DDR2D                     0x0100 /* CPR register */
+#define CPR0_DDR2D_DDR2DV_ENCODE(n)    ((((u32)(n)) & 0x03) << 25)
+#define CPR0_DDR2D_DDR2DV_DECODE(n)    ((((u32)(n)) >> 25) & 0x03)
 
+#endif
 #define SDR0_SDCS_SDD			(0x80000000 >> 31)
 
 #if defined(CONFIG_440GP)
@@ -1517,7 +1566,8 @@
 #define SDR0_EBC0		0x00000100
 #define SDR0_SDSTP2		0x00004001
 #define SDR0_SDSTP3		0x00004001
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+      defined(CONFIG_APM82XXX)
 
 #define SDR0_SRST0		SDR0_SRST  /* for compatability reasons */
 #define SDR0_SRST0_BGO		0x80000000 /* PLB to OPB bridge */
@@ -1909,9 +1959,12 @@
 
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_APM82XXX)
 #define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE+0x00000B00)
+#if !defined(CONFIG_APM82XXX)
 #define GPIO1_BASE		(CONFIG_SYS_PERIPHERAL_BASE+0x00000C00)
+#endif
 
 #define GPIO0_OR		(GPIO0_BASE+0x0)
 #define GPIO0_TCR		(GPIO0_BASE+0x4)
diff --git a/include/ppc4xx.h b/include/ppc4xx.h
index ee30a4c..3224d5f 100644
--- a/include/ppc4xx.h
+++ b/include/ppc4xx.h
@@ -44,14 +44,15 @@
 #if defined(CONFIG_405EX) || \
     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_460SX)
+    defined(CONFIG_460SX) || defined(CONFIG_APM82XXX)
 #define CONFIG_SDRAM_PPC4xx_IBM_DDR2	/* IBM DDR(2) controller */
 #endif
 
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) ||	\
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) ||	\
     defined(CONFIG_405EZ) || defined(CONFIG_405EX) ||	\
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_APM82XXX)
 #define CONFIG_NAND_NDFC
 #endif
 
@@ -61,7 +62,7 @@
     defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)  || \
-    defined(CONFIG_460SX)
+    defined(CONFIG_460SX) || defined(CONFIG_APM82XXX)
 
 #define PLB_ARBITER_BASE		0x80
 
-- 
1.6.1.rc3

[U-Boot] [PATCH v2 1/2] APM82xxx: Add CPU and other peripheral support

[Wolfgang Denk]

Dear tmarri at apm.com,

In message <1283390214-28255-1-git-send-email-tmarri@apm.com> you wrote:
> From: Tirumala Marri <tmarri@apm.com>
> 
> APM82XXX is a new line of SoCs which are derivatives of
> PPC44X family of processors.
> 
> This patch adds support of CPU, cache,
> tlb, 32k ocm, bootstraps, PLB AHB bus, DDR and
> Some common register definitions.
...
>  #if defined(CONFIG_XILINX_440)
>  	puts("IBM PowerPC 4");
> +#elif defined(CONFIG_APM82XXX)
> +	puts("APM PowerPC APM82");

Hm... is this APM82? Official press releases refer to this as
APM821xx? Or ist it APM82xxx?

On the other hand, this seems to be a 464 core, so should we not print
464 here?

>  #else
>  	puts("AMCC PowerPC 4");
>  #endif
> @@ -316,7 +334,7 @@ int checkcpu (void)
>  #if defined(CONFIG_440)
>  #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
>  	puts("60");
> -#else
> +#elif !defined(CONFIG_APM82XXX)
>  	puts("40");

This gets confusing.

If you don't decide to print "64" here, then please pull all the APM82???
code into a separate #ifdef block.

> --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c
> +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c
> @@ -222,13 +222,15 @@ void reconfigure_pll(u32 new_cpu_freq)
>  void
>  cpu_init_f (void)
>  {
> -#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX)
> +#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || \
> +	defined(CONFIG_460EX)

Why do you modify this line?  Coding style fixes should go separate.

> -#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CONFIG_SYS_4xx_GPIO_TABLE)
> +#if (defined(CONFIG_405EP) || defined(CONFIG_405EX)) && \
> +	!defined(CONFIG_SYS_4xx_GPIO_TABLE) && !defined(CONFIG_APM82XXX)

Please keep list sorted.

> +#if defined(CONFIG_APM82XXX)
> +
> +/*
> + * Specific for APM82XXX
> + * Change:
> + *	PLL registers reflect the current PLL setting of the chip.
> + *	So unlike previous implementation that reads bootstrap
> + *	registers to determine system clocking information, this
> + *	implementation directly extracts the information from
> + *	current PLL registers values.
> + */

Please remove references to "previous implementation" which is unknown
here anyway.


> -#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT)
> +#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \
> +      defined(CONFIG_460GT) || defined(CONFIG_APM82XXX)
>  	lis	r1,0x0000		/* BAS = X_0000_0000 */
>  	ori	r1,r1,0x0984		/* first 64k */

Should the size be adjusted here, too?

>  	mtdcr	ISRAM0_SB0CR,r1
> @@ -752,7 +754,11 @@ _start:
>  	mtdcr	ISRAM1_PMEG,r1
>  
>  	lis	r1,0x0004		/* BAS = 4_0004_0000 */
> +#if defined(CONFIG_APM82XXX) /* APM82XXX only has 32KB of OCM */
> +	ori     r1,r1,0x0784            /* 32k */
> +#else
>  	ori	r1,r1,0x0984		/* 64k */

Please get rid of these magic numbers and add a #define for a symbolic
constant so the code becomes readable, and the selection can be done
on a per-CPU base, i. e. without needing #ifdef's here.


> diff --git a/include/ppc440.h b/include/ppc440.h
> index c807dda..b5c1832 100644
> --- a/include/ppc440.h
> +++ b/include/ppc440.h

Hm... you are adding a number of large blocks of code, all #ifdef'ed.

This is ugly, difficult to read and difficult to maintain.

Why not adding a new file  include/apm82xxx.h  instead?


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Due to lack of disk space, this fortune database has been discontinued.

[U-Boot] [PATCH v2 1/2] APM82xxx: Add CPU and other peripheral support

[Tirumala Marri]

Mr Wolfgang,

>
> On the other hand, this seems to be a 464 core, so should we not print
> 464 here?
[Marri] Interesting point, For all other processors we were printing SoC
name not the CPU core name.
APM82xxx is SoC name.


> > diff --git a/include/ppc440.h b/include/ppc440.h
> > index c807dda..b5c1832 100644
> > --- a/include/ppc440.h
> > +++ b/include/ppc440.h
>
> Hm... you are adding a number of large blocks of code, all #ifdef'ed.
>
> This is ugly, difficult to read and difficult to maintain.
>
> Why not adding a new file  include/apm82xxx.h  instead?
>
[Marri] If we create new file it would cause too many changes in the
common files.
When more and more APM8xxxx processors with new registers definitions
being released
At that point we can create separate file. Please suggest ?


Regards,
Marri

[U-Boot] [PATCH v2 1/2] APM82xxx: Add CPU and other peripheral support

[Wolfgang Denk]

Dear Tirumala Marri,

In message <f5b257a2367890d26637726f5c8e1dea@mail.gmail.com> you wrote:
> 
> > On the other hand, this seems to be a 464 core, so should we not print
> > 464 here?
> [Marri] Interesting point, For all other processors we were printing SoC
> name not the CPU core name.
> APM82xxx is SoC name.

OK.

Hm.., the whole CPU ID code in "arch/powerpc/cpu/ppc4xx/cpu.c" has
become a mess.

Stefan:

is there any deeper logic for the repeated #ifdef's there, when we
finally do a switch on the PVR anyway?

Instead of painstakingly concatenating  "AMCC PowerPC 4" with "05"
and later "GP Rev. B" we could shrink this into a plain

	case PVR_405GP_RB:
		puts("AMCC PowerPC 405GP Rev. B");
		break;
	
Or am I missing something?

Let's get rid of all these nested #ifdef's...


> > > diff --git a/include/ppc440.h b/include/ppc440.h
> > > index c807dda..b5c1832 100644
> > > --- a/include/ppc440.h
> > > +++ b/include/ppc440.h
> >
> > Hm... you are adding a number of large blocks of code, all #ifdef'ed.
> >
> > This is ugly, difficult to read and difficult to maintain.
> >
> > Why not adding a new file  include/apm82xxx.h  instead?
> >
> [Marri] If we create new file it would cause too many changes in the
> common files.
> When more and more APM8xxxx processors with new registers definitions
> being released
> At that point we can create separate file. Please suggest ?

If there are plans for more and more APM8xxxx processors with new
registers definitions to be released we should not create a mess now
and later go into efforts to clean it up again, but start with a
separate register definitions file apm82xxx.h now.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The more sins you confess, the more books you will sell.

[U-Boot] [PATCH v2 1/2] APM82xxx: Add CPU and other peripheral support

[Stefan Roese]

Hi Wolfgang,

On Thursday 02 September 2010 21:01:37 Wolfgang Denk wrote:
> Hm.., the whole CPU ID code in "arch/powerpc/cpu/ppc4xx/cpu.c" has
> become a mess.
> 
> Stefan:
> 
> is there any deeper logic for the repeated #ifdef's there, when we
> finally do a switch on the PVR anyway?
> 
> Instead of painstakingly concatenating  "AMCC PowerPC 4" with "05"
> and later "GP Rev. B" we could shrink this into a plain
> 
> 	case PVR_405GP_RB:
> 		puts("AMCC PowerPC 405GP Rev. B");
> 		break;
> 
> Or am I missing something?

IIRC, then the main reason for this is the code size reduction. Using your 
version would increase the code size quite a bit. But I concur, it would be 
much better readable. So just let me know, and I'll try to come up with a 
patch cleaning this up a bit.

> Let's get rid of all these nested #ifdef's...

As described in some comments, the problem is that some SoC's have the same 
PVR (for example 440EP rev C and 440GR rev B have same PVR). I have no idea 
how this identification could be solved without such ifdef's.

But you are right. Some of the ifdef's can be removed. Again, this would also 
result in a bigger image size though.

Cheers,
Stefan

--
DENX Software Engineering GmbH,      MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de

[U-Boot] [PATCH v2 1/2] APM82xxx: Add CPU and other peripheral support

[Wolfgang Denk]

Dear Stefan Roese,

In message <201009030946.22440.sr@denx.de> you wrote:
>
> IIRC, then the main reason for this is the code size reduction. Using your 
> version would increase the code size quite a bit. But I concur, it would be 
> much better readable. So just let me know, and I'll try to come up with a 
> patch cleaning this up a bit.

Maybe some common parts (like "AMCC PowerPC ") could be split off.

For the rest, the compelex code needs also space, so I'm not sure
about the end result.

> As described in some comments, the problem is that some SoC's have the same 
> PVR (for example 440EP rev C and 440GR rev B have same PVR). I have no idea 
> how this identification could be solved without such ifdef's.

I see.

> But you are right. Some of the ifdef's can be removed. Again, this would also 
> result in a bigger image size though.

Really? We should measure the effect.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The most exciting phrase to hear in science, the one that heralds new
discoveries, is not "Eureka!" (I found it!) but "That's funny ..."
                                                      -- Isaac Asimov

[U-Boot] [PATCH v2 1/2] APM82xxx: Add CPU and other peripheral support

[Stefan Roese]

Hi Wolfgang,

On Friday 03 September 2010 10:32:53 Wolfgang Denk wrote:
> Dear Stefan Roese,
> 
> In message <201009030946.22440.sr@denx.de> you wrote:
> > IIRC, then the main reason for this is the code size reduction. Using
> > your version would increase the code size quite a bit. But I concur, it
> > would be much better readable. So just let me know, and I'll try to come
> > up with a patch cleaning this up a bit.
> 
> Maybe some common parts (like "AMCC PowerPC ") could be split off.

Yes, this would help a bit. I'll add this on list.
 
> For the rest, the compelex code needs also space, so I'm not sure
> about the end result.
> 
> > As described in some comments, the problem is that some SoC's have the
> > same PVR (for example 440EP rev C and 440GR rev B have same PVR). I have
> > no idea how this identification could be solved without such ifdef's.
> 
> I see.
> 
> > But you are right. Some of the ifdef's can be removed. Again, this would
> > also result in a bigger image size though.
> 
> Really? We should measure the effect.

I'll work on this a bit in the near future and will post my findings.

Cheers,
Stefan

--
DENX Software Engineering GmbH,      MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de

[U-Boot] [PATCH v2 1/2] APM82xxx: Add CPU and other peripheral support

[Tirumala Marri]

Mr Wolfgang,
> Hm... is this APM82? Official press releases refer to this as
> APM821xx? Or ist it APM82xxx?
[Marri] You are correct APM821XX is right name.

>
> If you don't decide to print "64" here, then please pull all the
> APM82???
> code into a separate #ifdef block.
[Marri] Sure will do.

>
> > -#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) ||
> defined(CONFIG_460GT)
> > +#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \
> > +      defined(CONFIG_460GT) || defined(CONFIG_APM82XXX)
> >  	lis	r1,0x0000		/* BAS = X_0000_0000 */
> >  	ori	r1,r1,0x0984		/* first 64k */
>
> Should the size be adjusted here, too?
[Marri] No, It is same as other SoCs.

>
> >  	mtdcr	ISRAM0_SB0CR,r1
> > @@ -752,7 +754,11 @@ _start:
> >  	mtdcr	ISRAM1_PMEG,r1
> >
> >  	lis	r1,0x0004		/* BAS = 4_0004_0000 */
> > +#if defined(CONFIG_APM82XXX) /* APM82XXX only has 32KB of OCM */
> > +	ori     r1,r1,0x0784            /* 32k */
> > +#else
> >  	ori	r1,r1,0x0984		/* 64k */
>
> Please get rid of these magic numbers and add a #define for a symbolic
> constant so the code becomes readable, and the selection can be done
> on a per-CPU base, i. e. without needing #ifdef's here.


[Marri] I will define CONFIG_SYS_OCM_SIZE . But for now this is only added

Bluestone.h. I need to remove  "#if defined(CONFIG_APM821XX) I will have
to
Add CONFIG_SYS_OCM_SIZE to all the board config files which are based on
460Ex and 460GT.
I think that would be completely different patch.


>
>
> > diff --git a/include/ppc440.h b/include/ppc440.h
> > index c807dda..b5c1832 100644
> > --- a/include/ppc440.h
> > +++ b/include/ppc440.h
>
> Hm... you are adding a number of large blocks of code, all #ifdef'ed.
>
> This is ugly, difficult to read and difficult to maintain.
>
> Why not adding a new file  include/apm82xxx.h  instead?
>
[Marri] I will work on this .

Regards,
Marri

[U-Boot] [PATCH v2 1/2] APM82xxx: Add CPU and other peripheral support

[Stefan Roese]

Hi Marri,

On Friday 03 September 2010 03:48:44 Tirumala Marri wrote:
> > >  	mtdcr	ISRAM0_SB0CR,r1
> > > 
> > > @@ -752,7 +754,11 @@ _start:
> > >  	mtdcr	ISRAM1_PMEG,r1
> > >  	
> > >  	lis	r1,0x0004		/* BAS = 4_0004_0000 */
> > > 
> > > +#if defined(CONFIG_APM82XXX) /* APM82XXX only has 32KB of OCM */
> > > +	ori     r1,r1,0x0784            /* 32k */
> > > +#else
> > > 
> > >  	ori	r1,r1,0x0984		/* 64k */
> > 
> > Please get rid of these magic numbers and add a #define for a symbolic
> > constant so the code becomes readable, and the selection can be done
> > on a per-CPU base, i. e. without needing #ifdef's here.
> 
> [Marri] I will define CONFIG_SYS_OCM_SIZE . But for now this is only added
> Bluestone.h. I need to remove  "#if defined(CONFIG_APM821XX) I will have
> to
> Add CONFIG_SYS_OCM_SIZE to all the board config files which are based on
> 460Ex and 460GT.
> I think that would be completely different patch.

Since the OCM size is SoC specific, I would prefer not to put such a define in 
each and every board config header, but in a SoC header. There you could 
automatically select the OCM size depending on the SoC type. No change in the 
board config header needed.
 
Cheers,
Stefan

--
DENX Software Engineering GmbH,      MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de