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* [U-Boot] [PATCH v3 1/2] APM821xx: Add CPU support
@ 2010-09-08  2:06 tmarri at apm.com
  2010-09-09 14:45 ` Stefan Roese
  0 siblings, 1 reply; 7+ messages in thread
From: tmarri at apm.com @ 2010-09-08  2:06 UTC (permalink / raw)
  To: u-boot

From: Tirumala Marri <tmarri@apm.com>

APM821XX is a new line of SoCs which are derivatives of
PPC44X family of processors. This patch adds support of CPU, cache,
tlb, 32k ocm, bootstraps, PLB and AHB bus.

Signed-off-by: Tirumala R Marri <tmarri@apm.com>
---
V2:
  * Removed Defines added to 405ex.
V3:  
  * Change APM82XXX to APM821XX
  * Modify the way cpu id is printed.
  * Correct inadvertent change.
  * Sort define list.
  * Remove comment for get_sys_info().
  * Define a symbolic constat ISRAM1_OCM_SIZE.
  * Create apm821xx.h instead of using ppc440.h
  * Correct multiline comment.
---
 arch/powerpc/cpu/ppc4xx/cpu.c           |   36 ++-
 arch/powerpc/cpu/ppc4xx/cpu_init.c      |    5 +-
 arch/powerpc/cpu/ppc4xx/speed.c         |   76 +++++-
 arch/powerpc/cpu/ppc4xx/start.S         |   11 +-
 arch/powerpc/cpu/ppc4xx/tlb.c           |    2 +
 arch/powerpc/include/asm/ppc4xx-ebc.h   |    4 +
 arch/powerpc/include/asm/ppc4xx-isram.h |   14 +-
 arch/powerpc/include/asm/ppc4xx-sdram.h |   12 +-
 arch/powerpc/include/asm/ppc4xx-uic.h   |    5 +-
 arch/powerpc/include/asm/processor.h    |    1 +
 include/apm821xx.h                      |  493 +++++++++++++++++++++++++++++++
 include/ppc4xx.h                        |   11 +-
 12 files changed, 645 insertions(+), 25 deletions(-)

diff --git a/arch/powerpc/cpu/ppc4xx/cpu.c b/arch/powerpc/cpu/ppc4xx/cpu.c
index 851065c..2c12907 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu.c
@@ -80,7 +80,8 @@ static int pci_async_enabled(void)
 #endif /* CONFIG_PCI */
 
 #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
-    !defined(CONFIG_405) && !defined(CONFIG_405EX)
+    !defined(CONFIG_405) && !defined(CONFIG_405EX) && \
+    !defined(CONFIG_APM821XX)
 int pci_arbiter_enabled(void)
 {
 #if defined(CONFIG_405GP)
@@ -250,6 +251,21 @@ static char *bootstrap_str[] = {
 };
 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
 #endif
+#if defined(CONFIG_APM821XX)
+#define SDR0_PINSTP_SHIFT       29
+static char *bootstrap_str[] = {
+	"RESERVED",
+	"RESERVED",
+	"RESERVED",
+	"NAND (8 bits)",
+	"NOR  (8 bits)",
+	"NOR  (8 bits) w/PLL Bypassed",
+	"I2C (Addr 0x54)",
+	"I2C (Addr 0x52)",
+};
+static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
+#endif
+
 
 #if defined(SDR0_PINSTP_SHIFT)
 static int bootstrap_option(void)
@@ -285,7 +301,7 @@ int checkcpu (void)
 	uint pvr = get_pvr();
 	ulong clock = gd->cpu_clk;
 	char buf[32];
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || defined(CONFIG_APM821XX)
 	u32 reg;
 #endif
 
@@ -301,7 +317,9 @@ int checkcpu (void)
 		puts("CPU:   ");
 
 	get_sys_info(&sys_info);
-
+#if defined(CONFIG_APM821XX)
+	puts("APM PowerPC APM821XX");
+#else
 #if defined(CONFIG_XILINX_440)
 	puts("IBM PowerPC 4");
 #else
@@ -320,6 +338,7 @@ int checkcpu (void)
 	puts("40");
 #endif
 #endif
+#endif
 
 	switch (pvr) {
 	case PVR_405GP_RB:
@@ -598,7 +617,18 @@ int checkcpu (void)
 		puts("GX Rev. A");
 		strcpy(addstr, "No Security support");
 		break;
+#if defined(CONFIG_APM821XX)
+	case PVR_APM821XX_RA:
+		mfsdr(SDR0_ECID3, reg);
+		if (reg & 0x00200000)
+			puts("181 Rev. A");
 
+		if (reg & 0x00100000)
+			strcpy(addstr, "No Security support");
+		else
+			strcpy(addstr, "Security support");
+		break;
+#endif
 	case PVR_VIRTEX5:
 		puts("x5 VIRTEX5");
 		break;
diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c
index b31bd0b..009a35a 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu_init.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c
@@ -237,7 +237,8 @@ cpu_init_f (void)
 
 	reconfigure_pll(CONFIG_SYS_PLL_RECONFIG);
 
-#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CONFIG_SYS_4xx_GPIO_TABLE)
+#if !defined(CONFIG_APM821XX) && (defined(CONFIG_405EP) || \
+     defined(CONFIG_405EX)) && !defined(CONFIG_SYS_4xx_GPIO_TABLE)
 	/*
 	 * GPIO0 setup (select GPIO or alternate function)
 	 */
@@ -393,7 +394,7 @@ cpu_init_f (void)
 #if defined(CONFIG_405EX) || \
     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)  || \
-    defined(CONFIG_460SX)
+    defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
 	/*
 	 * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
 	 */
diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c
index 906face..9538736 100644
--- a/arch/powerpc/cpu/ppc4xx/speed.c
+++ b/arch/powerpc/cpu/ppc4xx/speed.c
@@ -189,7 +189,7 @@ ulong get_PCI_freq (void)
 #elif defined(CONFIG_440)
 
 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_460SX)
+    defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
 static u8 pll_fwdv_multi_bits[] = {
 	/* values for:  1 - 16 */
 	0x00, 0x01, 0x0f, 0x04, 0x09, 0x0a, 0x0d, 0x0e, 0x03, 0x0c,
@@ -250,6 +250,79 @@ u32 get_cpr0_fbdv(unsigned long cpr_reg_fbdv)
 	return 0;
 }
 
+#if defined(CONFIG_APM821XX)
+
+void get_sys_info(sys_info_t *sysInfo)
+{
+	unsigned long plld;
+	unsigned long temp;
+	unsigned long mul;
+	unsigned long cpudv;
+	unsigned long plb2dv;
+	unsigned long ddr2dv;
+
+	/* Calculate Forward divisor A and Feeback divisor */
+	mfcpr(CPR0_PLLD, plld);
+
+	temp = CPR0_PLLD_FWDVA(plld);
+	sysInfo->pllFwdDivA = get_cpr0_fwdv(temp);
+
+	temp = CPR0_PLLD_FDV(plld);
+	sysInfo->pllFbkDiv = get_cpr0_fbdv(temp);
+
+	/* Calculate OPB clock divisor */
+	mfcpr(CPR0_OPBD, temp);
+	temp = CPR0_OPBD_OPBDV(temp);
+	sysInfo->pllOpbDiv = temp ? temp : 4;
+
+	/* Calculate Peripheral clock divisor */
+	mfcpr(CPR0_PERD, temp);
+	temp = CPR0_PERD_PERDV(temp);
+	sysInfo->pllExtBusDiv = temp ? temp : 4;
+
+	/* Calculate CPU clock divisor */
+	mfcpr(CPR0_CPUD, temp);
+	temp = CPR0_CPUD_CPUDV(temp);
+	cpudv = temp ? temp : 8;
+
+	/* Calculate PLB2 clock divisor */
+	mfcpr(CPR0_PLB2D, temp);
+	temp = CPR0_PLB2D_PLB2DV(temp);
+	plb2dv = temp ? temp : 4;
+
+	/* Calculate DDR2 clock divisor */
+	mfcpr(CPR0_DDR2D, temp);
+	temp = CPR0_DDR2D_DDR2DV(temp);
+	ddr2dv = temp ? temp : 4;
+
+	/* Calculate 'M' based on feedback source */
+	mfcpr(CPR0_PLLC, temp);
+	temp = CPR0_PLLC_SEL(temp);
+	if (temp == 0) {
+		/* PLL internal feedback */
+		mul = sysInfo->pllFbkDiv;
+	} else {
+		/* PLL PerClk feedback */
+		mul = sysInfo->pllFwdDivA * sysInfo->pllFbkDiv * cpudv
+			* plb2dv * 2 * sysInfo->pllOpbDiv *
+			  sysInfo->pllExtBusDiv;
+	}
+
+	/* Now calculate the individual clocks */
+	sysInfo->freqVCOMhz = (mul * CONFIG_SYS_CLK_FREQ) + (mul >> 1);
+	sysInfo->freqProcessor = sysInfo->freqVCOMhz /
+		sysInfo->pllFwdDivA / cpudv;
+	sysInfo->freqPLB = sysInfo->freqVCOMhz /
+		sysInfo->pllFwdDivA / cpudv / plb2dv / 2;
+	sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv;
+	sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv;
+	sysInfo->freqDDR = sysInfo->freqVCOMhz /
+		sysInfo->pllFwdDivA / cpudv / ddr2dv / 2;
+	sysInfo->freqUART = sysInfo->freqPLB;
+}
+
+#else
+
 /*
  * AMCC_TODO: verify this routine against latest EAS, cause stuff changed
  *            with latest EAS
@@ -307,6 +380,7 @@ void get_sys_info (sys_info_t * sysInfo)
 
 	return;
 }
+#endif
 
 #elif defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index 4bad32f..74277fe 100644
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -700,7 +700,8 @@ _start:
     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
     defined(CONFIG_460SX)
 	mtdcr	L2_CACHE_CFG,r0		/* Ensure L2 Cache is off */
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+      defined(CONFIG_APM821XX)
 	lis	r1, 0x0000
 	ori	r1,r1,0x0008		/* Set L2_CACHE_CFG[RDBW]=1 */
 	mtdcr	L2_CACHE_CFG,r1
@@ -728,7 +729,8 @@ _start:
 	lis	r1, 0x8003
 	ori	r1,r1, 0x0980		/* fourth 64k */
 	mtdcr	ISRAM0_SB3CR,r1
-#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \
+      defined(CONFIG_460GT) || defined(CONFIG_APM821XX)
 	lis	r1,0x0000		/* BAS = X_0000_0000 */
 	ori	r1,r1,0x0984		/* first 64k */
 	mtdcr	ISRAM0_SB0CR,r1
@@ -741,7 +743,8 @@ _start:
 	lis	r1, 0x0003
 	ori	r1,r1, 0x0984		/* fourth 64k */
 	mtdcr	ISRAM0_SB3CR,r1
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_APM821XX)	
 	lis	r2,0x7fff
 	ori	r2,r2,0xffff
 	mfdcr	r1,ISRAM1_DPC
@@ -752,7 +755,7 @@ _start:
 	mtdcr	ISRAM1_PMEG,r1
 
 	lis	r1,0x0004		/* BAS = 4_0004_0000 */
-	ori	r1,r1,0x0984		/* 64k */
+	ori	r1,r1,ISRAM1_SIZE	/* ocm size */
 	mtdcr	ISRAM1_SB0CR,r1
 #endif
 #elif defined(CONFIG_460SX)
diff --git a/arch/powerpc/cpu/ppc4xx/tlb.c b/arch/powerpc/cpu/ppc4xx/tlb.c
index 24a9a9c..9a8964a 100644
--- a/arch/powerpc/cpu/ppc4xx/tlb.c
+++ b/arch/powerpc/cpu/ppc4xx/tlb.c
@@ -25,7 +25,9 @@
 
 #if defined(CONFIG_440)
 
+#if !defined(CONFIG_APM821XX)
 #include <ppc440.h>
+#endif
 #include <asm/cache.h>
 #include <asm/io.h>
 #include <asm/mmu.h>
diff --git a/arch/powerpc/include/asm/ppc4xx-ebc.h b/arch/powerpc/include/asm/ppc4xx-ebc.h
index 9c17e46..2c79118 100644
--- a/arch/powerpc/include/asm/ppc4xx-ebc.h
+++ b/arch/powerpc/include/asm/ppc4xx-ebc.h
@@ -73,6 +73,10 @@
 #define EBC_NUM_BANKS	3
 #endif
 
+#if defined(CONFIG_APM821XX)
+#define EBC_NUM_BANKS   3
+#endif
+
 /* Bank Configuration Register */
 #define EBC_BXCR(n)		(n)
 #define EBC_BXCR_BANK_SIZE(n)	(0x100000 << (((n) & EBC_BXCR_BS_MASK) >> 17))
diff --git a/arch/powerpc/include/asm/ppc4xx-isram.h b/arch/powerpc/include/asm/ppc4xx-isram.h
index d6d17ac..32e1297 100644
--- a/arch/powerpc/include/asm/ppc4xx-isram.h
+++ b/arch/powerpc/include/asm/ppc4xx-isram.h
@@ -25,7 +25,8 @@
 /*
  * Internal SRAM
  */
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_APM821XX)
 #define ISRAM0_DCR_BASE 0x380
 #else
 #define ISRAM0_DCR_BASE 0x020
@@ -42,7 +43,8 @@
 #define ISRAM0_REVID	(ISRAM0_DCR_BASE+0x09)	/* SRAM bus revision id reg */
 #define ISRAM0_DPC	(ISRAM0_DCR_BASE+0x0a)	/* SRAM data parity check reg */
 
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_APM821XX)
 #define ISRAM1_DCR_BASE 0x0B0
 #define ISRAM1_SB0CR	(ISRAM1_DCR_BASE+0x00)	/* SRAM1 bank config 0*/
 #define ISRAM1_BEAR	(ISRAM1_DCR_BASE+0x04)	/* SRAM1 bus error addr reg */
@@ -54,13 +56,19 @@
 #define ISRAM1_DPC	(ISRAM1_DCR_BASE+0x0a)	/* SRAM1 data parity check reg */
 #endif /* CONFIG_460EX || CONFIG_460GT */
 
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define ISRAM1_SIZE 0x0984 /* OCM size 64k */
+#elif defined(CONFIG_APM821XX)
+#define ISRAM1_SIZE 0x0784 /* OCM size 32k */
+#endif
+
 /*
  * L2 Cache
  */
 #if defined (CONFIG_440GX) || \
     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_460SX)
+    defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
 #define L2_CACHE_BASE	0x030
 #define L2_CACHE_CFG	(L2_CACHE_BASE+0x00)	/* L2 Cache Config      */
 #define L2_CACHE_CMD	(L2_CACHE_BASE+0x01)	/* L2 Cache Command     */
diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h
index 4ec1ef8..8575c4d 100644
--- a/arch/powerpc/include/asm/ppc4xx-sdram.h
+++ b/arch/powerpc/include/asm/ppc4xx-sdram.h
@@ -292,7 +292,7 @@
  */
 #if defined(CONFIG_440SPE) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_460SX)
+    defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
 #define SDRAM_RXBAS_SDBA_MASK		0xFFE00000	/* Base address	*/
 #define SDRAM_RXBAS_SDBA_ENCODE(n)	((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000))
 #define SDRAM_RXBAS_SDBA_DECODE(n)	((((phys_size_t)(n)) & 0xFFE00000) << 2)
@@ -365,7 +365,7 @@
 /*
  * Memory controller registers
  */
-#ifdef CONFIG_405EX
+#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX)
 #define SDRAM_BESR	0x00	/* PLB bus error status (read/clear)         */
 #define SDRAM_BESRT	0x01	/* PLB bus error status (test/set)           */
 #define SDRAM_BEARL	0x02	/* PLB bus error address low                 */
@@ -375,9 +375,9 @@
 #define SDRAM_PLBOPT	0x08	/* PLB slave options                         */
 #define SDRAM_PUABA	0x09	/* PLB upper address base                    */
 #define SDRAM_MCSTAT	0x1F	/* memory controller status                  */
-#else /* CONFIG_405EX */
+#else /* CONFIG_405EX || CONFIG_APM821XX */
 #define SDRAM_MCSTAT	0x14	/* memory controller status                  */
-#endif /* CONFIG_405EX */
+#endif /* CONFIG_405EX || CONFIG_APM821XX */
 #define SDRAM_MCOPT1	0x20	/* memory controller options 1               */
 #define SDRAM_MCOPT2	0x21	/* memory controller options 2               */
 #define SDRAM_MODT0	0x22	/* on die termination for bank 0             */
@@ -423,12 +423,12 @@
 #define SDRAM_MEMODE	0x89	/* memory extended mode                      */
 #define SDRAM_ECCES	0x98	/* ECC error status                          */
 #define SDRAM_CID	0xA4	/* core ID                                   */
-#ifndef CONFIG_405EX
+#if !defined(CONFIG_405EX) && !defined(CONFIG_APM821XX)
 #define SDRAM_RID	0xA8	/* revision ID                               */
 #endif
 #define SDRAM_FCSR	0xB0	/* feedback calibration status               */
 #define SDRAM_RTSR	0xB1	/* run time status tracking                  */
-#ifdef CONFIG_405EX
+#if  defined(CONFIG_405EX) || defined(CONFIG_APM821XX)
 #define SDRAM_RID	0xF8	/* revision ID                               */
 #endif
 
diff --git a/arch/powerpc/include/asm/ppc4xx-uic.h b/arch/powerpc/include/asm/ppc4xx-uic.h
index 782d045..3714a0a 100644
--- a/arch/powerpc/include/asm/ppc4xx-uic.h
+++ b/arch/powerpc/include/asm/ppc4xx-uic.h
@@ -31,7 +31,7 @@
  */
 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_460SX)
+    defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
 #define UIC_MAX		4
 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_405EX)
@@ -252,7 +252,8 @@
 #define VECNUM_ETH0		(32 + 28)
 #endif /* CONFIG_440SPE */
 
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_APM821XX)
 /* UIC 0 */
 #define VECNUM_UIC2NCI		10
 #define VECNUM_UIC2CI		11
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 84a1e2e..9cafe85 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -916,6 +916,7 @@
 #define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */
 #define PVR_460GX_RA    0x13541802 /* 460GX rev A                   */
 #define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */
+#define PVR_APM821XX_RA 0x12C41C80 /* APM821XX rev A */
 #define PVR_601		0x00010000
 #define PVR_602		0x00050000
 #define PVR_603		0x00030000
diff --git a/include/apm821xx.h b/include/apm821xx.h
new file mode 100644
index 0000000..fdf7fb7
--- /dev/null
+++ b/include/apm821xx.h
@@ -0,0 +1,493 @@
+/*----------------------------------------------------------------------------+
+|   This source code is dual-licensed.  You may use it under the terms of the
+|   GNU General Public License version 2, or under the license below.
+|
+|	This source code has been made available to you by IBM on an AS-IS
+|	basis.	Anyone receiving this source is licensed under IBM
+|	copyrights to use it in any way he or she deems fit, including
+|	copying it, modifying it, compiling it, and redistributing it either
+|	with or without modifications.	No license under IBM patents or
+|	patent applications is to be implied by the copyright license.
+|
+|	Any user of this software should understand that IBM cannot provide
+|	technical support for this software and will not be responsible for
+|	any consequences resulting from the use of this software.
+|
+|	Any person who transfers this source code or any derivative work
+|	must include the IBM copyright notice, this paragraph, and the
+|	preceding two paragraphs in the transferred software.
+|
+|	COPYRIGHT   I B M   CORPORATION 1999
+|	LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
++----------------------------------------------------------------------------*/
+
+/*
+ * (C) Copyright 2006
+ * Sylvie Gohl,             AMCC/IBM, gohl.sylvie at fr.ibm.com
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol at fr.ibm.com
+ * Thierry Roman,           AMCC/IBM, thierry_roman at fr.ibm.com
+ * Alain Saurel,            AMCC/IBM, alain.saurel at fr.ibm.com
+ * Robert Snyder,           AMCC/IBM, rob.snyder at fr.ibm.com
+ * Tirumala Marri,          APM/IBM, tmarri@apm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __APM821XX_H__
+#define __APM821XX_H__
+
+#define CONFIG_SYS_DCACHE_SIZE		(32 << 10)	/* For AMCC 440 CPUs */
+
+/****************************************************************************
+ * DCRs & Related
+ ****************************************************************************/
+
+/*
+ * Clocking Controller
+ */
+/* values for clkcfga register - indirect addressing of these regs */
+#define CPR0_CLKUPD      0x0020
+#define CPR0_PLLC        0x0040
+#define CPR0_PLLC_SEL(pllc)      (((pllc) & 0x01000000) >> 24)
+#define CPR0_PLLD        0x0060
+#define CPR0_PLLD_FDV(plld)     (((plld) & 0xff000000) >> 24)
+#define CPR0_PLLD_FWDVA(plld)    (((plld) & 0x000f0000) >> 16)
+#define CPR0_CPUD        0x0080
+#define CPR0_CPUD_CPUDV(cpud)    (((cpud) & 0x07000000) >> 24)
+#define CPR0_PLB2D       0x00a0
+#define CPR0_PLB2D_PLB2DV(plb2d) (((plb2d) & 0x06000000) >> 25)
+#define CPR0_OPBD        0x00c0
+#define CPR0_OPBD_OPBDV(opbd)    (((opbd) & 0x03000000) >> 24)
+#define CPR0_PERD       0x00e0
+#define CPR0_PERD_PERDV(perd)    (((perd) & 0x03000000) >> 24)
+#define CPR0_DDR2D      0x0100
+#define CPR0_DDR2D_DDR2DV(ddr2d) (((ddr2d) & 0x06000000) >> 25)
+#define CLK_ICFG	0x0140
+
+#define BOOT_STRAP_OPTION_A	0x00000000
+#define BOOT_STRAP_OPTION_B	0x00000001
+#define BOOT_STRAP_OPTION_D	0x00000003
+#define BOOT_STRAP_OPTION_E	0x00000004
+
+#define SDR0_SDSTP0	0x0020	/* */
+#define SDR0_SDSTP1	0x0021	/* */
+#define SDR0_PINSTP	0x0040
+#define SDR0_SDCS0	0x0060
+#define SDR0_EBC	0x0100
+#define SDR0_UART0	0x0120	/* UART0 Config */
+#define SDR0_UART1	0x0121	/* UART1 Config */
+#define SDR0_UART2	0x0122	/* UART2 Config */
+#define SDR0_UART3	0x0123	/* UART3 Config */
+#define SDR0_CP440	0x0180
+#define SDR0_XCR	0x01c0
+#define SDR0_XPLLC	0x01c1
+#define SDR0_XPLLD	0x01c2
+#define SDR0_SRST	0x0200
+#define SD0_AMP0	0x0240	/* Override PLB4 prio for up to 8 masters */
+#define SD0_AMP1	0x0241	/* Override PLB3 prio for up to 8 masters */
+#define SDR0_PCI0	0x0300
+#define SDR0_USB0	0x0320
+#define SDR0_CUST0	0x4000
+#define SDR0_CUST1	0x4002
+#define SDR0_PFC0	0x4100	/* Pin Function 0 */
+#define SDR0_PFC1	0x4101	/* Pin Function 1 */
+#define SDR0_MFR	0x4300	/* SDR0_MFR reg */
+
+/*
+ *Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
+ */
+#define CCR0_PRE		0x40000000
+#define CCR0_CRPE		0x08000000
+#define CCR0_DSTG		0x00200000
+#define CCR0_DAPUIB		0x00100000
+#define CCR0_DTB		0x00008000
+#define CCR0_GICBT		0x00004000
+#define CCR0_GDCBT		0x00002000
+#define CCR0_FLSTA		0x00000100
+#define CCR0_ICSLC_MASK		0x0000000C
+#define CCR0_ICSLT_MASK		0x00000003
+#define CCR1_TCS_MASK		0x00000080
+#define CCR1_TCS_INTCLK		0x00000000
+#define CCR1_TCS_EXTCLK		0x00000080
+#define MMUCR_SWOA		0x01000000
+#define MMUCR_U1TE		0x00400000
+#define MMUCR_U2SWOAE		0x00200000
+#define MMUCR_DULXE		0x00800000
+#define MMUCR_IULXE		0x00400000
+#define MMUCR_STS		0x00100000
+#define MMUCR_STID_MASK		0x000000FF
+
+/*
+ * External Bus Controller
+ */
+/* values for EBC0_CFGADDR register - indirect addressing of these regs */
+#define PB0CR		0x00	/* periph bank 0 config reg             */
+#define PB1CR		0x01	/* periph bank 1 config reg             */
+#define PB2CR		0x02	/* periph bank 2 config reg             */
+#define PB3CR		0x03	/* periph bank 3 config reg             */
+#define PB4CR		0x04	/* periph bank 4 config reg             */
+#define PB5CR		0x05	/* periph bank 5 config reg             */
+#define PB6CR		0x06	/* periph bank 6 config reg             */
+#define PB7CR		0x07	/* periph bank 7 config reg             */
+#define PB0AP		0x10	/* periph bank 0 access parameters      */
+#define PB1AP		0x11	/* periph bank 1 access parameters      */
+#define PB2AP		0x12	/* periph bank 2 access parameters      */
+#define PB3AP		0x13	/* periph bank 3 access parameters      */
+#define PB4AP		0x14	/* periph bank 4 access parameters      */
+#define PB5AP		0x15	/* periph bank 5 access parameters      */
+#define PB6AP		0x16	/* periph bank 6 access parameters      */
+#define PB7AP		0x17	/* periph bank 7 access parameters      */
+#define PBEAR		0x20	/* periph bus error addr reg            */
+#define PBESR		0x21	/* periph bus error status reg          */
+#define EBC0_CFG	0x23	/* external bus configuration reg       */
+
+/*
+ * On-Chip Buses
+ */
+/*
+ * Clocking, Power Management and Chip Control
+ */
+#define CNTRL_DCR_BASE 0x0b0
+
+#define CPC0_SYS0	(CNTRL_DCR_BASE+0x30)	/* System config reg 0 */
+#define CPC0_SYS1	(CNTRL_DCR_BASE+0x31)	/* System config reg 1 */
+
+#define CPC0_STRP0	(CNTRL_DCR_BASE+0x34)	/* Power-on config reg 0(RO) */
+#define CPC0_STRP1	(CNTRL_DCR_BASE+0x35)	/* Power-on config reg 1(RO) */
+
+#define CPC0_GPIO	(CNTRL_DCR_BASE+0x38)	/* GPIO config reg  */
+
+#define CPC0_CR0		(CNTRL_DCR_BASE+0x3b)	/* Control 0 reg */
+#define CPC0_CR1		(CNTRL_DCR_BASE+0x3a)	/* Control 1 reg */
+
+/*
+ * DMA
+ */
+#define DMA_DCR_BASE 0x100
+#define DMACR0	(DMA_DCR_BASE+0x00)	/* DMA channel control reg 0       */
+#define DMACT0	(DMA_DCR_BASE+0x01)	/* DMA count register 0            */
+#define DMACR1	(DMA_DCR_BASE+0x08)	/* DMA channel control reg 1       */
+#define DMACT1	(DMA_DCR_BASE+0x09)	/* DMA count register 1            */
+#define DMACR2	(DMA_DCR_BASE+0x10)	/* DMA channel control reg 2       */
+#define DMACT2	(DMA_DCR_BASE+0x11)	/* DMA count register 2            */
+#define DMACR3	(DMA_DCR_BASE+0x18)	/* DMA channel control reg 2       */
+#define DMASR	(DMA_DCR_BASE+0x20)	/* DMA status register             */
+#define DMASGC	(DMA_DCR_BASE+0x23)	/* DMA scatter/gather cmd register */
+
+/*
+ * Memory Access Layer
+ */
+#define MAL_DCR_BASE 0x180
+#define MAL0_CFG	(MAL_DCR_BASE + 0x00)	/* MAL Config reg       */
+#define MAL0_ESR	(MAL_DCR_BASE + 0x01)	/* Error Status (Read/Clear)*/
+#define MAL0_IER	(MAL_DCR_BASE + 0x02)	/* Interrupt enable */
+#define MAL0_TXCASR	(MAL_DCR_BASE + 0x04)	/* TX Channel active (set) */
+#define MAL0_TXCARR	(MAL_DCR_BASE + 0x05)	/* TX Channel active (rst) */
+#define MAL0_TXEOBISR	(MAL_DCR_BASE + 0x06)	/* TX End of buf int status */
+#define MAL0_TXDEIR	(MAL_DCR_BASE + 0x07)	/* TX Descr. Error Int */
+#define MAL0_TXBADDR	(MAL_DCR_BASE + 0x09)	/* TX descriptor base addr */
+#define MAL0_RXCASR	(MAL_DCR_BASE + 0x10)	/* RX Channel active (set) */
+#define MAL0_RXCARR	(MAL_DCR_BASE + 0x11)	/* RX Channel actve (reset) */
+#define MAL0_RXEOBISR	(MAL_DCR_BASE + 0x12)	/* RX End of buf int status */
+#define MAL0_RXDEIR	(MAL_DCR_BASE + 0x13)	/* RX Descr. Error Int */
+#define MAL0_RXBADDR	(MAL_DCR_BASE + 0x15)	/* RX descriptor base addr */
+#define MAL0_TXCTP0R	(MAL_DCR_BASE + 0x20)	/* TX 0 Channel table pointer */
+#define MAL0_TXCTP1R	(MAL_DCR_BASE + 0x21)	/* TX 1 Channel table pointer */
+#define MAL0_TXCTP2R	(MAL_DCR_BASE + 0x22)	/* TX 2 Channel table pointer */
+#define MAL0_TXCTP3R	(MAL_DCR_BASE + 0x23)	/* TX 3 Channel table pointer */
+#define MAL0_RXCTP0R	(MAL_DCR_BASE + 0x40)	/* RX 0 Channel table pointer */
+#define MAL0_RXCTP1R	(MAL_DCR_BASE + 0x41)	/* RX 1 Channel table pointer */
+#define MAL0_RCBS0	(MAL_DCR_BASE + 0x60)	/* RX 0 Channel buffer size */
+#define MAL0_RCBS1	(MAL_DCR_BASE + 0x61)	/* RX 1 Channel buffer size */
+/*
+ *  SDR0 Bit Settings
+ */
+
+#define SDR0_DDR0			0x00E1
+#define SDR0_DDR0_DDRM_ENCODE(n)	((((u32)(n)) & 0x03) << 29)
+#define SDR0_DDR0_DDRM_DECODE(n)	((((u32)(n)) >> 29) & 0x03)
+#define SDR0_DDR0_TUNE_ENCODE(n)	((((u32)(n)) & 0x2FF) << 0)
+#define SDR0_DDR0_TUNE_DECODE(n)	((((u32)(n)) >> 0) & 0x2FF)
+
+#define SDR_SDSTP1_RL_DECODE(x) (((x) & 0x000C0000) >> 18)
+#define SDR_SDSTP1_RL_EBC       0x0
+#define SDR_SDSTP1_RL_NDFC      0x2
+
+/* ECID */
+#define SDR0_ECID0             0x0080
+#define SDR0_ECID1             0x0081
+#define SDR0_ECID2             0x0082
+#define SDR0_ECID3             0x0083
+
+/* AHB config. */
+#define AHB_TOP                 0xA4
+#define AHB_BOT                 0xA5
+#define SDR0_AHB_CFG            0x370
+
+/* DDR SDRAM Controller clock (CPR register)*/
+#define SDR0_DDRCE                     0x00E0	/* SDR register */
+#define CPR0_DDR2D                     0x0100	/* CPR register */
+#define CPR0_DDR2D_DDR2DV_ENCODE(n)    ((((u32)(n)) & 0x03) << 25)
+#define CPR0_DDR2D_DDR2DV_DECODE(n)    ((((u32)(n)) >> 25) & 0x03)
+
+#define SDR0_SDCS_SDD			(0x80000000 >> 31)
+
+#define SDR0_SRST0		SDR0_SRST	/* for compatability reasons */
+#define SDR0_SRST0_BGO		0x80000000	/* PLB to OPB bridge */
+#define SDR0_SRST0_PLB4		0x40000000	/* PLB4 arbiter */
+#define SDR0_SRST0_EBC		0x20000000	/* External bus controller */
+#define SDR0_SRST0_OPB		0x10000000	/* OPB arbiter */
+#define SDR0_SRST0_UART0	0x08000000	/* Universal async receiver/
+						   transmitter 0 */
+#define SDR0_SRST0_UART1	0x04000000	/* Universal async receiver/
+						   transmitter 1 */
+#define SDR0_SRST0_IIC0		0x02000000	/* Inter intgrated circuit 0 */
+#define SDR0_SRST0_IIC1		0x01000000	/* Inter intgrated circuit 1 */
+#define SDR0_SRST0_GPIO0	0x00800000	/* General purpose I/O 0 */
+#define SDR0_SRST0_GPT		0x00400000	/* General purpose timer */
+#define SDR0_SRST0_DMC		0x00200000	/* DDR SDRAM mem controller */
+#define SDR0_SRST0_PCI		0x00100000	/* PCI */
+#define SDR0_SRST0_CPM0		0x00020000	/* Clock and power mgmt */
+#define SDR0_SRST0_IMU		0x00010000	/* I2O DMA */
+#define SDR0_SRST0_UIC0		0x00008000	/* Universal intr ctrller 0 */
+#define SDR0_SRST0_UIC1		0x00004000	/* Universal intr ctrller 1 */
+#define SDR0_SRST0_SRAM		0x00002000	/* Universal intr ctrller 0 */
+#define SDR0_SRST0_UIC2		0x00001000	/* Universal intr ctrller 2 */
+#define SDR0_SRST0_UIC3		0x00000800	/* Universal intr ctrller 3 */
+#define SDR0_SRST0_OCM		0x00000400	/* Universal intr ctrller 0 */
+#define SDR0_SRST0_UART2	0x00000200	/* Universal asynchronous receiver/
+						   transmitter 2 */
+#define SDR0_SRST0_MAL		0x00000100	/* Media access layer */
+#define SDR0_SRST0_GPTR         0x00000040	/* General purpose timer */
+#define SDR0_SRST0_L2CACHE	0x00000004	/* L2 Cache */
+#define SDR0_SRST0_UART3	0x00000002	/* Universal asynchronous receiver/
+						   transmitter 3 */
+#define SDR0_SRST0_GPIO1	0x00000001	/* General purpose I/O 1 */
+
+#define SDR0_SRST1		0x201
+#define SDR0_SRST1_RLL		0x80000000	/* SRIO RLL */
+#define SDR0_SRST1_SCP		0x40000000	/* Serial communications port */
+#define SDR0_SRST1_PLBARB	0x20000000	/* PLB Arbiter */
+#define SDR0_SRST1_EIPPKP	0x10000000	/* EIPPPKP */
+#define SDR0_SRST1_EIP94	0x08000000	/* EIP 94 */
+#define SDR0_SRST1_EMAC0	0x04000000	/* Ethernet media access
+						   controller 0 */
+#define SDR0_SRST1_EMAC1	0x02000000	/* Ethernet media access
+						   controller 1 */
+#define SDR0_SRST1_EMAC2	0x01000000	/* Ethernet media access
+						   controller 2 */
+#define SDR0_SRST1_EMAC3	0x00800000	/* Ethernet media access
+						   controller 3 */
+#define SDR0_SRST1_ZMII		0x00400000	/* Ethernet ZMII/RMII/SMII */
+#define SDR0_SRST1_RGMII0	0x00200000	/* Ethernet RGMII/RTBI 0 */
+#define SDR0_SRST1_RGMII1	0x00100000	/* Ethernet RGMII/RTBI 1 */
+#define SDR0_SRST1_DMA4		0x00080000	/* DMA to PLB4 */
+#define SDR0_SRST1_DMA4CH	0x00040000	/* DMA Channel to PLB4 */
+#define SDR0_SRST1_SATAPHY	0x00020000	/* Serial ATA PHY */
+#define SDR0_SRST1_SRIODEV	0x00010000	/* Serial Rapid IO core, PCS,
+						   serdes */
+#define SDR0_SRST1_SRIOPCS	0x00008000	/* Serial Rapid PCS */
+#define SDR0_SRST1_NDFC		0x00004000	/* Nand flash controller */
+#define SDR0_SRST1_SRIOPLB	0x00002000	/* Serial Rapid IO PLB */
+#define SDR0_SRST1_ETHPLL	0x00001000	/* Ethernet PLL */
+#define SDR0_SRST1_TAHOE1	0x00000800	/* Ethernet Tahoe 1 */
+#define SDR0_SRST1_TAHOE0	0x00000400	/* Ethernet Tahoe 0 */
+#define SDR0_SRST1_SGMII0	0x00000200	/* Ethernet SGMII 0 */
+#define SDR0_SRST1_SGMII1	0x00000100	/* Ethernet SGMII 1 */
+#define SDR0_SRST1_SGMII2	0x00000080	/* Ethernet SGMII 2 */
+#define SDR0_SRST1_AHB		0x00000040	/* PLB4XAHB bridge */
+#define SDR0_SRST1_USBOTGPHY	0x00000020	/* USB 2.0 OTG PHY */
+#define SDR0_SRST1_USBOTG	0x00000010	/* USB 2.0 OTG controller */
+#define SDR0_SRST1_USBHOST	0x00000008	/* USB 2.0 Host controller */
+#define SDR0_SRST1_AHBDMAC	0x00000004	/* AHB DMA controller */
+#define SDR0_SRST1_AHBICM	0x00000002	/* AHB inter-connect matrix */
+#define SDR0_SRST1_SATA		0x00000001	/* Serial ATA controller */
+
+/*
+ *  Clocking
+ */
+#define PLLSYS0_ENG_MASK	0x80000000	/* 0 = SysClk, 1 = PLL VCO */
+#define PLLSYS0_SRC_MASK	0x40000000	/* 0 = PLL A, 1 = PLL B */
+#define PLLSYS0_SEL_MASK	0x38000000	/* 0 = PLL,1 = CPU,5=PerClk*/
+#define PLLSYS0_TUNE_MASK	0x07fe0000	/* PLL Tune bits */
+#define PLLSYS0_FB_DIV_MASK	0x0001f000	/* Feedback divisor */
+#define PLLSYS0_FWD_DIV_A_MASK	0x00000f00	/* Fwd Div A */
+#define PLLSYS0_FWD_DIV_B_MASK	0x000000e0	/* Fwd Div B */
+#define PLLSYS0_PRI_DIV_B_MASK	0x0000001c	/* PLL Primary Divisor B */
+#define PLLSYS0_OPB_DIV_MASK	0x00000003	/* OPB Divisor */
+
+#define PLLC_ENG_MASK       0x20000000	/* PLL primary forward divisor src */
+#define PLLC_SRC_MASK       0x20000000	/* PLL feedback source   */
+#define PLLD_FBDV_MASK      0x1f000000	/* PLL Feedback Divisor  */
+#define PLLD_FWDVA_MASK     0x000f0000	/* PLL Forward Divisor A */
+#define PLLD_FWDVB_MASK     0x00000700	/* PLL Forward Divisor B */
+#define PLLD_LFBDV_MASK     0x0000003f	/* PLL Local Feedback Divisor */
+
+#define OPBDDV_MASK         0x03000000	/* OPB Clock Divisor Register */
+#define PERDV_MASK          0x07000000	/* Periferal Clock Divisor */
+#define PRADV_MASK          0x07000000	/* Primary Divisor A */
+#define PRBDV_MASK          0x07000000	/* Primary Divisor B */
+#define SPCID_MASK          0x03000000	/* Sync PCI Divisor  */
+
+#define PLL_VCO_FREQ_MIN	500	/* Min VCO freq (MHz)       */
+#define PLL_VCO_FREQ_MAX	1000	/* Max VCO freq (MHz)       */
+#define PLL_CPU_FREQ_MAX	400	/* Max CPU freq (MHz)       */
+#define PLL_PLB_FREQ_MAX	133	/* Max PLB freq (MHz)       */
+
+/* Strap 1 Register */
+#define PLLSYS1_LF_DIV_MASK	0xfc000000	/* PLL Local Feedback Div */
+#define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
+#define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
+#define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
+#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Addres reset vector */
+#define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
+#define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
+#define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */
+#define PLLSYS1_PCWE_MASK	0x00008000	/* PCI local cpu wait enable */
+#define PLLSYS1_PPIM_MASK	0x00007800	/* PCI inbound map */
+#define PLLSYS1_PR64E_MASK	0x00000400	/* PCI init Req64 enable */
+#define PLLSYS1_PXFS_MASK	0x00000300	/* PCI-X Freq Sel */
+#define PLLSYS1_RSVD_MASK	0x00000080	/* RSVD */
+#define PLLSYS1_PDM_MASK	0x00000040	/* PCI-X Driver Mode */
+#define PLLSYS1_EPS_MASK	0x00000038	/* Ethernet Pin Select */
+#define PLLSYS1_RMII_MASK	0x00000004	/* RMII Mode */
+#define PLLSYS1_TRE_MASK	0x00000002	/* GPIO Trace Enable */
+#define PLLSYS1_NTO1_MASK	0x00000001	/* CPU:PLB N-to-1 ratio */
+
+#define PCIL0_VENDID		(PCIL0_CFGBASE + PCI_VENDOR_ID)
+#define PCIL0_DEVID		(PCIL0_CFGBASE + PCI_DEVICE_ID)
+#define PCIL0_CMD		(PCIL0_CFGBASE + PCI_COMMAND)
+#define PCIL0_STATUS		(PCIL0_CFGBASE + PCI_STATUS)
+#define PCIL0_REVID		(PCIL0_CFGBASE + PCI_REVISION_ID)
+#define PCIL0_CLS		(PCIL0_CFGBASE + PCI_CLASS_CODE)
+#define PCIL0_CACHELS		(PCIL0_CFGBASE + PCI_CACHE_LINE_SIZE)
+#define PCIL0_LATTIM		(PCIL0_CFGBASE + PCI_LATENCY_TIMER)
+#define PCIL0_HDTYPE		(PCIL0_CFGBASE + PCI_HEADER_TYPE)
+#define PCIL0_BIST		(PCIL0_CFGBASE + PCI_BIST)
+#define PCIL0_BAR0		(PCIL0_CFGBASE + PCI_BASE_ADDRESS_0)
+#define PCIL0_BAR1		(PCIL0_CFGBASE + PCI_BASE_ADDRESS_1)
+#define PCIL0_BAR2		(PCIL0_CFGBASE + PCI_BASE_ADDRESS_2)
+#define PCIL0_BAR3		(PCIL0_CFGBASE + PCI_BASE_ADDRESS_3)
+#define PCIL0_BAR4		(PCIL0_CFGBASE + PCI_BASE_ADDRESS_4)
+#define PCIL0_BAR5		(PCIL0_CFGBASE + PCI_BASE_ADDRESS_5)
+#define PCIL0_CISPTR		(PCIL0_CFGBASE + PCI_CARDBUS_CIS)
+#define PCIL0_SBSYSVID		(PCIL0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID)
+#define PCIL0_SBSYSID		(PCIL0_CFGBASE + PCI_SUBSYSTEM_ID)
+#define PCIL0_EROMBA		(PCIL0_CFGBASE + PCI_ROM_ADDRESS)
+#define PCIL0_CAP		(PCIL0_CFGBASE + PCI_CAPABILITY_LIST)
+#define PCIL0_RES0		(PCIL0_CFGBASE + 0x0035)
+#define PCIL0_RES1		(PCIL0_CFGBASE + 0x0036)
+#define PCIL0_RES2		(PCIL0_CFGBASE + 0x0038)
+#define PCIL0_INTLN		(PCIL0_CFGBASE + PCI_INTERRUPT_LINE)
+#define PCIL0_INTPN		(PCIL0_CFGBASE + PCI_INTERRUPT_PIN)
+#define SDR0_EMACxTXST_FUR	0x02000000	/* TX FIFO underrun */
+#define SDR0_EMACxTXST_BC	0x01000000	/* broadcase address */
+#define SDR0_EMACxTXST_MC	0x00800000	/* multicast address */
+#define SDR0_EMACxTXST_UC	0x00400000	/* unicast address */
+#define SDR0_EMACxTXST_FP	0x00200000	/* frame paused by ctrl pkt */
+#define SDR0_EMACxTXST_BFCS	0x00100000	/* bad FCS in the txmitted fr*/
+#define SDR0_EMACxTXST_CPF	0x00080000	/* TX control pause frame */
+#define SDR0_EMACxTXST_CF	0x00040000	/* TX control frame */
+#define SDR0_EMACxTXST_MSIZ	0x00020000	/* 1024-max bytes txmitted */
+#define SDR0_EMACxTXST_1023	0x00010000	/* 512-1023 bytes txmitted */
+#define SDR0_EMACxTXST_511	0x00008000	/* 256-511 bytes txmitted */
+#define SDR0_EMACxTXST_255	0x00004000	/* 128-255 bytes txmitted */
+#define SDR0_EMACxTXST_127	0x00002000	/* 65-127 bytes txmitted */
+#define SDR0_EMACxTXST_64	0x00001000	/* 64 bytes txmitted */
+#define SDR0_EMACxTXST_SQE	0x00000800	/* SQE indication */
+#define SDR0_EMACxTXST_LOC	0x00000400	/* loss of carrier sense */
+#define SDR0_EMACxTXST_IERR	0x00000080	/* EMAC internal error */
+#define SDR0_EMACxTXST_EDF	0x00000040	/* excessive deferral */
+#define SDR0_EMACxTXST_ECOL	0x00000020	/* excessive collisions */
+#define SDR0_EMACxTXST_LCOL	0x00000010	/* late collision */
+#define SDR0_EMACxTXST_DFFR	0x00000008	/* deferred frame */
+#define SDR0_EMACxTXST_MCOL	0x00000004	/* multiple collision frame */
+#define SDR0_EMACxTXST_SCOL	0x00000002	/* single collision frame */
+#define SDR0_EMACxTXST_TXOK	0x00000001	/* transmit OK */
+
+#define PCIL0_MINGNT		(PCIL0_CFGBASE + PCI_MIN_GNT)
+#define PCIL0_MAXLTNCY		(PCIL0_CFGBASE + PCI_MAX_LAT)
+
+#define PCIL0_BRDGOPT1		(PCIL0_CFGBASE + 0x0040)
+#define PCIL0_BRDGOPT2		(PCIL0_CFGBASE + 0x0044)
+
+#define PCIL0_POM0LAL		(PCIL0_CFGBASE + 0x0068)
+#define PCIL0_POM0LAH		(PCIL0_CFGBASE + 0x006c)
+#define PCIL0_POM0SA		(PCIL0_CFGBASE + 0x0070)
+#define PCIL0_POM0PCIAL		(PCIL0_CFGBASE + 0x0074)
+#define PCIL0_POM0PCIAH		(PCIL0_CFGBASE + 0x0078)
+#define PCIL0_POM1LAL		(PCIL0_CFGBASE + 0x007c)
+#define PCIL0_POM1LAH		(PCIL0_CFGBASE + 0x0080)
+#define PCIL0_POM1SA		(PCIL0_CFGBASE + 0x0084)
+#define PCIL0_POM1PCIAL		(PCIL0_CFGBASE + 0x0088)
+#define PCIL0_POM1PCIAH		(PCIL0_CFGBASE + 0x008c)
+#define PCIL0_POM2SA		(PCIL0_CFGBASE + 0x0090)
+
+#define PCIL0_PIM0SA		(PCIL0_CFGBASE + 0x0098)
+#define PCIL0_PIM0LAL		(PCIL0_CFGBASE + 0x009c)
+#define PCIL0_PIM0LAH		(PCIL0_CFGBASE + 0x00a0)
+#define PCIL0_PIM1SA		(PCIL0_CFGBASE + 0x00a4)
+#define PCIL0_PIM1LAL		(PCIL0_CFGBASE + 0x00a8)
+#define PCIL0_PIM1LAH		(PCIL0_CFGBASE + 0x00ac)
+#define PCIL0_PIM2SA		(PCIL0_CFGBASE + 0x00b0)
+#define PCIL0_PIM2LAL		(PCIL0_CFGBASE + 0x00b4)
+#define PCIL0_PIM2LAH		(PCIL0_CFGBASE + 0x00b8)
+
+#define PCIL0_STS		(PCIL0_CFGBASE + 0x00e0)
+
+/*****************************************************************************
+ * GPIO macro register define
+ *****************************************************************************/
+
+#define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE+0x00000B00)
+
+#define GPIO0_OR		(GPIO0_BASE+0x0)
+#define GPIO0_TCR		(GPIO0_BASE+0x4)
+#define GPIO0_OSRL		(GPIO0_BASE+0x8)
+#define GPIO0_OSRH		(GPIO0_BASE+0xC)
+#define GPIO0_TSRL		(GPIO0_BASE+0x10)
+#define GPIO0_TSRH		(GPIO0_BASE+0x14)
+#define GPIO0_ODR		(GPIO0_BASE+0x18)
+#define GPIO0_IR		(GPIO0_BASE+0x1C)
+#define GPIO0_RR1		(GPIO0_BASE+0x20)
+#define GPIO0_RR2		(GPIO0_BASE+0x24)
+#define GPIO0_RR3		(GPIO0_BASE+0x28)
+#define GPIO0_ISR1L		(GPIO0_BASE+0x30)
+#define GPIO0_ISR1H		(GPIO0_BASE+0x34)
+#define GPIO0_ISR2L		(GPIO0_BASE+0x38)
+#define GPIO0_ISR2H		(GPIO0_BASE+0x3C)
+#define GPIO0_ISR3L		(GPIO0_BASE+0x40)
+#define GPIO0_ISR3H		(GPIO0_BASE+0x44)
+
+#define GPIO1_OR		(GPIO1_BASE+0x0)
+#define GPIO1_TCR		(GPIO1_BASE+0x4)
+#define GPIO1_OSRL		(GPIO1_BASE+0x8)
+#define GPIO1_OSRH		(GPIO1_BASE+0xC)
+#define GPIO1_TSRL		(GPIO1_BASE+0x10)
+#define GPIO1_TSRH		(GPIO1_BASE+0x14)
+#define GPIO1_ODR		(GPIO1_BASE+0x18)
+#define GPIO1_IR		(GPIO1_BASE+0x1C)
+#define GPIO1_RR1		(GPIO1_BASE+0x20)
+#define GPIO1_RR2		(GPIO1_BASE+0x24)
+#define GPIO1_RR3		(GPIO1_BASE+0x28)
+#define GPIO1_ISR1L		(GPIO1_BASE+0x30)
+#define GPIO1_ISR1H		(GPIO1_BASE+0x34)
+#define GPIO1_ISR2L		(GPIO1_BASE+0x38)
+#define GPIO1_ISR2H		(GPIO1_BASE+0x3C)
+#define GPIO1_ISR3L		(GPIO1_BASE+0x40)
+#define GPIO1_ISR3H		(GPIO1_BASE+0x44)
+
+#endif /* __APM821XX_H__ */
diff --git a/include/ppc4xx.h b/include/ppc4xx.h
index ee30a4c..06230bd 100644
--- a/include/ppc4xx.h
+++ b/include/ppc4xx.h
@@ -44,14 +44,15 @@
 #if defined(CONFIG_405EX) || \
     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_460SX)
+    defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
 #define CONFIG_SDRAM_PPC4xx_IBM_DDR2	/* IBM DDR(2) controller */
 #endif
 
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) ||	\
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) ||	\
     defined(CONFIG_405EZ) || defined(CONFIG_405EX) ||	\
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_APM821XX)
 #define CONFIG_NAND_NDFC
 #endif
 
@@ -61,7 +62,7 @@
     defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)  || \
-    defined(CONFIG_460SX)
+    defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
 
 #define PLB_ARBITER_BASE		0x80
 
@@ -99,7 +100,9 @@
 
 #endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/
 
-#if defined(CONFIG_440)
+#if defined(CONFIG_APM821XX)
+#include <apm821xx.h>
+#elif defined(CONFIG_440)
 #include <ppc440.h>
 #else
 #include <ppc405.h>
-- 
1.6.1.rc3

^ permalink raw reply related	[flat|nested] 7+ messages in thread
* [U-Boot] [PATCH v3 1/2] APM821xx: Add CPU support
  2010-09-08  2:06 [U-Boot] [PATCH v3 1/2] APM821xx: Add CPU support tmarri at apm.com
@ 2010-09-09 14:45 ` Stefan Roese
  2010-09-09 14:53   ` Wolfgang Denk
  0 siblings, 1 reply; 7+ messages in thread
From: Stefan Roese @ 2010-09-09 14:45 UTC (permalink / raw)
  To: u-boot

Hi Marri,

On Wednesday 08 September 2010 04:06:21 tmarri at apm.com wrote:
> From: Tirumala Marri <tmarri@apm.com>
> 
> APM821XX is a new line of SoCs which are derivatives of
> PPC44X family of processors. This patch adds support of CPU, cache,
> tlb, 32k ocm, bootstraps, PLB and AHB bus.

Look mostly good. One comment though below.
 
> Signed-off-by: Tirumala R Marri <tmarri@apm.com>
> ---
> V2:
>   * Removed Defines added to 405ex.
> V3:
>   * Change APM82XXX to APM821XX
>   * Modify the way cpu id is printed.
>   * Correct inadvertent change.
>   * Sort define list.
>   * Remove comment for get_sys_info().
>   * Define a symbolic constat ISRAM1_OCM_SIZE.
>   * Create apm821xx.h instead of using ppc440.h
>   * Correct multiline comment.
> ---
>  arch/powerpc/cpu/ppc4xx/cpu.c           |   36 ++-
>  arch/powerpc/cpu/ppc4xx/cpu_init.c      |    5 +-
>  arch/powerpc/cpu/ppc4xx/speed.c         |   76 +++++-
>  arch/powerpc/cpu/ppc4xx/start.S         |   11 +-
>  arch/powerpc/cpu/ppc4xx/tlb.c           |    2 +
>  arch/powerpc/include/asm/ppc4xx-ebc.h   |    4 +
>  arch/powerpc/include/asm/ppc4xx-isram.h |   14 +-
>  arch/powerpc/include/asm/ppc4xx-sdram.h |   12 +-
>  arch/powerpc/include/asm/ppc4xx-uic.h   |    5 +-
>  arch/powerpc/include/asm/processor.h    |    1 +
>  include/apm821xx.h                      |  493 +++++++++++++++++++++++++++++++

I know that Wolfgang specifically asked you to add this file for this
"new" SoC. But I'm not so sure if this is the right way. Most of the
defines in this new file are a plain copy from include/ppc440.h.

Wolfgang, do you really think this is better than adding support for
this SoC into ppc440.h? After all, the CPU core of this SoC is still
a PPC4xx PowerPC.

Cheers,
Stefan

--
DENX Software Engineering GmbH,      MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de

^ permalink raw reply	[flat|nested] 7+ messages in thread
* [U-Boot] [PATCH v3 1/2] APM821xx: Add CPU support
  2010-09-09 14:45 ` Stefan Roese
@ 2010-09-09 14:53   ` Wolfgang Denk
  2010-09-09 16:43     ` Tirumala Marri
  0 siblings, 1 reply; 7+ messages in thread
From: Wolfgang Denk @ 2010-09-09 14:53 UTC (permalink / raw)
  To: u-boot

Dear Stefan Roese,

In message <201009091645.16076.sr@denx.de> you wrote:
>
> >  include/apm821xx.h                      |  493 +++++++++++++++++++++++++++++++
> 
> I know that Wolfgang specifically asked you to add this file for this
> "new" SoC. But I'm not so sure if this is the right way. Most of the
> defines in this new file are a plain copy from include/ppc440.h.
> 
> Wolfgang, do you really think this is better than adding support for
> this SoC into ppc440.h? After all, the CPU core of this SoC is still
> a PPC4xx PowerPC.

It makes no sense to duplicate common parts. Only different code
should be moved to separate files.

Viele Gr??e,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
When in doubt, mumble;   when in trouble, delegate;  when in  charge,
ponder.                                             -- James H. Boren

^ permalink raw reply	[flat|nested] 7+ messages in thread
* [U-Boot] [PATCH v3 1/2] APM821xx: Add CPU support
  2010-09-09 14:53   ` Wolfgang Denk
@ 2010-09-09 16:43     ` Tirumala Marri
  2010-09-09 17:39       ` Stefan Roese
  0 siblings, 1 reply; 7+ messages in thread
From: Tirumala Marri @ 2010-09-09 16:43 UTC (permalink / raw)
  To: u-boot

> > >  include/apm821xx.h                      |  493
> +++++++++++++++++++++++++++++++
> >
> > I know that Wolfgang specifically asked you to add this file for this
> > "new" SoC. But I'm not so sure if this is the right way. Most of the
> > defines in this new file are a plain copy from include/ppc440.h.
> >
> > Wolfgang, do you really think this is better than adding support for
> > this SoC into ppc440.h? After all, the CPU core of this SoC is still
> > a PPC4xx PowerPC.
>
> It makes no sense to duplicate common parts. Only different code
> should be moved to separate files.
>
[Marri] It is only few lines of code is different. Any way I will make a
change and
Send it.
Regards,
Marri

^ permalink raw reply	[flat|nested] 7+ messages in thread
* [U-Boot] [PATCH v3 1/2] APM821xx: Add CPU support
  2010-09-09 16:43     ` Tirumala Marri
@ 2010-09-09 17:39       ` Stefan Roese
  2010-09-09 17:41         ` Tirumala Marri
  2010-09-09 18:01         ` Feng Kan
  0 siblings, 2 replies; 7+ messages in thread
From: Stefan Roese @ 2010-09-09 17:39 UTC (permalink / raw)
  To: u-boot

Hi Marri,

On Thursday 09 September 2010 18:43:31 Tirumala Marri wrote:
> > It makes no sense to duplicate common parts. Only different code
> > should be moved to separate files.
> 
> [Marri] It is only few lines of code is different. Any way I will make a
> change and Send it.

Please wait a day or two. I have an idea on how to best cleanup this PPC4xx 
header mess and will post some patches for it soon. It would be best if you 
could rebase your work on those patches then (if we find a consensus here).

Cheers,
Stefan

--
DENX Software Engineering GmbH,      MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de

^ permalink raw reply	[flat|nested] 7+ messages in thread
* [U-Boot] [PATCH v3 1/2] APM821xx: Add CPU support
  2010-09-09 17:39       ` Stefan Roese
@ 2010-09-09 17:41         ` Tirumala Marri
  2010-09-09 18:01         ` Feng Kan
  1 sibling, 0 replies; 7+ messages in thread
From: Tirumala Marri @ 2010-09-09 17:41 UTC (permalink / raw)
  To: u-boot

Stefan,
>
> Please wait a day or two. I have an idea on how to best cleanup this
> PPC4xx
> header mess and will post some patches for it soon. It would be best if
> you
> could rebase your work on those patches then (if we find a consensus
> here).

  Sure I will wait for your changes.

Regards,
Marri

^ permalink raw reply	[flat|nested] 7+ messages in thread
* [U-Boot] [PATCH v3 1/2] APM821xx: Add CPU support
  2010-09-09 17:39       ` Stefan Roese
  2010-09-09 17:41         ` Tirumala Marri
@ 2010-09-09 18:01         ` Feng Kan
  1 sibling, 0 replies; 7+ messages in thread
From: Feng Kan @ 2010-09-09 18:01 UTC (permalink / raw)
  To: u-boot

On Thu, Sep 9, 2010 at 10:39 AM, Stefan Roese <sr@denx.de> wrote:
> Hi Marri,
>
> On Thursday 09 September 2010 18:43:31 Tirumala Marri wrote:
>> > It makes no sense to duplicate common parts. Only different code
>> > should be moved to separate files.
>>
>> [Marri] It is only few lines of code is different. Any way I will make a
>> change and Send it.
>
> Please wait a day or two. I have an idea on how to best cleanup this PPC4xx
> header mess and will post some patches for it soon. It would be best if you
> could rebase your work on those patches then (if we find a consensus here).
>

Hi Stefan, just a heads up. There are number of processors coming down the
pipeline. All with the apm8Xxxx convention. The X is processor family and the
later xxx are SoC specializations.

> Cheers,
> Stefan
>
> --
> DENX Software Engineering GmbH, ? ? ?MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, ?Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>

^ permalink raw reply	[flat|nested] 7+ messages in thread
end of thread, other threads:[~2010-09-09 18:01 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2010-09-08  2:06 [U-Boot] [PATCH v3 1/2] APM821xx: Add CPU support tmarri at apm.com
2010-09-09 14:45 ` Stefan Roese
2010-09-09 14:53   ` Wolfgang Denk
2010-09-09 16:43     ` Tirumala Marri
2010-09-09 17:39       ` Stefan Roese
2010-09-09 17:41         ` Tirumala Marri
2010-09-09 18:01         ` Feng Kan

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