[U-Boot] [PATCH] ppc4xx: Add CATCenter Io 405EP board support

[U-Boot] [PATCH] ppc4xx: Add CATCenter Io 405EP board support

[Dirk Eibach]

Board support for the Guntermann & Drunck CATCenter Io.

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
---
 MAKEALL                  |    1 +
 Makefile                 |    3 +
 board/gdsys/io/Makefile  |   51 ++++++++++
 board/gdsys/io/config.mk |   24 +++++
 board/gdsys/io/io.c      |  231 ++++++++++++++++++++++++++++++++++++++++++
 include/configs/io.h     |  251 ++++++++++++++++++++++++++++++++++++++++++++++
 6 files changed, 561 insertions(+), 0 deletions(-)
 create mode 100644 board/gdsys/io/Makefile
 create mode 100644 board/gdsys/io/config.mk
 create mode 100644 board/gdsys/io/io.c
 create mode 100644 include/configs/io.h

diff --git a/MAKEALL b/MAKEALL
index 1b506d6..37aeed4 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -156,6 +156,7 @@ LIST_4xx="$(boards_by_cpu ppc4xx)
 	haleakala_nand	\
 	hcu4		\
 	hcu5		\
+	io		\
 	intip		\
 	kilauea		\
 	kilauea_nand	\
diff --git a/Makefile b/Makefile
index 8df60fa..86f9efa 100644
--- a/Makefile
+++ b/Makefile
@@ -1004,6 +1004,9 @@ mcu25_config:  unconfig
 	@mkdir -p $(obj)board/netstal/common
 	@$(MKCONFIG) $@ powerpc ppc4xx $(call lcname,$@) netstal
 
+io_config: unconfig
+	@$(MKCONFIG) $(@:_config=) powerpc ppc4xx io gdsys
+
 # Kilauea & Haleakala images are identical (recognized via PVR)
 kilauea_config \
 haleakala_config: unconfig
diff --git a/board/gdsys/io/Makefile b/board/gdsys/io/Makefile
new file mode 100644
index 0000000..1270fea
--- /dev/null
+++ b/board/gdsys/io/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o
+SOBJS   =
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/gdsys/io/config.mk b/board/gdsys/io/config.mk
new file mode 100644
index 0000000..1bdf5e4
--- /dev/null
+++ b/board/gdsys/io/config.mk
@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFFFC0000
diff --git a/board/gdsys/io/io.c b/board/gdsys/io/io.c
new file mode 100644
index 0000000..4247806
--- /dev/null
+++ b/board/gdsys/io/io.c
@@ -0,0 +1,231 @@
+/*
+ * (C) Copyright 2009
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach at gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+#include <miiphy.h>
+
+#define GBIT_PHY_NAME "iophy"
+
+#define REFLECTION_TESTPATTERN 0xdede
+#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
+
+enum {
+	REG_REFELECTION_LOW = 0x0000,
+	REG_VERSIONS = 0x0002,
+	REG_FPGA_FEATURES = 0x0004,
+	REG_FPGA_VERSION = 0x0006,
+	REG_QUAD_SERDES_RESET = 0x0012,
+	REG_REFELECTION_HIGH = 0x3ffe,
+};
+
+enum {
+	UNITTYPE_CCD_SWITCH = 1,
+};
+
+enum {
+	HWVER_100 = 0,
+	HWVER_110 = 1,
+	HWVER_121 = 2,
+	HWVER_122 = 3,
+};
+
+static u16 fpga_get_reg(unsigned reg)
+{
+	return in_le16((void *)(CONFIG_SYS_FPGA_BASE + reg));
+}
+
+static void fpga_set_reg(unsigned reg, u16 val)
+{
+	return out_le16((void *)(CONFIG_SYS_FPGA_BASE + reg), val);
+}
+
+int configure_gbit_phy(unsigned char addr)
+{
+	unsigned short value;
+
+	if (miiphy_write(GBIT_PHY_NAME, addr, 0x16, 0x0002))
+		goto err_out;
+	if (miiphy_write(GBIT_PHY_NAME, addr, 0x1a, 0x800a))
+		goto err_out;
+	if (miiphy_write(GBIT_PHY_NAME, addr, 0x16, 0x0000))
+		goto err_out;
+	if (miiphy_read(GBIT_PHY_NAME, addr, 0x10, &value))
+		goto err_out;
+	if (miiphy_write(GBIT_PHY_NAME, addr, 0x10, value & ~0x0004))
+		goto err_out;
+	if (miiphy_write(GBIT_PHY_NAME, addr, 0x00, 0x9140))
+		goto err_out;
+
+	return 0;
+
+err_out:
+	printf("Error writing to the PHY addr=%02x\n", addr);
+	return -1;
+}
+
+int board_early_init_f(void)
+{
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);	/* set all to be non-critical */
+	mtdcr(UIC0PR, 0xFFFFFF80);	/* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest prio */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks
+	 * -> ca. 15 us
+	 */
+	mtebc(EBC0_CFG, 0xa8400000);	/* ebc always driven */
+
+	/*
+	 * setup io-latches
+	 */
+	out_le16((void *)CONFIG_SYS_LATCH_BASE, 0xffff);
+	out_le16((void *)(CONFIG_SYS_LATCH_BASE + 0x100), 0xffbf);
+
+	/*
+	 * set "startup-finished"-gpios
+	 */
+	gpio_write_bit(21, 0);
+	gpio_write_bit(22, 1);
+
+	/*
+	 * wait for fpga-done
+	 */
+	while (!(in_le16((void *)(CONFIG_SYS_LATCH_BASE + 0x200)) & 0x0010));
+
+	/*
+	 * stop reset peripherals
+	 */
+	udelay(10);
+	out_le16((void *)(CONFIG_SYS_LATCH_BASE + 0x100), 0xffff);
+
+	/*
+	 * wait for fpga out of reset
+	 */
+	while (1) {
+		fpga_set_reg(REG_REFELECTION_LOW, REFLECTION_TESTPATTERN);
+		if (fpga_get_reg(REG_REFELECTION_HIGH) ==
+			REFLECTION_TESTPATTERN_INV)
+			break;
+	}
+
+	return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+	u16 versions = fpga_get_reg(REG_VERSIONS);
+	u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
+	u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
+	unsigned unit_type = (versions & 0xf000) >> 12;
+	unsigned hardware_version = versions & 0x000f;
+	unsigned feature_channels = fpga_features & 0x007f;
+	unsigned feature_expansion = fpga_features & (1<<15);
+
+	printf("Board: ");
+
+	printf("CATCenter Io");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	puts("\n       ");
+
+	switch (unit_type) {
+	case UNITTYPE_CCD_SWITCH:
+		printf("CCD-Switch");
+		break;
+
+	default:
+		printf("UnitType %d(not supported)", unit_type);
+		break;
+	}
+
+	switch (hardware_version) {
+	case HWVER_100:
+		printf(" HW-Ver 1.00\n");
+		break;
+
+	case HWVER_110:
+		printf(" HW-Ver 1.10\n");
+		break;
+
+	case HWVER_121:
+		printf(" HW-Ver 1.21\n");
+		break;
+
+	case HWVER_122:
+		printf(" HW-Ver 1.22\n");
+		break;
+
+	default:
+		printf(" HW-Ver %d(not supported)\n",
+		       hardware_version);
+		break;
+	}
+
+	printf("       FPGA V %d.%02d, features:",
+		fpga_version / 100, fpga_version % 100);
+
+	printf(" %d channel(s)", feature_channels);
+
+	printf(", expansion %ssupported", feature_expansion ? "" : "un");
+
+	puts("\n");
+
+	return 0;
+}
+
+/*
+ * setup Gbit PHYs
+ */
+int last_stage_init(void)
+{
+	unsigned int k;
+
+	miiphy_register(GBIT_PHY_NAME, bb_miiphy_read, bb_miiphy_write);
+
+	out_le16((void *)(CONFIG_SYS_LATCH_BASE + 0x100), 0xffdf);
+
+	for (k = 0; k < 32; ++k)
+		configure_gbit_phy(k);
+
+	out_le16((void *)(CONFIG_SYS_LATCH_BASE + 0x100), 0xffcf);
+
+	fpga_set_reg(REG_QUAD_SERDES_RESET, 0);
+
+	return 0;
+}
diff --git a/include/configs/io.h b/include/configs/io.h
new file mode 100644
index 0000000..53dce7d
--- /dev/null
+++ b/include/configs/io.h
@@ -0,0 +1,251 @@
+/*
+ * (C) Copyright 2009
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_405EP		1	/* this is a PPC405 CPU */
+#define CONFIG_4xx		1	/*  member of PPC4xx family */
+#define CONFIG_IO	        1	/*  on a Io board */
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		io
+#define CONFIG_IDENT_STRING	" io 0.04"
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F	/* call board_early_init_f */
+#define CONFIG_LAST_STAGE_INIT		/* call last_stage_init */
+
+#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll   */
+
+/*
+ * Configure PLL
+ */
+#define PLLMR0_DEFAULT PLLMR0_266_133_66
+#define PLLMR1_DEFAULT PLLMR1_266_133_66
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+#define CONFIG_ENV_IS_IN_FLASH	/* use FLASH for environment vars */
+
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=fc000000\0"					\
+	"fdt_addr=fc1e0000\0"						\
+	"ramdisk_addr=fc200000\0"					\
+	""
+
+#define CONFIG_PHY_ADDR		4	/* PHY address			*/
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY1_ADDR	0xc	/* EMAC1 PHY address		*/
+#define CONFIG_PHY_CLK_FREQ    EMAC_STACR_CLK_66MHZ
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CACHE
+#undef CONFIG_CMD_EEPROM
+
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */
+
+/* SDRAM timings used in datasheet */
+#define CONFIG_SYS_SDRAM_CL             3	/* CAS latency */
+#define CONFIG_SYS_SDRAM_tRP           20	/* PRECHARGE command period */
+#define CONFIG_SYS_SDRAM_tRC           66	/* ACTIVE-to-ACTIVE period */
+#define CONFIG_SYS_SDRAM_tRCD          20	/* ACTIVE-to-READ delay */
+#define CONFIG_SYS_SDRAM_tRFC          66	/* Auto refresh period */
+
+/*
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
+ * The Linux BASE_BAUD define should match this configuration.
+ *    baseBaud = cpuClock/(uartDivisor*16)
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* external serial clock */
+#undef  CONFIG_SYS_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD		691200
+
+/*
+ * I2C stuff
+ */
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address*/
+
+/* Temp sensor/hwmon/dtt */
+#define CONFIG_DTT_LM63		1	/* National LM63	*/
+#define CONFIG_DTT_SENSORS	{ 0 }	/* Sensor addresses	*/
+#define CONFIG_DTT_PWM_LOOKUPTABLE	\
+		{ { 40, 10 }, { 50, 20 }, { 60, 40 } }
+#define CONFIG_DTT_TACH_LIMIT	0xa10
+
+/*
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible	*/
+#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
+
+#define CONFIG_SYS_FLASH_BASE		0xFC000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sectors per chip*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase/ms */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write/ms */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buff'd writes */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protect */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* no warn upon unknown flash */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector */
+#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif
+
+/* Gbit PHYs */
+#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
+
+#define CONFIG_SYS_MDIO_PIN  (0x80000000 >> 13)	 /* our MDIO is GPIO0 */
+#define CONFIG_SYS_MDC_PIN   (0x80000000 >> 7)	 /* our MDC  is GPIO7  */
+
+#define MDIO_ACTIVE	out32(GPIO0_TCR, in32(GPIO0_TCR) | CONFIG_SYS_MDIO_PIN)
+#define MDIO_TRISTATE	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_MDIO_PIN)
+#define MDIO_READ	((in32(GPIO0_IR) & CONFIG_SYS_MDIO_PIN) != 0)
+
+#define MDIO(bit)	if(bit) out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_MDIO_PIN); \
+			else	out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_MDIO_PIN)
+
+#define MDC(bit)	if(bit) out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_MDC_PIN); \
+			else	out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_MDC_PIN)
+
+#define MIIDELAY	udelay(1)
+
+
+/*
+ * PPC405 GPIO Configuration
+ */
+#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO	Alternate1	*/ \
+{ \
+/* GPIO Core 0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO0	PerBLast */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1	TS1E */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2	TS2E */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3	TS1O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4	TS2O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5	TS3 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6	TS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO7	TS5 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8	TS6 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9	TrcClk */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10	PerCS1 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11	PerCS2 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12	PerCS3 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO13	PerCS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14	PerAddr03 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15	PerAddr04 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16	PerAddr05 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17	IRQ0 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18	IRQ1 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19	IRQ2 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20	IRQ3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21	IRQ4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22	IRQ5 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23	IRQ6 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24	UART0_DCD */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25	UART0_DSR */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26	UART0_RI */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27	UART0_DTR */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28	UART1_Rx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29	UART1_Tx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30	RejectPkt0 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31	RejectPkt1 */ \
+} \
+}
+
+/*
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM        1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
+
+#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size/bytes res'd for init data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CONFIG_SYS_EBC_PB0AP		0xa382a880
+/* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0CR		0xFC0DA000
+
+/* Memory Bank 1 (NVRAM) initializatio */
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+/* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit  */
+#define CONFIG_SYS_EBC_PB1CR		0x7f318000
+
+/* Memory Bank 2 (FPGA) initialization */
+#define CONFIG_SYS_FPGA_BASE		0x7f100000
+#define CONFIG_SYS_EBC_PB2AP		0x02025080
+/* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB2CR		0x7f11a000
+
+/* Memory Bank 3 (Latches) initialization */
+#define CONFIG_SYS_LATCH_BASE		0x7f200000
+#define CONFIG_SYS_EBC_PB3AP		0xa2015480
+/* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB3CR		0x7f21a000
+
+#endif	/* __CONFIG_H */
-- 
1.5.6.5

[U-Boot] [PATCH] ppc4xx: Add CATCenter Io 405EP board support

[Wolfgang Denk]

Dear Dirk Eibach,

In message <1286890387-11491-1-git-send-email-eibach@gdsys.de> you wrote:
> Board support for the Guntermann & Drunck CATCenter Io.
> 
> Signed-off-by: Dirk Eibach <eibach@gdsys.de>
> ---
>  MAKEALL                  |    1 +
>  Makefile                 |    3 +
>  board/gdsys/io/Makefile  |   51 ++++++++++
>  board/gdsys/io/config.mk |   24 +++++
>  board/gdsys/io/io.c      |  231 ++++++++++++++++++++++++++++++++++++++++++
>  include/configs/io.h     |  251 ++++++++++++++++++++++++++++++++++++++++++++++
>  6 files changed, 561 insertions(+), 0 deletions(-)
>  create mode 100644 board/gdsys/io/Makefile
>  create mode 100644 board/gdsys/io/config.mk
>  create mode 100644 board/gdsys/io/io.c
>  create mode 100644 include/configs/io.h

Entry to MAINTAINERS missing.

> diff --git a/MAKEALL b/MAKEALL
> index 1b506d6..37aeed4 100755
> --- a/MAKEALL
> +++ b/MAKEALL
> @@ -156,6 +156,7 @@ LIST_4xx="$(boards_by_cpu ppc4xx)
>  	haleakala_nand	\
>  	hcu4		\
>  	hcu5		\
> +	io		\
>  	intip		\
>  	kilauea		\
>  	kilauea_nand	\

Please keep lists sorted.

> diff --git a/Makefile b/Makefile
> index 8df60fa..86f9efa 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -1004,6 +1004,9 @@ mcu25_config:  unconfig
>  	@mkdir -p $(obj)board/netstal/common
>  	@$(MKCONFIG) $@ powerpc ppc4xx $(call lcname,$@) netstal
>  
> +io_config: unconfig
> +	@$(MKCONFIG) $(@:_config=) powerpc ppc4xx io gdsys
> +

NAK. We don't accept entries to Makefile any more. Please add your
board description to boards.cfg instead.

And remember to keep lists sorted.

> +int configure_gbit_phy(unsigned char addr)
> +{
> +	unsigned short value;
> +
> +	if (miiphy_write(GBIT_PHY_NAME, addr, 0x16, 0x0002))
> +		goto err_out;
> +	if (miiphy_write(GBIT_PHY_NAME, addr, 0x1a, 0x800a))
> +		goto err_out;
> +	if (miiphy_write(GBIT_PHY_NAME, addr, 0x16, 0x0000))
> +		goto err_out;
> +	if (miiphy_read(GBIT_PHY_NAME, addr, 0x10, &value))
> +		goto err_out;
> +	if (miiphy_write(GBIT_PHY_NAME, addr, 0x10, value & ~0x0004))
> +		goto err_out;
> +	if (miiphy_write(GBIT_PHY_NAME, addr, 0x00, 0x9140))
> +		goto err_out;

You might want to replace all these magic constants with some
#defines, and add some comments what you're actually doing.

> +	while (!(in_le16((void *)(CONFIG_SYS_LATCH_BASE + 0x200)) & 0x0010));

Semicolon onnew line, please.

> +	/*
> +	 * wait for fpga out of reset
> +	 */
> +	while (1) {
> +		fpga_set_reg(REG_REFELECTION_LOW, REFLECTION_TESTPATTERN);
> +		if (fpga_get_reg(REG_REFELECTION_HIGH) ==
> +			REFLECTION_TESTPATTERN_INV)
> +			break;
> +	}

What happens if this loop does not terminate? Maybe a timeout and
error message would be helpful?

> +	char *s = getenv("serial#");
> +	u16 versions = fpga_get_reg(REG_VERSIONS);
> +	u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
> +	u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
> +	unsigned unit_type = (versions & 0xf000) >> 12;
> +	unsigned hardware_version = versions & 0x000f;
> +	unsigned feature_channels = fpga_features & 0x007f;
> +	unsigned feature_expansion = fpga_features & (1<<15);

Please separate declarations and code.  A few initializations may be
ok, but this is unreadable.

> +	printf(", expansion %ssupported", feature_expansion ? "" : "un");
> +
> +	puts("\n");

Why not include the newline in the printf() format string ?

> diff --git a/include/configs/io.h b/include/configs/io.h
> new file mode 100644
> index 0000000..53dce7d
> --- /dev/null
> +++ b/include/configs/io.h
> @@ -0,0 +1,251 @@
> +/*
> + * (C) Copyright 2009
> + * Dirk Eibach,  Guntermann & Drunck GmbH, eibach at gdsys.de

2009?

+
> +#define CONFIG_PHY_ADDR		4	/* PHY address			*/
> +#define CONFIG_HAS_ETH0
> +#define CONFIG_HAS_ETH1
> +#define CONFIG_PHY1_ADDR	0xc	/* EMAC1 PHY address		*/
> +#define CONFIG_PHY_CLK_FREQ    EMAC_STACR_CLK_66MHZ

Please use TABs for vertical alignment.

> +/*
> + * I2C stuff
> + */
> +#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address*/

Comment wrong? I don't see a slave address here.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Unix is like a toll road on which you have to stop every 50  feet  to
pay another nickel. But hey! You only feel 5 cents poorer each time.
                 - Larry Wall in <1992Aug13.192357.15731@netlabs.com>

[U-Boot] [PATCH] ppc4xx: Add CATCenter Io 405EP board support

[Stefan Roese]

Hi Dirk,

On Tuesday 12 October 2010 15:33:07 Dirk Eibach wrote:
> Board support for the Guntermann & Drunck CATCenter Io.

Apart from Wolfgangs comments, some more from myself below.
 
> diff --git a/include/configs/io.h b/include/configs/io.h
> new file mode 100644
> index 0000000..53dce7d
> --- /dev/null
> +++ b/include/configs/io.h

<snip>

> +/* Gbit PHYs */
> +#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
> +
> +#define CONFIG_SYS_MDIO_PIN  (0x80000000 >> 13)	 /* our MDIO is GPIO0 
*/
> +#define CONFIG_SYS_MDC_PIN   (0x80000000 >> 7)	 /* our MDC  is GPIO7  
*/
> +
> +#define MDIO_ACTIVE	out32(GPIO0_TCR, in32(GPIO0_TCR) |
> CONFIG_SYS_MDIO_PIN)

Use out_be32() accessors here and below.

Please fix and resubmit. Thanks.

Cheers,
Stefan

--
DENX Software Engineering GmbH,      MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de

[U-Boot] [PATCH] ppc4xx: Add CATCenter Io 405EP board support

[Eibach, Dirk]

> Hi Dirk,

Hi Stefan,

> ...
> <snip>
> 
> > +/* Gbit PHYs */
> > +#define CONFIG_BITBANGMII		/* bit-bang MII PHY 
> management	*/
> > +
> > +#define CONFIG_SYS_MDIO_PIN  (0x80000000 >> 13)	 /* our 
> MDIO is GPIO0 
> */
> > +#define CONFIG_SYS_MDC_PIN   (0x80000000 >> 7)	 /* our 
> MDC  is GPIO7  
> */
> > +
> > +#define MDIO_ACTIVE	out32(GPIO0_TCR, in32(GPIO0_TCR) |
> > CONFIG_SYS_MDIO_PIN)
> 
> Use out_be32() accessors here and below.

Just being curious: why? Has in32() also to be replaced?

> Please fix and resubmit. Thanks.

OK.
 
> Cheers,
> Stefan

Cheers
Dirk
--------------------------------------------------------------------------
Guntermann & Drunck GmbH Systementwicklung 
Dortmunder Str. 4a 
D-57234 Wilnsdorf - Germany 
Tel: +49 (0) 27 39 / 89 01 - 100  Fax: +49 (0) 27 39 / 89 01 - 120 
E-Mail: mailto:sales at gdsys.de Web: www.gdsys.de
--------------------------------------------------------------------------
Geschaeftsfuehrer: 
Udo Guntermann - Martin Drunck - Reiner Ruelmann - Klaus Tocke
HRB 2884, Amtsgericht Siegen - WEEE-Reg.-Nr. DE30763240
USt.-Id.-Nr. DE 126575222 - Steuer-Nr. 342 / 5835 / 1041
--------------------------------------------------------------------------
DQS-zertifiziert nach ISO 9001:2000
--------------------------------------------------------------------------

[U-Boot] [PATCH] ppc4xx: Add CATCenter Io 405EP board support

[Stefan Roese]

Hi Dirk,

On Wednesday 13 October 2010 09:25:33 Eibach, Dirk wrote:
> > > +#define MDIO_ACTIVE	out32(GPIO0_TCR, in32(GPIO0_TCR) |
> > > CONFIG_SYS_MDIO_PIN)
> > 
> > Use out_be32() accessors here and below.
> 
> Just being curious: why?

Because of the included memory barriers in the in/out_be32() functions. You 
might run into problems when using the "plain" in/out32() function requiring 
extra "sync" instructions.

> Has in32() also to be replaced?

Yes, of course.

Cheers,
Stefan

--
DENX Software Engineering GmbH,      MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de

[U-Boot] [PATCH] ppc4xx: Add CATCenter Io 405EP board support

[Eibach, Dirk]

>... 
> <snip>
> 
> > +/* Gbit PHYs */
> > +#define CONFIG_BITBANGMII		/* bit-bang MII PHY 
> management	*/
> > +
> > +#define CONFIG_SYS_MDIO_PIN  (0x80000000 >> 13)	 /* our 
> MDIO is GPIO0 
> */
> > +#define CONFIG_SYS_MDC_PIN   (0x80000000 >> 7)	 /* our 
> MDC  is GPIO7  
> */
> > +
> > +#define MDIO_ACTIVE	out32(GPIO0_TCR, in32(GPIO0_TCR) |
> > CONFIG_SYS_MDIO_PIN)
> 
> Use out_be32() accessors here and below.
> 
> Please fix and resubmit. Thanks.

To make this work, drivers/net/phy/miiphybb.c would have to include
asm/io.h somehow. What would be the right way to achieve this?

> Cheers,
> Stefan

Cheers
Dirk

[U-Boot] [PATCH] ppc4xx: Add CATCenter Io 405EP board support

[Wolfgang Denk]

Dear "Eibach, Dirk",

In message <48D3D52125C49B43AE880038E2E5314BB5BDEA@SRV101.gdsys.de> you wrote:
> 
> To make this work, drivers/net/phy/miiphybb.c would have to include
> asm/io.h somehow. What would be the right way to achieve this?

This is a pretty clear indication that this processor or even board
specific access stuff does not belong into the generic file
drivers/net/phy/miiphybb.c - please reconsider the design.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Where people stand is not as important as which way they face.
        - Terry Pratchett & Stephen Briggs, _The Discworld Companion_

[U-Boot] [PATCH] ppc4xx: Add CATCenter Io 405EP board support

[Stefan Roese]

On Wednesday 13 October 2010 10:23:26 Eibach, Dirk wrote:
> > > +
> > > +#define MDIO_ACTIVE	out32(GPIO0_TCR, in32(GPIO0_TCR) |
> > > CONFIG_SYS_MDIO_PIN)
> > 
> > Use out_be32() accessors here and below.
> > 
> > Please fix and resubmit. Thanks.
> 
> To make this work, drivers/net/phy/miiphybb.c would have to include
> asm/io.h somehow. What would be the right way to achieve this?

From looking at the code it seems there is a CONFIG_BITBANGMII_MULTI config 
option to enable board specific commands for GPIO access. Take a look at 
doc/README.bitbangMII for more details.

Cheers,
Stefan

--
DENX Software Engineering GmbH,      MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de