[U-Boot] [PATCH 01/15] powerpc/fsl-pci: Add generic code to setup PCIe controllers

[U-Boot] [PATCH 01/15] powerpc/fsl-pci: Add generic code to setup PCIe controllers

[Kumar Gala]

Since all the PCIe controllers are connected over SERDES on the SoCs we
can utilize is_serdes_configured() to determine if a controller is
enabled.  After which we can setup the ATMUs and LAWs for the controller
in a common fashion and allow board code to specify what the controller
is connected to for reporting reasons.

We also provide a per controller (rather than all) for some systems that
may have special requirements.

Finally, we refactor the code used by the P1022DS to utilize the new
generic code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 arch/powerpc/include/asm/fsl_pci.h |   10 +++
 board/freescale/p1022ds/p1022ds.c  |   67 +------------------
 drivers/pci/fsl_pci_init.c         |  127 ++++++++++++++++++++++++++++++++++++
 3 files changed, 139 insertions(+), 65 deletions(-)

diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h
index 5cbe139..15ab50d 100644
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -22,6 +22,8 @@
 #define __FSL_PCI_H_
 
 #include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <pci.h>
 
 int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
 int fsl_is_pci_agent(struct pci_controller *hose);
@@ -172,6 +174,9 @@ struct fsl_pci_info {
 
 int fsl_pci_init_port(struct fsl_pci_info *pci_info,
 				struct pci_controller *hose, int busno);
+int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
+			struct fsl_pci_info *pci_info);
+int fsl_pcie_init_board(int busno);
 
 #define SET_STD_PCI_INFO(x, num) \
 {			\
@@ -220,6 +225,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
 	FT_FSL_PCIE2_SETUP; \
 	FT_FSL_PCIE3_SETUP; \
 	FT_FSL_PCIE4_SETUP;
+#define FT_FSL_PCIE_SETUP FT_FSL_PCI_SETUP
 #elif defined(CONFIG_MPC85xx)
 #define FSL_PCI_COMPAT	"fsl,mpc8540-pci"
 #define FSL_PCIE_COMPAT	"fsl,mpc8548-pcie"
@@ -229,6 +235,10 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
 	FT_FSL_PCIE1_SETUP; \
 	FT_FSL_PCIE2_SETUP; \
 	FT_FSL_PCIE3_SETUP;
+#define FT_FSL_PCIE_SETUP \
+	FT_FSL_PCIE1_SETUP; \
+	FT_FSL_PCIE2_SETUP; \
+	FT_FSL_PCIE3_SETUP;
 #elif defined(CONFIG_MPC86xx)
 #define FSL_PCI_COMPAT	"fsl,mpc8610-pci"
 #define FSL_PCIE_COMPAT	"fsl,mpc8641-pcie"
diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c
index 7cb549b..fc62a00 100644
--- a/board/freescale/p1022ds/p1022ds.c
+++ b/board/freescale/p1022ds/p1022ds.c
@@ -200,7 +200,7 @@ static u8 serdes_dev_slot[][SATA2 + 1] = {
  * Returns the name of the slot to which the PCIe or SATA controller is
  * connected
  */
-const char *serdes_slot_name(enum srds_prtcl device)
+const char *board_serdes_name(enum srds_prtcl device)
 {
 	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
 	u32 pordevsr = in_be32(&gur->pordevsr);
@@ -215,73 +215,10 @@ const char *serdes_slot_name(enum srds_prtcl device)
 		return "Nothing";
 }
 
-static void configure_pcie(struct fsl_pci_info *info,
-			   struct pci_controller *hose,
-			   const char *connected)
-{
-	static int bus_number = 0;
-	int is_endpoint;
-
-	set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
-	set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
-	is_endpoint = fsl_setup_hose(hose, info->regs);
-	printf("PCIE%u: connected to %s as %s (base addr %lx)\n",
-	       info->pci_num, connected,
-	       is_endpoint ? "Endpoint" : "Root Complex", info->regs);
-	bus_number = fsl_pci_init_port(info, hose, bus_number);
-}
-
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif
-
-#ifdef CONFIG_PCIE2
-static struct pci_controller pcie2_hose;
-#endif
-
-#ifdef CONFIG_PCIE3
-static struct pci_controller pcie3_hose;
-#endif
-
 #ifdef CONFIG_PCI
 void pci_init_board(void)
 {
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-	struct fsl_pci_info pci_info;
-	u32 devdisr = in_be32(&gur->devdisr);
-
-#ifdef CONFIG_PCIE1
-	if (is_serdes_configured(PCIE1) && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
-		SET_STD_PCIE_INFO(pci_info, 1);
-		configure_pcie(&pci_info, &pcie1_hose, serdes_slot_name(PCIE1));
-	} else {
-		printf("PCIE1: disabled\n");
-	}
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE2
-	if (is_serdes_configured(PCIE2) && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
-		SET_STD_PCIE_INFO(pci_info, 2);
-		configure_pcie(&pci_info, &pcie2_hose, serdes_slot_name(PCIE2));
-	} else {
-		printf("PCIE2: disabled\n");
-	}
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE3
-	if (is_serdes_configured(PCIE3) && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
-		SET_STD_PCIE_INFO(pci_info, 3);
-		configure_pcie(&pci_info, &pcie3_hose, serdes_slot_name(PCIE3));
-	} else {
-		printf("PCIE3: disabled\n");
-	}
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
-#endif
+	fsl_pcie_init_board(0);
 }
 #endif
 
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 71ab02b..64c0198 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -18,6 +18,8 @@
  */
 
 #include <common.h>
+#include <malloc.h>
+#include <asm/fsl_serdes.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -513,6 +515,131 @@ void fsl_pci_config_unlock(struct pci_controller *hose)
 	}
 }
 
+#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || \
+    defined(CONFIG_PCIE3) || defined(CONFIG_PCIE4) 
+int fsl_configure_pcie(struct fsl_pci_info *info,
+			struct pci_controller *hose,
+			const char *connected, int busno)
+{
+	int is_endpoint;
+
+	set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
+	set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
+	is_endpoint = fsl_setup_hose(hose, info->regs);
+	printf("PCIE%u: connected to %s as %s (base addr %lx)\n",
+	       info->pci_num, connected,
+	       is_endpoint ? "Endpoint" : "Root Complex", info->regs);
+	return fsl_pci_init_port(info, hose, busno);
+}
+
+#if defined(CONFIG_FSL_CORENET)
+	#define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1
+	#define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2
+	#define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3
+	#define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4
+	#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
+#elif defined(CONFIG_MPC85xx)
+	#define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE
+	#define _DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2
+	#define _DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3
+	#define _DEVDISR_PCIE4 0
+	#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
+#elif defined(CONFIG_MPC86xx)
+	#define _DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIE1
+	#define _DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIE2
+	#define _DEVDISR_PCIE3 0
+	#define _DEVDISR_PCIE4 0
+	#define CONFIG_SYS_MPC8xxx_GUTS_ADDR \
+		(&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
+#else
+#error "No defines for DEVDISR_PCIE"
+#endif
+
+/* Implement a dummy function for those platforms w/o SERDES */
+static const char *__board_serdes_name(enum srds_prtcl device)
+{
+	return NULL;
+}
+
+__attribute__((weak, alias("__board_serdes_name"))) const char *
+board_serdes_name(enum srds_prtcl device);
+
+static u32 devdisr_mask[] = {
+	_DEVDISR_PCIE1,
+	_DEVDISR_PCIE2,
+	_DEVDISR_PCIE3,
+	_DEVDISR_PCIE4,
+};
+
+int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
+			struct fsl_pci_info *pci_info)
+{
+	struct pci_controller *hose;
+	int num = dev - PCIE1;
+
+	hose = calloc(1, sizeof(struct pci_controller));
+	if (!hose)
+		return busno;
+
+	if (is_serdes_configured(dev) && !(devdisr & devdisr_mask[num])) {
+		busno = fsl_configure_pcie(pci_info, hose,
+				board_serdes_name(dev), busno);
+	} else {
+		printf("PCIE%d: disabled\n", num + 1);
+	}
+
+	return busno;
+}
+
+int fsl_pcie_init_board(int busno)
+{
+	struct fsl_pci_info pci_info;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
+	u32 devdisr = in_be32(&gur->devdisr);
+
+#ifdef CONFIG_PCIE1
+	SET_STD_PCIE_INFO(pci_info, 1);
+	busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info);
+#else
+	setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */
+#endif
+
+#ifdef CONFIG_PCIE2
+	SET_STD_PCIE_INFO(pci_info, 2);
+	busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE2, &pci_info);
+#else
+	setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */
+#endif
+
+#ifdef CONFIG_PCIE3
+	SET_STD_PCIE_INFO(pci_info, 3);
+	busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE3, &pci_info);
+#else
+	setbits_be32(&gur->devdisr, _DEVDISR_PCIE3); /* disable */
+#endif
+
+#ifdef CONFIG_PCIE4
+	SET_STD_PCIE_INFO(pci_info, 4);
+	busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE4, &pci_info);
+#else
+	setbits_be32(&gur->devdisr, _DEVDISR_PCIE4); /* disable */
+#endif
+
+ 	return busno;
+}
+#else
+int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
+			struct fsl_pci_info *pci_info)
+{
+	return busno;
+}
+
+int fsl_pcie_init_board(int busno)
+{
+	return busno;
+}
+#endif
+
 #ifdef CONFIG_OF_BOARD_SETUP
 #include <libfdt.h>
 #include <fdt_support.h>
-- 
1.6.0.6

[U-Boot] [PATCH 02/15] powerpc/85xx: Rework MPC8572DS pci_init_board to use common FSL PCIe code

[Kumar Gala]

Remove duplicated code in MPC8572DS board and utliize the common
fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 board/freescale/mpc8572ds/law.c       |    8 +--
 board/freescale/mpc8572ds/mpc8572ds.c |  100 ++++++--------------------------
 2 files changed, 20 insertions(+), 88 deletions(-)

diff --git a/board/freescale/mpc8572ds/law.c b/board/freescale/mpc8572ds/law.c
index e13bb53..7c63f84 100644
--- a/board/freescale/mpc8572ds/law.c
+++ b/board/freescale/mpc8572ds/law.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008, 2010 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
@@ -29,12 +29,6 @@
 
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3),
-	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
 	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 };
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index c217c27..2b269f2 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -148,107 +148,45 @@ phys_size_t fixed_sdram (void)
 
 #endif
 
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif
-
-#ifdef CONFIG_PCIE2
-static struct pci_controller pcie2_hose;
-#endif
+#ifdef CONFIG_PCI
+static const char *slot_names[] = {
+	[PCIE1] = "Slot 2",
+	[PCIE2] = "Slot 1",
+	[PCIE3] = "ULI",
+};
 
-#ifdef CONFIG_PCIE3
-static struct pci_controller pcie3_hose;
-#endif
+const char *board_serdes_name(enum srds_prtcl device)
+{
+	return slot_names[device];
+}
 
-#ifdef CONFIG_PCI
 void pci_init_board(void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	struct fsl_pci_info pci_info[3];
-	u32 devdisr, pordevsr, io_sel, temp32;
-	int first_free_busno = 0;
-	int num = 0;
+	struct pci_controller *hose;
 
-	int pcie_ep, pcie_configured;
+	fsl_pcie_init_board(0);
 
-	devdisr = in_be32(&gur->devdisr);
-	pordevsr = in_be32(&gur->pordevsr);
-	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+	hose = find_hose_by_cfg_addr((void *)(CONFIG_SYS_PCIE3_ADDR));
 
-	debug ("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
+	if (hose) {
+		u32 temp32;
+		u8 uli_busno = hose->first_busno + 2;
 
-	puts("\n");
-#ifdef CONFIG_PCIE3
-	pcie_configured = is_serdes_configured(PCIE3);
-
-	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
-		SET_STD_PCIE_INFO(pci_info[num], 3);
-		pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
-		printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
-			pcie_ep ? "Endpoint" : "Root Complex",
-			pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie3_hose, first_free_busno);
 		/*
 		 * Activate ULI1575 legacy chip by performing a fake
 		 * memory access.  Needed to make ULI RTC work.
 		 * Device 1d has the first on-board memory BAR.
 		 */
-		pci_hose_read_config_dword(&pcie3_hose, PCI_BDF(2, 0x1d, 0),
+		pci_hose_read_config_dword(hose, PCI_BDF(uli_busno, 0x1d, 0),
 				PCI_BASE_ADDRESS_1, &temp32);
+
 		if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
-			void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
+			void *p = pci_mem_to_virt(PCI_BDF(uli_busno, 0x1d, 0),
 					temp32, 4, 0);
 			debug(" uli1572 read to %p\n", p);
 			in_be32(p);
 		}
-	} else {
-		printf("PCIE3: disabled\n");
 	}
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE2
-	pcie_configured = is_serdes_configured(PCIE2);
-
-	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
-		SET_STD_PCIE_INFO(pci_info[num], 2);
-		pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
-		printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n",
-			pcie_ep ? "Endpoint" : "Root Complex",
-			pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie2_hose, first_free_busno);
-	} else {
-		printf("PCIE2: disabled\n");
-	}
-
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE1
-	pcie_configured = is_serdes_configured(PCIE1);
-
-	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
-		SET_STD_PCIE_INFO(pci_info[num], 1);
-		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-		printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
-				pcie_ep ? "Endpoint" : "Root Complex",
-				pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie1_hose, first_free_busno);
-	} else {
-		printf("PCIE1: disabled\n");
-	}
-
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
-#endif
 }
 #endif
 
-- 
1.6.0.6

[U-Boot] [PATCH 03/15] powerpc/85xx: Rework P2020DS pci_init_board to use common FSL PCIe code

[Kumar Gala]

Remove duplicated code in P2020DS board and utliize the common
fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 board/freescale/p2020ds/law.c     |    8 +--
 board/freescale/p2020ds/p2020ds.c |  114 ++++---------------------------------
 2 files changed, 12 insertions(+), 110 deletions(-)

diff --git a/board/freescale/p2020ds/law.c b/board/freescale/p2020ds/law.c
index 28ed2ed..91642a9 100644
--- a/board/freescale/p2020ds/law.c
+++ b/board/freescale/p2020ds/law.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
@@ -29,12 +29,6 @@
 
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3),
-	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
 	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 };
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index 07b0801..727de69 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -175,113 +175,21 @@ phys_size_t fixed_sdram(void)
 
 #endif
 
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif
-
-#ifdef CONFIG_PCIE2
-static struct pci_controller pcie2_hose;
-#endif
+#ifdef CONFIG_PCI
+static const char *slot_names[] = {
+	[PCIE1] = "Slot 2",
+	[PCIE2] = "ULI",
+	[PCIE3] = "Slot 1",
+};
 
-#ifdef CONFIG_PCIE3
-static struct pci_controller pcie3_hose;
-#endif
+const char *board_serdes_name(enum srds_prtcl device)
+{
+	return slot_names[device];
+}
 
-#ifdef CONFIG_PCI
 void pci_init_board(void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	struct fsl_pci_info pci_info[3];
-	u32 devdisr, pordevsr, io_sel;
-	int first_free_busno = 0;
-	int num = 0;
-
-	int pcie_ep, pcie_configured;
-
-	devdisr = in_be32(&gur->devdisr);
-	pordevsr = in_be32(&gur->pordevsr);
-	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
-
-	debug ("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
-
-	puts("\n");
-#ifdef CONFIG_PCIE2
-	pcie_configured = is_serdes_configured(PCIE2);
-
-	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
-		SET_STD_PCIE_INFO(pci_info[num], 2);
-		pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
-		printf("PCIE2: connected to ULI as %s (base addr %lx)\n",
-			pcie_ep ? "Endpoint" : "Root Complex",
-			pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie2_hose, first_free_busno);
-
-		/*
-		 * The workaround doesn't work on p2020 because the location
-		 * we try and read isn't valid on p2020, fix this later
-		 */
-#if 0
-		/*
-		 * Activate ULI1575 legacy chip by performing a fake
-		 * memory access.  Needed to make ULI RTC work.
-		 * Device 1d has the first on-board memory BAR.
-		 */
-
-		pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0),
-				PCI_BASE_ADDRESS_1, &temp32);
-		if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
-			void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
-							temp32, 4, 0);
-			debug(" uli1575 read to %p\n", p);
-			in_be32(p);
-		}
-#endif
-	} else {
-		printf("PCIE2: disabled\n");
-	}
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE3
-	pcie_configured = is_serdes_configured(PCIE3);
-
-	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
-		SET_STD_PCIE_INFO(pci_info[num], 3);
-		pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
-		printf("PCIE3: connected to Slot 1 as %s (base addr %lx)\n",
-			pcie_ep ? "Endpoint" : "Root Complex",
-			pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie3_hose, first_free_busno);
-	} else {
-		printf("PCIE3: disabled\n");
-	}
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE1
-	pcie_configured = is_serdes_configured(PCIE1);
-
-	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
-		SET_STD_PCIE_INFO(pci_info[num], 1);
-		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-		printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
-			pcie_ep ? "Endpoint" : "Root Complex",
-			pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie1_hose, first_free_busno);
-	} else {
-		printf("PCIE1: disabled\n");
-	}
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
-#endif
+	fsl_pcie_init_board(0);
 }
 #endif
 
-- 
1.6.0.6

[U-Boot] [PATCH 04/15] powerpc/85xx: Rework MPC8544DS pci_init_board to use common FSL PCIe code

[Kumar Gala]

Remove duplicated code in MPC8544DS board and utliize the common
fsl_pcie_init_ctrl().  We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.

We don't use the full fsl_pcie_init_ctrl() since we have to handle PCIE3
specially to setup the additional memory map region and we utilize a
single LAW to cover the controller.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 board/freescale/mpc8544ds/law.c       |   10 +---
 board/freescale/mpc8544ds/mpc8544ds.c |  110 +++++++++++----------------------
 2 files changed, 37 insertions(+), 83 deletions(-)

diff --git a/board/freescale/mpc8544ds/law.c b/board/freescale/mpc8544ds/law.c
index 3d308c8..59e03fc 100644
--- a/board/freescale/mpc8544ds/law.c
+++ b/board/freescale/mpc8544ds/law.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008, 2010 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
@@ -28,15 +28,7 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI),
 	SET_LAW(CONFIG_SYS_LBC_NONCACHE_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
-	/* contains both PCIE3 MEM & IO space */
-	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_PCIE_3),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index 2b6900c..908077f 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -89,26 +89,28 @@ initdram(int board_type)
 static struct pci_controller pci1_hose;
 #endif
 
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif
-
-#ifdef CONFIG_PCIE2
-static struct pci_controller pcie2_hose;
-#endif
-
 #ifdef CONFIG_PCIE3
 static struct pci_controller pcie3_hose;
 #endif
 
+static const char *slot_names[] = {
+	[PCIE1] = "Slot 2",
+	[PCIE2] = "Slot 1",
+	[PCIE3] = "ULI",
+};
+ 
+const char *board_serdes_name(enum srds_prtcl device)
+{
+	return slot_names[device];
+}
+
 void pci_init_board(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	struct fsl_pci_info pci_info[4];
+	struct fsl_pci_info pci_info;
 	u32 devdisr, pordevsr, io_sel;
 	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
 	int first_free_busno = 0;
-	int num = 0;
 
 	int pcie_ep, pcie_configured;
 
@@ -125,9 +127,12 @@ void pci_init_board(void)
 	pcie_configured = is_serdes_configured(PCIE3);
 
 	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
-		SET_STD_PCIE_INFO(pci_info[num], 3);
-		pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
-#ifdef CONFIG_SYS_PCIE3_MEM_BUS2
+		/* contains both PCIE3 MEM & IO space */
+		set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M,
+				LAW_TRGT_IF_PCIE_3);
+		SET_STD_PCIE_INFO(pci_info, 3);
+		pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info.regs);
+
 		/* outbound memory */
 		pci_set_region(&pcie3_hose.regions[0],
 			       CONFIG_SYS_PCIE3_MEM_BUS2,
@@ -136,11 +141,11 @@ void pci_init_board(void)
 			       PCI_REGION_MEM);
 
 		pcie3_hose.region_count = 1;
-#endif
+
 		printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
 			pcie_ep ? "Endpoint" : "Root Complex",
-			pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+			pci_info.regs);
+		first_free_busno = fsl_pci_init_port(&pci_info,
 					&pcie3_hose, first_free_busno);
 
 		/*
@@ -157,64 +162,17 @@ void pci_init_board(void)
 #endif
 
 #ifdef CONFIG_PCIE1
-	pcie_configured = is_serdes_configured(PCIE1);
-
-	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
-		SET_STD_PCIE_INFO(pci_info[num], 1);
-		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-#ifdef CONFIG_SYS_PCIE1_MEM_BUS2
-		/* outbound memory */
-		pci_set_region(&pcie1_hose.regions[0],
-			       CONFIG_SYS_PCIE1_MEM_BUS2,
-			       CONFIG_SYS_PCIE1_MEM_PHYS2,
-			       CONFIG_SYS_PCIE1_MEM_SIZE2,
-			       PCI_REGION_MEM);
-
-		pcie1_hose.region_count = 1;
-#endif
-		printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
-				pcie_ep ? "Endpoint" : "Root Complex",
-				pci_info[num].regs);
-
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie1_hose, first_free_busno);
-	} else {
-		printf("PCIE1: disabled\n");
-	}
-
-	puts("\n");
+	SET_STD_PCIE_INFO(pci_info, 1);
+	first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE1, &pci_info);
 #else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
+	setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */
 #endif
 
 #ifdef CONFIG_PCIE2
-	pcie_configured = is_serdes_configured(PCIE2);
-
-	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
-		SET_STD_PCIE_INFO(pci_info[num], 2);
-		pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
-#ifdef CONFIG_SYS_PCIE2_MEM_BUS2
-		/* outbound memory */
-		pci_set_region(&pcie2_hose.regions[0],
-			       CONFIG_SYS_PCIE2_MEM_BUS2,
-			       CONFIG_SYS_PCIE2_MEM_PHYS2,
-			       CONFIG_SYS_PCIE2_MEM_SIZE2,
-			       PCI_REGION_MEM);
-
-		pcie2_hose.region_count = 1;
-#endif
-		printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n",
-			pcie_ep ? "Endpoint" : "Root Complex",
-			pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie2_hose, first_free_busno);
-	} else {
-		printf("PCIE2: disabled\n");
-	}
-
-	puts("\n");
+	SET_STD_PCIE_INFO(pci_info, 2);
+	first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE2, &pci_info);
 #else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
+	setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */
 #endif
 
 #ifdef CONFIG_PCI1
@@ -224,8 +182,13 @@ void pci_init_board(void)
 	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
 
 	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
-		SET_STD_PCI_INFO(pci_info[num], 1);
-		pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
+		SET_STD_PCI_INFO(pci_info, 1);
+		set_next_law(pci_info.mem_phys,
+			law_size_bits(pci_info.mem_size), pci_info.law);
+		set_next_law(pci_info.io_phys,
+			law_size_bits(pci_info.io_size), pci_info.law);
+
+		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
 		printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
 			(pci_32) ? 32 : 64,
 			(pci_speed == 33333000) ? "33" :
@@ -233,9 +196,9 @@ void pci_init_board(void)
 			pci_clk_sel ? "sync" : "async",
 			pci_agent ? "agent" : "host",
 			pci_arb ? "arbiter" : "external-arbiter",
-			pci_info[num].regs);
+			pci_info.regs);
 
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+		first_free_busno = fsl_pci_init_port(&pci_info,
 					&pci1_hose, first_free_busno);
 	} else {
 		printf("PCI: disabled\n");
@@ -247,7 +210,6 @@ void pci_init_board(void)
 #endif
 }
 
-
 int last_stage_init(void)
 {
 	return 0;
-- 
1.6.0.6

[U-Boot] [PATCH 05/15] powerpc/85xx: Rework MPC8536DS pci_init_board to use common FSL PCIe code

[Kumar Gala]

Remove duplicated code in MPC8536DS board and utliize the common
fsl_pcie_init_board().

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 board/freescale/mpc8536ds/mpc8536ds.c |  125 ++++++--------------------------
 1 files changed, 24 insertions(+), 101 deletions(-)

diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index bd80cb7..c005ab7 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -177,123 +177,46 @@ phys_size_t fixed_sdram (void)
 static struct pci_controller pci1_hose;
 #endif
 
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif
-
-#ifdef CONFIG_PCIE2
-static struct pci_controller pcie2_hose;
-#endif
+#ifdef CONFIG_PCI
+static const char *slot_names[] = {
+	[PCIE1] = "Slot 1",
+	[PCIE2] = "Slot 2",
+	[PCIE3] = "Slot 3",
+};
 
-#ifdef CONFIG_PCIE3
-static struct pci_controller pcie3_hose;
-#endif
+const char *board_serdes_name(enum srds_prtcl device)
+{
+	return slot_names[device];
+}
 
-#ifdef CONFIG_PCI
 void pci_init_board(void)
 {
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	struct fsl_pci_info pci_info[4];
-	u32 devdisr, pordevsr, io_sel;
+	struct fsl_pci_info pci_info;
+	u32 devdisr, pordevsr;
 	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
-	int first_free_busno = 0;
-	int num = 0;
+	int first_free_busno;
 
-	int pcie_ep, pcie_configured;
+	first_free_busno = fsl_pcie_init_board(0);
 
+#ifdef CONFIG_PCI1
 	devdisr = in_be32(&gur->devdisr);
 	pordevsr = in_be32(&gur->pordevsr);
 	porpllsr = in_be32(&gur->porpllsr);
-	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
-
-	debug("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
 
-	puts("\n");
-#ifdef CONFIG_PCIE3
-	pcie_configured = is_serdes_configured(PCIE3);
-
-	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
-		set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M,
-				LAW_TRGT_IF_PCIE_3);
-		set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K,
-				LAW_TRGT_IF_PCIE_3);
-		SET_STD_PCIE_INFO(pci_info[num], 3);
-		pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
-		printf("PCIE3: connected to Slot3 as %s (base address %lx)\n",
-			pcie_ep ? "Endpoint" : "Root Complex",
-			pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie3_hose, first_free_busno);
-	} else {
-		printf("PCIE3: disabled\n");
-	}
-
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE1
-	pcie_configured = is_serdes_configured(PCIE1);
-
-	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
-		set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M,
-				LAW_TRGT_IF_PCIE_1);
-		set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K,
-				LAW_TRGT_IF_PCIE_1);
-		SET_STD_PCIE_INFO(pci_info[num], 1);
-		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-		printf("PCIE1: connected to Slot1 as %s (base address %lx)\n",
-			pcie_ep ? "Endpoint" : "Root Complex",
-			pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie1_hose, first_free_busno);
-	} else {
-		printf("PCIE1: disabled\n");
-	}
-
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE2
-	pcie_configured = is_serdes_configured(PCIE2);
-
-	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
-		set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M,
-				LAW_TRGT_IF_PCIE_2);
-		set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K,
-				LAW_TRGT_IF_PCIE_2);
-		SET_STD_PCIE_INFO(pci_info[num], 2);
-		pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
-		printf("PCIE2: connected to Slot 2 as %s (base address %lx)\n",
-			pcie_ep ? "Endpoint" : "Root Complex",
-			pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie2_hose, first_free_busno);
-	} else {
-		printf("PCIE2: disabled\n");
-	}
-
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
-#endif
-
-#ifdef CONFIG_PCI1
 	pci_speed = 66666000;
 	pci_32 = 1;
 	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
 	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
 
 	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
-		set_next_law(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M,
-				LAW_TRGT_IF_PCI);
-		set_next_law(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K,
-				LAW_TRGT_IF_PCI);
-		SET_STD_PCI_INFO(pci_info[num], 1);
-		pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
+		SET_STD_PCI_INFO(pci_info, 1);
+		set_next_law(pci_info.mem_phys,
+			law_size_bits(pci_info.mem_size), pci_info.law);
+		set_next_law(pci_info.io_phys,
+			law_size_bits(pci_info.io_size), pci_info.law);
+
+		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
 		printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
 			(pci_32) ? 32 : 64,
 			(pci_speed == 33333000) ? "33" :
@@ -301,9 +224,9 @@ void pci_init_board(void)
 			pci_clk_sel ? "sync" : "async",
 			pci_agent ? "agent" : "host",
 			pci_arb ? "arbiter" : "external-arbiter",
-			pci_info[num].regs);
+			pci_info.regs);
 
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+		first_free_busno = fsl_pci_init_port(&pci_info,
 					&pci1_hose, first_free_busno);
 	} else {
 		printf("PCI: disabled\n");
-- 
1.6.0.6

[U-Boot] [PATCH 06/15] powerpc/86xx: Rework MPC8641HPCN pci_init_board to use common FSL PCIe code

[Kumar Gala]

Remove duplicated code in MPC8641HPCN board and utliize the common
fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 board/freescale/mpc8641hpcn/law.c         |    7 +---
 board/freescale/mpc8641hpcn/mpc8641hpcn.c |   56 +++++-----------------------
 2 files changed, 11 insertions(+), 52 deletions(-)

diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c
index 8c8ce95..30a7b70 100644
--- a/board/freescale/mpc8641hpcn/law.c
+++ b/board/freescale/mpc8641hpcn/law.c
@@ -53,12 +53,7 @@ struct law_entry law_table[] = {
 #if !defined(CONFIG_SPD_EEPROM)
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
 #endif
-#ifdef CONFIG_PCI
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2),
-#elif defined(CONFIG_RIO)
+#if defined(CONFIG_RIO)
 	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 #endif
 	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index e951021..be70dc2 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -127,64 +127,28 @@ fixed_sdram(void)
 }
 #endif	/* !defined(CONFIG_SPD_EEPROM) */
 
-
-#if defined(CONFIG_PCI)
-static struct pci_controller pcie1_hose;
-#endif /* CONFIG_PCI */
-
-#ifdef CONFIG_PCIE2
-static struct pci_controller pcie2_hose;
-#endif	/* CONFIG_PCIE2 */
-
-int first_free_busno = 0;
+static const char *slot_names[] = {
+	[PCIE1] = "ULI",
+	[PCIE2] = "",
+};
+ 
+const char *board_serdes_name(enum srds_prtcl device)
+{
+	return slot_names[device];
+}
 
 void pci_init_board(void)
 {
-	struct fsl_pci_info pci_info[2];
-	int pcie_ep;
-	int num = 0;
+	fsl_pcie_init_board(0);
 
 #ifdef CONFIG_PCIE1
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	uint devdisr = in_be32(&gur->devdisr);
-	int pcie_configured = is_serdes_configured(PCIE1);
-
-	if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
-		SET_STD_PCIE_INFO(pci_info[num], 1);
-		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-		printf("PCIE1: connected to ULI as %s (base addr %lx)\n",
-			pcie_ep ? "Endpoint" : "Root Complex",
-			pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie1_hose, first_free_busno);
-
 		/*
 		 * Activate ULI1575 legacy chip by performing a fake
 		 * memory access.  Needed to make ULI RTC work.
 		 */
 		in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT
 				       + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
-
-	} else {
-		puts("PCIE1: disabled\n");
-	}
-#else
-	puts("PCIE1: disabled\n");
 #endif /* CONFIG_PCIE1 */
-
-#ifdef CONFIG_PCIE2
-	SET_STD_PCIE_INFO(pci_info[num], 2);
-	pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
-	printf("PCIE2: connected as %s (base addr %lx)\n",
-		pcie_ep ? "Endpoint" : "Root Complex",
-		pci_info[num].regs);
-	first_free_busno = fsl_pci_init_port(&pci_info[num++],
-				&pcie2_hose, first_free_busno);
-#else
-	puts("PCIE2: disabled\n");
-#endif /* CONFIG_PCIE2 */
-
 }
 
 
-- 
1.6.0.6

[U-Boot] [PATCH 07/15] powerpc/85xx: Rework MPC8548CDS pci_init_board to use common FSL PCIe code

[Kumar Gala]

Remove duplicated code in MPC8548CDS board and utliize the common
fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 board/freescale/mpc8548cds/law.c        |   10 +------
 board/freescale/mpc8548cds/mpc8548cds.c |   46 ++++++++++---------------------
 2 files changed, 16 insertions(+), 40 deletions(-)

diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c
index 98748aa..e59fee8 100644
--- a/board/freescale/mpc8548cds/law.c
+++ b/board/freescale/mpc8548cds/law.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008,2010 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
@@ -51,18 +51,10 @@
  */
 
 struct law_entry law_table[] = {
-#ifdef CONFIG_SYS_PCI1_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
-#endif
 #ifdef CONFIG_SYS_PCI2_MEM_PHYS
 	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
 	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
 #endif
-#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
-#endif
 	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
 	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 #ifdef CONFIG_SYS_RIO_MEM_PHYS
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index ebeb897..0f8d04e 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -254,20 +254,18 @@ static struct pci_controller pci1_hose = {
 static struct pci_controller pci2_hose;
 #endif	/* CONFIG_PCI2 */
 
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif	/* CONFIG_PCIE1 */
+const char *board_serdes_name(enum srds_prtcl device)
+{
+	return "Slot";
+}
 
 void pci_init_board(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	struct fsl_pci_info pci_info[4];
+	struct fsl_pci_info pci_info;
 	u32 devdisr, pordevsr, io_sel;
 	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
 	int first_free_busno = 0;
-	int num = 0;
-
-	int pcie_ep, pcie_configured;
 
 	devdisr = in_be32(&gur->devdisr);
 	pordevsr = in_be32(&gur->pordevsr);
@@ -283,8 +281,13 @@ void pci_init_board(void)
 	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
 
 	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
-		SET_STD_PCI_INFO(pci_info[num], 1);
-		pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
+		SET_STD_PCI_INFO(pci_info, 1);
+		set_next_law(pci_info.mem_phys,
+			law_size_bits(pci_info.mem_size), pci_info.law);
+		set_next_law(pci_info.io_phys,
+			law_size_bits(pci_info.io_size), pci_info.law);
+
+		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
 		printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
 			(pci_32) ? 32 : 64,
 			(pci_speed == 33333000) ? "33" :
@@ -292,9 +295,9 @@ void pci_init_board(void)
 			pci_clk_sel ? "sync" : "async",
 			pci_agent ? "agent" : "host",
 			pci_arb ? "arbiter" : "external-arbiter",
-			pci_info[num].regs);
+			pci_info.regs);
 
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+		first_free_busno = fsl_pci_init_port(&pci_info,
 					&pci1_hose, first_free_busno);
 
 #ifdef CONFIG_PCIX_CHECK
@@ -332,26 +335,7 @@ void pci_init_board(void)
 	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */
 #endif /* CONFIG_PCI2 */
 
-#ifdef CONFIG_PCIE1
-	pcie_configured = is_serdes_configured(PCIE1);
-
-	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
-		SET_STD_PCIE_INFO(pci_info[num], 1);
-		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-		printf("PCIE1: connected to Slot as %s (base addr %lx)\n",
-			pcie_ep ? "Endpoint" : "Root Complex",
-			pci_info[num].regs);
-
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie1_hose, first_free_busno);
-	} else {
-		printf("PCIE1: disabled\n");
-	}
-
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
-#endif
+	fsl_pcie_init_board(first_free_busno);
 }
 
 int last_stage_init(void)
-- 
1.6.0.6

[U-Boot] [PATCH 08/15] powerpc/8xxx: Rework XES boards pci_init_board to use common FSL PCIe code

[Kumar Gala]

Remove duplicated code in MPC8572 DS board and utliize the common
fsl_pcie_init_board().

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
CC: Peter Tyser <ptyser@xes-inc.com>
---
 board/xes/common/fsl_8xxx_pci.c |   82 ++++-----------------------------------
 board/xes/xpedite517x/law.c     |    8 ----
 board/xes/xpedite520x/law.c     |    4 --
 board/xes/xpedite537x/law.c     |   12 ------
 board/xes/xpedite550x/law.c     |   12 ------
 5 files changed, 8 insertions(+), 110 deletions(-)

diff --git a/board/xes/common/fsl_8xxx_pci.c b/board/xes/common/fsl_8xxx_pci.c
index 4135849..202520d 100644
--- a/board/xes/common/fsl_8xxx_pci.c
+++ b/board/xes/common/fsl_8xxx_pci.c
@@ -34,15 +34,6 @@
 #ifdef CONFIG_PCI1
 static struct pci_controller pci1_hose;
 #endif
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif
-#ifdef CONFIG_PCIE2
-static struct pci_controller pcie2_hose;
-#endif
-#ifdef CONFIG_PCIE3
-static struct pci_controller pcie3_hose;
-#endif
 
 /*
  * 85xx and 86xx share naming conventions, but different layout.
@@ -69,22 +60,13 @@ static struct pci_controller pcie3_hose;
 
 void pci_init_board(void)
 {
-	struct fsl_pci_info pci_info[3];
 	int first_free_busno = 0;
-	int num = 0;
-	int pcie_ep;
-	__maybe_unused int pcie_configured;
 
-#if defined(CONFIG_MPC85xx)
+#ifdef CONFIG_PCI1
+	int pcie_ep;
+	struct fsl_pci_info pci_info;
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#elif defined(CONFIG_MPC86xx)
-	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-#endif
 	u32 devdisr = in_be32(&gur->devdisr);
-
-#ifdef CONFIG_PCI1
-	u32 pordevsr = in_be32(&gur->pordevsr);
 	uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD;
 	uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32;
 	uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB;
@@ -92,8 +74,8 @@ void pci_init_board(void)
 	uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
 
 	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
-		SET_STD_PCI_INFO(pci_info[num], 1);
-		pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
+		SET_STD_PCI_INFO(pci_info, 1);
+		pcie_ep = fsl_setup_hose(&pci1_hose, pci_info.regs);
 		printf("PCI1: %d bit %s, %s %d MHz, %s, %s\n",
 			pci_32 ? 32 : 64,
 			pcix ? "PCIX" : "PCI",
@@ -102,66 +84,18 @@ void pci_init_board(void)
 			pcie_ep ? "agent" : "host",
 			pci_arb ? "arbiter" : "external-arbiter");
 
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+		first_free_busno = fsl_pci_init_port(&pci_info,
 					&pci1_hose, first_free_busno);
 	} else {
 		printf("PCI1: disabled\n");
 	}
 #elif defined CONFIG_MPC8548
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	/* PCI1 not present on MPC8572 */
 	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
 #endif
 
-#ifdef CONFIG_PCIE1
-	pcie_configured = is_serdes_configured(PCIE1);
-
-	if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) {
-		SET_STD_PCIE_INFO(pci_info[num], 1);
-		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-		printf("PCIE1: connected as %s\n",
-			pcie_ep ? "Endpoint" : "Root Complex");
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie1_hose, first_free_busno);
-	} else {
-		printf("PCIE1: disabled\n");
-	}
-#else
-	setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE1);
-#endif /* CONFIG_PCIE1 */
-
-#ifdef CONFIG_PCIE2
-	pcie_configured = is_serdes_configured(PCIE2);
-
-	if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) {
-		SET_STD_PCIE_INFO(pci_info[num], 2);
-		pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
-		printf("PCIE2: connected as %s\n",
-			pcie_ep ? "Endpoint" : "Root Complex");
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie2_hose, first_free_busno);
-	} else {
-		printf("PCIE2: disabled\n");
-	}
-#else
-	setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE2);
-#endif /* CONFIG_PCIE2 */
-
-#ifdef CONFIG_PCIE3
-	pcie_configured = is_serdes_configured(PCIE3);
-
-	if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) {
-		SET_STD_PCIE_INFO(pci_info[num], 3);
-		pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
-		printf("PCIE3: connected as %s\n",
-			pcie_ep ? "Endpoint" : "Root Complex");
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie3_hose, first_free_busno);
-	} else {
-		printf("PCIE3: disabled\n");
-	}
-#else
-	setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE3);
-#endif /* CONFIG_PCIE3 */
+	fsl_pcie_init_board(first_free_busno);
 }
 
 #if defined(CONFIG_OF_BOARD_SETUP)
diff --git a/board/xes/xpedite517x/law.c b/board/xes/xpedite517x/law.c
index 0b7d9ef..df23df1 100644
--- a/board/xes/xpedite517x/law.c
+++ b/board/xes/xpedite517x/law.c
@@ -39,14 +39,6 @@ struct law_entry law_table[] = {
 	/* NAND LAW covers 2 NAND flashes */
 	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_512K, LAW_TRGT_IF_LBC),
 #endif
-#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
-#endif
-#ifdef CONFIG_SYS_PCIE2_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2),
-#endif
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/xes/xpedite520x/law.c b/board/xes/xpedite520x/law.c
index bbfcb9d..3afb3ae 100644
--- a/board/xes/xpedite520x/law.c
+++ b/board/xes/xpedite520x/law.c
@@ -38,10 +38,6 @@ struct law_entry law_table[] = {
 	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
 	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-#if CONFIG_SYS_PCI1_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_1),
-#endif
 #if CONFIG_SYS_PCI2_MEM_PHYS
 	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2),
 	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_2),
diff --git a/board/xes/xpedite537x/law.c b/board/xes/xpedite537x/law.c
index daee676..54c28da 100644
--- a/board/xes/xpedite537x/law.c
+++ b/board/xes/xpedite537x/law.c
@@ -37,18 +37,6 @@
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
-#endif
-#ifdef CONFIG_SYS_PCIE2_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2),
-#endif
-#ifdef CONFIG_SYS_PCIE3_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_3),
-	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_3),
-#endif
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/xes/xpedite550x/law.c b/board/xes/xpedite550x/law.c
index 4d4445d..66f1cf9 100644
--- a/board/xes/xpedite550x/law.c
+++ b/board/xes/xpedite550x/law.c
@@ -37,18 +37,6 @@
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
-#endif
-#ifdef CONFIG_SYS_PCIE2_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2),
-#endif
-#ifdef CONFIG_SYS_PCIE3_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_3),
-	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_3),
-#endif
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
-- 
1.6.0.6

[U-Boot] [PATCH 09/15] powerpc/85xx: Rework TQM boards pci_init_board to use common FSL PCIe code

[Kumar Gala]

Remove duplicated code in TQM 85xx boards and utliize the common
fsl_pcie_init_board().

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
CC: wd at denx.de
---
 board/tqc/tqm85xx/law.c     |    9 +--------
 board/tqc/tqm85xx/tqm85xx.c |   41 ++++++++++++-----------------------------
 2 files changed, 13 insertions(+), 37 deletions(-)

diff --git a/board/tqc/tqm85xx/law.c b/board/tqc/tqm85xx/law.c
index e684ba2..c596303 100644
--- a/board/tqc/tqm85xx/law.c
+++ b/board/tqc/tqm85xx/law.c
@@ -67,20 +67,13 @@
 
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_2G, LAW_TRGT_IF_DDR),
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
 	SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
-#ifdef CONFIG_PCIE1
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_BUS, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1),
-#else /* !CONFIG_PCIE1 */
+#ifndef CONFIG_PCIE1
 	SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO),
 #endif /* CONFIG_PCIE1 */
 #if defined(CONFIG_CAN_DRIVER) || defined(CONFIG_NAND)
 	SET_LAW(CONFIG_SYS_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
 #endif /* CONFIG_CAN_DRIVER || CONFIG_NAND */
-#ifdef CONFIG_PCIE1
-	SET_LAW(CONFIG_SYS_PCIE1_IO_BUS, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1),
-#endif /* CONFIG_PCIE */
 };
 
 int num_law_entries = ARRAY_SIZE (law_table);
diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c
index 43c73e1..99b1331 100644
--- a/board/tqc/tqm85xx/tqm85xx.c
+++ b/board/tqc/tqm85xx/tqm85xx.c
@@ -541,31 +541,29 @@ void local_bus_init (void)
 static struct pci_controller pci1_hose;
 #endif /* CONFIG_PCI1 */
 
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif /* CONFIG_PCIE1 */
-
 void pci_init_board (void)
 {
-	struct fsl_pci_info pci_info[2];
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	int first_free_busno = 0;
-	int num = 0;
+#ifdef CONFIG_PCI1
+	struct fsl_pci_info pci_info;
 	int pcie_ep;
-	__maybe_unused int pcie_configured;
 
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	u32 devdisr = in_be32(&gur->devdisr);
-	u32 pordevsr = in_be32(&gur->pordevsr);
 
-#ifdef CONFIG_PCI1
 	uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32;
 	uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB;
 	uint pci_speed = CONFIG_SYS_CLK_FREQ;	/* PCI PSPEED in [4:5] */
 	uint pci_clk_sel = in_be32(&gur->porpllsr) & MPC85xx_PORDEVSR_PCI1_SPD;
 
 	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
-		SET_STD_PCI_INFO(pci_info[num], 1);
-		pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
+		SET_STD_PCI_INFO(pci_info, 1);
+		set_next_law(pci_info.mem_phys,
+			law_size_bits(pci_info.mem_size), pci_info.law);
+		set_next_law(pci_info.io_phys,
+			law_size_bits(pci_info.io_size), pci_info.law);
+
+		pcie_ep = fsl_setup_hose(&pci1_hose, pci_info.regs);
 		printf("PCI1:  %d bit, %s MHz, %s, %s, %s\n",
 			(pci_32) ? 32 : 64,
 			(pci_speed == 33333333) ? "33" :
@@ -573,7 +571,7 @@ void pci_init_board (void)
 			pci_clk_sel ? "sync" : "async",
 			pcie_ep ? "agent" : "host",
 			pci_arb ? "arbiter" : "external-arbiter");
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+		first_free_busno = fsl_pci_init_port(&pci_info,
 					&pci1_hose, first_free_busno);
 #ifdef CONFIG_PCIX_CHECK
 		if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1)) {
@@ -596,22 +594,7 @@ void pci_init_board (void)
 	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
 #endif
 
-#ifdef CONFIG_PCIE1
-	pcie_configured = is_serdes_configured(PCIE1);
-
-	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
-		SET_STD_PCIE_INFO(pci_info[num], 1);
-		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-		printf("PCIE1: connected as %s\n",
-			pcie_ep ? "Endpoint" : "Root Complex");
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie1_hose, first_free_busno);
-	} else {
-		printf("PCIE1: disabled\n");
-	}
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE);
-#endif /* CONFIG_PCIE1 */
+	fsl_pcie_init_board(first_free_busno);
 }
 
 #ifdef CONFIG_OF_BOARD_SETUP
-- 
1.6.0.6

[U-Boot] [PATCH 10/15] powerpc/85xx: Rework MPC8568MDS pci_init_board to use common FSL PCIe code

[Kumar Gala]

Remove duplicated code in MPC8568MDS board and utliize the common
fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 board/freescale/mpc8568mds/law.c        |    6 +---
 board/freescale/mpc8568mds/mpc8568mds.c |   52 +++++++++++--------------------
 2 files changed, 19 insertions(+), 39 deletions(-)

diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c
index 3114e8a..e24b72b 100644
--- a/board/freescale/mpc8568mds/law.c
+++ b/board/freescale/mpc8568mds/law.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008, 2010 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
@@ -50,10 +50,6 @@
  */
 
 struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
 	SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 	/* LBC window - maps 256M.  That's SDRAM, BCSR, PIBs, and Flash */
 	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
index 71cfbf0..525622c 100644
--- a/board/freescale/mpc8568mds/mpc8568mds.c
+++ b/board/freescale/mpc8568mds/mpc8568mds.c
@@ -305,10 +305,6 @@ static struct pci_controller pci1_hose = {
 };
 #endif	/* CONFIG_PCI */
 
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif  /* CONFIG_PCIE1 */
-
 /*
  * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
  */
@@ -352,16 +348,19 @@ pib_init(void)
 }
 
 #ifdef CONFIG_PCI
+const char *board_serdes_name(enum srds_prtcl device)
+{
+	return "Slot";
+}
+
 void pci_init_board(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	struct fsl_pci_info pci_info[2];
+	int first_free_busno = 0;
+#ifdef CONFIG_PCI1
+	struct fsl_pci_info pci_info;
 	u32 devdisr, pordevsr, io_sel;
 	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
-	int first_free_busno = 0;
-	int num = 0;
-
-	int pcie_ep, pcie_configured;
 
 	devdisr = in_be32(&gur->devdisr);
 	pordevsr = in_be32(&gur->pordevsr);
@@ -370,15 +369,19 @@ void pci_init_board(void)
 
 	debug ("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
 
-#ifdef CONFIG_PCI1
 	pci_speed = 66666000;
 	pci_32 = 1;
 	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
 	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
 
 	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
-		SET_STD_PCI_INFO(pci_info[num], 1);
-		pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
+		SET_STD_PCI_INFO(pci_info, 1);
+		set_next_law(pci_info.mem_phys,
+			law_size_bits(pci_info.mem_size), pci_info.law);
+		set_next_law(pci_info.io_phys,
+			law_size_bits(pci_info.io_size), pci_info.law);
+
+		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
 		printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
 			(pci_32) ? 32 : 64,
 			(pci_speed == 33333000) ? "33" :
@@ -386,9 +389,9 @@ void pci_init_board(void)
 			pci_clk_sel ? "sync" : "async",
 			pci_agent ? "agent" : "host",
 			pci_arb ? "arbiter" : "external-arbiter",
-			pci_info[num].regs);
+			pci_info.regs);
 
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+		first_free_busno = fsl_pci_init_port(&pci_info,
 					&pci1_hose, first_free_busno);
 	} else {
 		printf("PCI: disabled\n");
@@ -399,26 +402,7 @@ void pci_init_board(void)
 	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
 #endif
 
-#ifdef CONFIG_PCIE1
-	pcie_configured = is_serdes_configured(PCIE1);
-
-	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
-		SET_STD_PCIE_INFO(pci_info[num], 1);
-		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-		printf("PCIE1: connected to Slot as %s (base addr %lx)\n",
-				pcie_ep ? "Endpoint" : "Root Complex",
-				pci_info[num].regs);
-
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie1_hose, first_free_busno);
-	} else {
-		printf("PCIE1: disabled\n");
-	}
-
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
-#endif
+	fsl_pcie_init_board(first_free_busno);
 }
 #endif /* CONFIG_PCI */
 
-- 
1.6.0.6

[U-Boot] [PATCH 11/15] powerpc/85xx: Rework MPC8569MDS pci_init_board to use common FSL PCIe code

[Kumar Gala]

Remove duplicated code in MPC8569MDS board and utliize the common
fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 board/freescale/mpc8569mds/law.c        |    4 +--
 board/freescale/mpc8569mds/mpc8569mds.c |   44 ++++--------------------------
 2 files changed, 7 insertions(+), 41 deletions(-)

diff --git a/board/freescale/mpc8569mds/law.c b/board/freescale/mpc8569mds/law.c
index 60eea45..bcd0311 100644
--- a/board/freescale/mpc8569mds/law.c
+++ b/board/freescale/mpc8569mds/law.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
@@ -51,8 +51,6 @@ struct law_entry law_table[] = {
 #ifndef CONFIG_SPD_EEPROM
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_1G, LAW_TRGT_IF_DDR),
 #endif
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
 	SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 };
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
index 9700b8c..773188c 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -554,51 +554,19 @@ static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd)
 	clrbits_8(&bcsr[17], BCSR17_nUSBEN);
 }
 
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif  /* CONFIG_PCIE1 */
-
 #ifdef CONFIG_PCI
-void pci_init_board(void)
+const char *board_serdes_name(enum srds_prtcl device)
 {
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	struct fsl_pci_info pci_info[1];
-	u32 devdisr, pordevsr, io_sel;
-	int first_free_busno = 0;
-	int num = 0;
-
-	int pcie_ep, pcie_configured;
-
-	devdisr = in_be32(&gur->devdisr);
-	pordevsr = in_be32(&gur->pordevsr);
-	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
-
-	debug ("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
+	return "Slot";
+}
 
+void pci_init_board(void)
+{
 #if defined(CONFIG_PQ_MDS_PIB)
 	pib_init();
 #endif
 
-#ifdef CONFIG_PCIE1
-	pcie_configured = is_serdes_configured(PCIE1);
-
-	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
-		SET_STD_PCIE_INFO(pci_info[num], 1);
-		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-		printf("PCIE1: connected to Slot as %s (base addr %lx)\n",
-			pcie_ep ? "Endpoint" : "Root Complex",
-			pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie1_hose, first_free_busno);
-	} else {
-		printf("PCIE1: disabled\n");
-	}
-
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
-#endif
-
+	fsl_pcie_init_board(0);
 }
 #endif /* CONFIG_PCI */
 
-- 
1.6.0.6

[U-Boot] [PATCH 12/15] powerpc/85xx: Rework P1_P2_RDB pci_init_board to use common FSL PCIe code

[Kumar Gala]

Remove duplicated code in P1_P2_RDB boards and utliize the common
fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 board/freescale/p1_p2_rdb/law.c |    6 +---
 board/freescale/p1_p2_rdb/pci.c |   64 +++++---------------------------------
 2 files changed, 10 insertions(+), 60 deletions(-)

diff --git a/board/freescale/p1_p2_rdb/law.c b/board/freescale/p1_p2_rdb/law.c
index 1320d5d..4c80fa6 100644
--- a/board/freescale/p1_p2_rdb/law.c
+++ b/board/freescale/p1_p2_rdb/law.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -26,10 +26,6 @@
 
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
 	SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 };
diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c
index 2034459..ccfc996 100644
--- a/board/freescale/p1_p2_rdb/pci.c
+++ b/board/freescale/p1_p2_rdb/pci.c
@@ -32,65 +32,19 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif
+static const char *slot_names[] = {
+	[PCIE1] = "Slot 2",
+	[PCIE2] = "Slot 1",
+};
 
-#ifdef CONFIG_PCIE2
-static struct pci_controller pcie2_hose;
-#endif
+const char *board_serdes_name(enum srds_prtcl device)
+{
+	return slot_names[device];
+}
 
 void pci_init_board(void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	struct fsl_pci_info pci_info[2];
-	u32 devdisr, pordevsr;
-	int first_free_busno = 0;
-	int num = 0;
-
-	int pcie_ep, pcie_configured;
-
-	devdisr = in_be32(&gur->devdisr);
-	pordevsr = in_be32(&gur->pordevsr);
-
-	puts("\n");
-#ifdef CONFIG_PCIE2
-	pcie_configured = is_serdes_configured(PCIE2);
-
-	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
-		SET_STD_PCIE_INFO(pci_info[num], 2);
-		pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
-		printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n",
-			pcie_ep ? "Endpoint" : "Root Complex",
-			pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie2_hose, first_free_busno);
-	} else {
-		printf("PCIE2: disabled\n");
-	}
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE1
-	pcie_configured = is_serdes_configured(PCIE1);
-
-	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
-		SET_STD_PCIE_INFO(pci_info[num], 1);
-		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-		printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
-			pcie_ep ? "Endpoint" : "Root Complex",
-			pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie1_hose, first_free_busno);
-	} else {
-		printf("PCIE1: disabled\n");
-	}
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
-#endif
+	fsl_pcie_init_board(0);
 }
 
 void ft_pci_board_setup(void *blob)
-- 
1.6.0.6

[U-Boot] [PATCH 13/15] powerpc/86xx: Rework MPC8610HPCD pci_init_board to use common FSL PCIe code

[Kumar Gala]

Remove duplicated code in MPC8610HPCD board and utliize the common
fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 board/freescale/mpc8610hpcd/law.c         |    8 +---
 board/freescale/mpc8610hpcd/mpc8610hpcd.c |   80 +++++++++--------------------
 2 files changed, 25 insertions(+), 63 deletions(-)

diff --git a/board/freescale/mpc8610hpcd/law.c b/board/freescale/mpc8610hpcd/law.c
index 0fc8384..26e41b6 100644
--- a/board/freescale/mpc8610hpcd/law.c
+++ b/board/freescale/mpc8610hpcd/law.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008,2010 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
@@ -31,14 +31,8 @@ struct law_entry law_table[] = {
 #if !defined(CONFIG_SPD_EEPROM)
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1),
 #endif
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
 	SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2),
 	SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_1)
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index 8abd917..e1ccff8 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -213,78 +213,44 @@ config_table:pci_mpc86xxcts_config_table
 };
 #endif /* CONFIG_PCI */
 
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif
-
-#ifdef CONFIG_PCIE2
-static struct pci_controller pcie2_hose;
-#endif
+static const char *slot_names[] = {
+	[PCIE1] = "ULI",
+	[PCIE2] = "Slot 1",
+};
+ 
+const char *board_serdes_name(enum srds_prtcl device)
+{
+	return slot_names[device];
+}
 
 void pci_init_board(void)
 {
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
 	volatile ccsr_gur_t *gur = &immap->im_gur;
-	struct fsl_pci_info pci_info[3];
+	struct fsl_pci_info pci_info;
 	u32 devdisr, pordevsr;
-	int first_free_busno = 0;
-	int num = 0;
-
-	int pci_agent, pcie_ep, pcie_configured;
+	int first_free_busno;
+	int pci_agent;
 
 	devdisr = in_be32(&gur->devdisr);
 	pordevsr = in_be32(&gur->pordevsr);
 
-#ifdef CONFIG_PCIE1
-	pcie_configured = is_serdes_configured(PCIE1);
-
-	if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)){
-		SET_STD_PCIE_INFO(pci_info[num], 1);
-		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-		printf("PCIE1: connected to ULI as %s (base addr %lx)\n",
-			pcie_ep ? "Endpoint" : "Root Complex",
-			pci_info[num].regs);
-
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie1_hose, first_free_busno);
-	} else {
-		printf("PCIE1: disabled\n");
-	}
-
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE1); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE2
-	pcie_configured = is_serdes_configured(PCIE2);
-
-	if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)){
-		SET_STD_PCIE_INFO(pci_info[num], 2);
-		pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
-		printf("PCIE2: connected to Slot as %s (base addr %lx)\n",
-			pcie_ep ? "Endpoint" : "Root Complex",
-			pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie2_hose, first_free_busno);
-	} else {
-		printf("PCIE2: disabled\n");
-	}
-
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE2); /* disable */
-#endif
+	first_free_busno = fsl_pcie_init_board(0);
 
 #ifdef CONFIG_PCI1
 	if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
-		SET_STD_PCI_INFO(pci_info[num], 1);
-		pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
+		SET_STD_PCI_INFO(pci_info, 1);
+		set_next_law(pci_info.mem_phys,
+			law_size_bits(pci_info.mem_size), pci_info.law);
+		set_next_law(pci_info.io_phys,
+			law_size_bits(pci_info.io_size), pci_info.law);
+
+		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
 		printf("PCI: connected to PCI slots as %s" \
 			" (base address %lx)\n",
 			pci_agent ? "Agent" : "Host",
-			pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+			pci_info.regs);
+		first_free_busno = fsl_pci_init_port(&pci_info,
 					&pci1_hose, first_free_busno);
 	} else {
 		printf("PCI: disabled\n");
@@ -294,6 +260,8 @@ void pci_init_board(void)
 #else
 	setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */
 #endif
+
+	fsl_pcie_init_board(first_free_busno);
 }
 
 #if defined(CONFIG_OF_BOARD_SETUP)
-- 
1.6.0.6

[U-Boot] [PATCH 14/15] powerpc/86xx: Rework SBC8641 pci_init_board to use common FSL PCIe code

[Kumar Gala]

Remove duplicated code in SBC8641 board and utliize the common
fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
CC: Paul Gortmaker <paul.gortmaker@windriver.com>
---
 board/sbc8641d/law.c      |    4 ---
 board/sbc8641d/sbc8641d.c |   63 +-------------------------------------------
 2 files changed, 2 insertions(+), 65 deletions(-)

diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c
index 705e1c2..a6f60ee 100644
--- a/board/sbc8641d/law.c
+++ b/board/sbc8641d/law.c
@@ -49,11 +49,7 @@ struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
 		 LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
 #endif
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
 	SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
 	SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
 };
diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c
index 5ee8f73..5c30b26 100644
--- a/board/sbc8641d/sbc8641d.c
+++ b/board/sbc8641d/sbc8641d.c
@@ -181,70 +181,11 @@ long int fixed_sdram (void)
  * Initialize PCI Devices, report devices found.
  */
 
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_fsl86xxads_config_table[] = {
-	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-	 PCI_IDSEL_NUMBER, PCI_ANY_ID,
-	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
-				     PCI_ENET0_MEMADDR,
-				     PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
-	{}
-};
-#endif
-
-static struct pci_controller pcie1_hose = {
-#ifndef CONFIG_PCI_PNP
-	config_table:pci_mpc86xxcts_config_table
-#endif
-};
-#endif /* CONFIG_PCI */
-
-#ifdef CONFIG_PCIE2
-static struct pci_controller pcie2_hose;
-#endif	/* CONFIG_PCIE2 */
-
-int first_free_busno = 0;
-
 void pci_init_board(void)
 {
-	struct fsl_pci_info pci_info[2];
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	uint devdisr = in_be32(&gur->devdisr);
-	int pcie_ep;
-	int num = 0;
-
-#ifdef CONFIG_PCIE1
-	int pcie_configured = is_serdes_configured(PCIE1);
-
-	if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
-		SET_STD_PCIE_INFO(pci_info[num], 1);
-		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-		printf("PCIE1: connected as %s (base addr %lx)\n",
-			pcie_ep ? "Endpoint" : "Root Complex",
-			pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie1_hose, first_free_busno);
-	} else {
-		puts("PCIE1: disabled\n");
-	}
-#else
-	puts("PCIE1: disabled\n");
-#endif /* CONFIG_PCIE1 */
-
-#ifdef CONFIG_PCIE2
-
-	SET_STD_PCIE_INFO(pci_info[num], 2);
-	pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
-	printf("PCIE2: connected as %s (base addr %lx)\n",
-		pcie_ep ? "Endpoint" : "Root Complex",
-		pci_info[num].regs);
-	first_free_busno = fsl_pci_init_port(&pci_info[num++],
-				&pcie2_hose, first_free_busno);
-#else
-	puts("PCIE2: disabled\n");
-#endif /* CONFIG_PCIE2 */
+	fsl_pcie_init_board(0);
 }
+#endif /* CONFIG_PCI */
 
 
 #if defined(CONFIG_OF_BOARD_SETUP)
-- 
1.6.0.6

[U-Boot] [PATCH 15/15] powerpc/85xx: Rework SBC8548 pci_init_board to use common FSL PCIe code

[Kumar Gala]

Remove duplicated code in SBC8548 board and utliize the common
fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
CC: Paul Gortmaker <paul.gortmaker@windriver.com>
---
 board/sbc8548/law.c     |    8 -------
 board/sbc8548/sbc8548.c |   50 ++++++++++++----------------------------------
 2 files changed, 13 insertions(+), 45 deletions(-)

diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c
index 6d1efc0..5fa9db0 100644
--- a/board/sbc8548/law.c
+++ b/board/sbc8548/law.c
@@ -50,14 +50,6 @@ struct law_entry law_table[] = {
 #ifndef CONFIG_SPD_EEPROM
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
 #endif
-#ifdef CONFIG_SYS_PCI1_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI),
-#endif
-#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
-#endif
 	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
 	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 };
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 06c1eea..f0e591b 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -310,33 +310,19 @@ long int fixed_sdram (void)
 static struct pci_controller pci1_hose;
 #endif	/* CONFIG_PCI1 */
 
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif	/* CONFIG_PCIE1 */
-
-
 #ifdef CONFIG_PCI
 void
 pci_init_board(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	struct fsl_pci_info pci_info[2];
-	u32 devdisr, pordevsr, porpllsr, io_sel;
 	int first_free_busno = 0;
-	int num = 0;
-
-#ifdef CONFIG_PCIE1
-	int pcie_configured;
-#endif
-
-	devdisr = in_be32(&gur->devdisr);
-	pordevsr = in_be32(&gur->pordevsr);
-	porpllsr = in_be32(&gur->porpllsr);
-	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
-
-	debug("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
 
 #ifdef CONFIG_PCI1
+	struct fsl_pci_info pci_info;
+	u32 devdisr = in_be32(&gur->devdisr);
+	u32 pordevsr = in_be32(&gur->pordevsr);
+	u32 porpllsr = in_be32(&gur->porpllsr);
+
 	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
 		uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
 		uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
@@ -350,8 +336,13 @@ pci_init_board(void)
 			pci_clk_sel ? "sync" : "async",
 			pci_arb ? "arbiter" : "external-arbiter");
 
-		SET_STD_PCI_INFO(pci_info[num], 1);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+		SET_STD_PCI_INFO(pci_info, 1);
+		set_next_law(pci_info.mem_phys,
+			law_size_bits(pci_info.mem_size), pci_info.law);
+		set_next_law(pci_info.io_phys,
+			law_size_bits(pci_info.io_size), pci_info.law);
+
+		first_free_busno = fsl_pci_init_port(&pci_info,
 					&pci1_hose, first_free_busno);
 	} else {
 		printf("PCI: disabled\n");
@@ -364,22 +355,7 @@ pci_init_board(void)
 
 	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
 
-#ifdef CONFIG_PCIE1
-	pcie_configured = is_serdes_configured(PCIE1);
-
-	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
-		SET_STD_PCIE_INFO(pci_info[num], 1);
-		printf("PCIE: base address %lx\n", pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie1_hose, first_free_busno);
-	} else {
-		printf("PCIE: disabled\n");
-	}
-
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
-#endif
+	fsl_pcie_init_board(first_free_busno);
 }
 #endif
 
-- 
1.6.0.6

[U-Boot] [PATCH 08/15] powerpc/8xxx: Rework XES boards pci_init_board to use common FSL PCIe code

[Peter Tyser]

Thanks for the cleanup.  What branch should this series be applied to?
And are there prerequisites?  I'm having issues applying them to test
and review.

On Fri, 2010-12-17 at 17:50 -0600, Kumar Gala wrote:
> Remove duplicated code in MPC8572 DS board and utliize the common
> fsl_pcie_init_board().

Looks like a copy/paste from the MPC8572.

On all the patches in the series s/utliize/utilize/.

<snip>

> --- a/board/xes/common/fsl_8xxx_pci.c
> +++ b/board/xes/common/fsl_8xxx_pci.c
> @@ -34,15 +34,6 @@
>  #ifdef CONFIG_PCI1
>  static struct pci_controller pci1_hose;
>  #endif

Is there a reason PCI1 wasn't changed over too?  I see pci1_hose is
still referenced below, but other boards with a PCI1 don't use similar
code.

> -#ifdef CONFIG_PCIE1
> -static struct pci_controller pcie1_hose;
> -#endif
> -#ifdef CONFIG_PCIE2
> -static struct pci_controller pcie2_hose;
> -#endif
> -#ifdef CONFIG_PCIE3
> -static struct pci_controller pcie3_hose;
> -#endif

<snip>

> diff --git a/board/xes/xpedite520x/law.c b/board/xes/xpedite520x/law.c
> index bbfcb9d..3afb3ae 100644
> --- a/board/xes/xpedite520x/law.c
> +++ b/board/xes/xpedite520x/law.c
> @@ -38,10 +38,6 @@ struct law_entry law_table[] = {
>  	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
>  	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
>  	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
> -#if CONFIG_SYS_PCI1_MEM_PHYS
> -	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCI_1),
> -	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_1),
> -#endif
>  #if CONFIG_SYS_PCI2_MEM_PHYS
>  	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2),
>  	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_2),

The PCI2 law can be removed too.  Its not currently used on any boards
supported by mainline U-Boot.

Thanks,
Peter

[U-Boot] [PATCH 08/15] powerpc/8xxx: Rework XES boards pci_init_board to use common FSL PCIe code

[Kumar Gala]

On Dec 20, 2010, at 10:49 AM, Peter Tyser wrote:

> Thanks for the cleanup.  What branch should this series be applied to?
> And are there prerequisites?  I'm having issues applying them to test
> and review.
> 
> On Fri, 2010-12-17 at 17:50 -0600, Kumar Gala wrote:
>> Remove duplicated code in MPC8572 DS board and utliize the common
>> fsl_pcie_init_board().
> 
> Looks like a copy/paste from the MPC8572.
> 
> On all the patches in the series s/utliize/utilize/.
> 
> <snip>

Will fix, oops ;)

> 
>> --- a/board/xes/common/fsl_8xxx_pci.c
>> +++ b/board/xes/common/fsl_8xxx_pci.c
>> @@ -34,15 +34,6 @@
>> #ifdef CONFIG_PCI1
>> static struct pci_controller pci1_hose;
>> #endif
> 
> Is there a reason PCI1 wasn't changed over too?  I see pci1_hose is
> still referenced below, but other boards with a PCI1 don't use similar
> code.

I was trying to limit how much clean up I did so left this to just PCIe interfaces.  Normal PCI and PCI-X is something I might get around to but one thing at a time

> 
>> -#ifdef CONFIG_PCIE1
>> -static struct pci_controller pcie1_hose;
>> -#endif
>> -#ifdef CONFIG_PCIE2
>> -static struct pci_controller pcie2_hose;
>> -#endif
>> -#ifdef CONFIG_PCIE3
>> -static struct pci_controller pcie3_hose;
>> -#endif
> 
> <snip>
> 
>> diff --git a/board/xes/xpedite520x/law.c b/board/xes/xpedite520x/law.c
>> index bbfcb9d..3afb3ae 100644
>> --- a/board/xes/xpedite520x/law.c
>> +++ b/board/xes/xpedite520x/law.c
>> @@ -38,10 +38,6 @@ struct law_entry law_table[] = {
>> 	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
>> 	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
>> 	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
>> -#if CONFIG_SYS_PCI1_MEM_PHYS
>> -	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCI_1),
>> -	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_1),
>> -#endif
>> #if CONFIG_SYS_PCI2_MEM_PHYS
>> 	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2),
>> 	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_2),
> 
> The PCI2 law can be removed too.  Its not currently used on any boards
> supported by mainline U-Boot.

Ok, will remove in updated patch

- k

[U-Boot] [PATCH 08/15] powerpc/8xxx: Rework XES boards pci_init_board to use common FSL PCIe code

[Peter Tyser]

On Tue, 2010-12-21 at 11:49 -0600, Kumar Gala wrote:
> On Dec 20, 2010, at 10:49 AM, Peter Tyser wrote:
> 
> > Thanks for the cleanup.  What branch should this series be applied to?
> > And are there prerequisites?  I'm having issues applying them to test
> > and review.

Any direction on how these should be applied for testing?

<snip>

> >> --- a/board/xes/common/fsl_8xxx_pci.c
> >> +++ b/board/xes/common/fsl_8xxx_pci.c
> >> @@ -34,15 +34,6 @@
> >> #ifdef CONFIG_PCI1
> >> static struct pci_controller pci1_hose;
> >> #endif
> > 
> > Is there a reason PCI1 wasn't changed over too?  I see pci1_hose is
> > still referenced below, but other boards with a PCI1 don't use similar
> > code.
> 
> I was trying to limit how much clean up I did so left this to just PCIe interfaces.  Normal PCI and PCI-X is something I might get around to but one thing at a time

Ah, OK.  If we're removing the LAW entries for PCI1 in law.c below, how
is a LAW being set for PCI1?  It looks like PCIe laws are set in
fsl_configure_pcie(), and PCI LAWs are set via set_next_law() in
board-specific code?  I'm not seeing the call to set_next_law() in X-ES
board specific code after this change though.

Best,
Peter

> > <snip>
> > 
> >> diff --git a/board/xes/xpedite520x/law.c b/board/xes/xpedite520x/law.c
> >> index bbfcb9d..3afb3ae 100644
> >> --- a/board/xes/xpedite520x/law.c
> >> +++ b/board/xes/xpedite520x/law.c
> >> @@ -38,10 +38,6 @@ struct law_entry law_table[] = {
> >> 	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
> >> 	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
> >> 	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
> >> -#if CONFIG_SYS_PCI1_MEM_PHYS
> >> -	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCI_1),
> >> -	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_1),
> >> -#endif
> >> #if CONFIG_SYS_PCI2_MEM_PHYS
> >> 	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2),
> >> 	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_2),

[U-Boot] [PATCH 08/15] powerpc/8xxx: Rework XES boards pci_init_board to use common FSL PCIe code

[Kumar Gala]

On Dec 21, 2010, at 2:23 PM, Peter Tyser wrote:

> On Tue, 2010-12-21 at 11:49 -0600, Kumar Gala wrote:
>> On Dec 20, 2010, at 10:49 AM, Peter Tyser wrote:
>> 
>>> Thanks for the cleanup.  What branch should this series be applied to?
>>> And are there prerequisites?  I'm having issues applying them to test
>>> and review.
> 
> Any direction on how these should be applied for testing?
> 
> <snip>

I've pushed a 'dev' branch on u-boot-85xx.git on denx.de with the current set of patches applied.

- k

[U-Boot] [PATCH 08/15] powerpc/8xxx: Rework XES boards pci_init_board to use common FSL PCIe code

[Kumar Gala]

On Dec 21, 2010, at 2:23 PM, Peter Tyser wrote:

> 
> Ah, OK.  If we're removing the LAW entries for PCI1 in law.c below, how
> is a LAW being set for PCI1?  It looks like PCIe laws are set in
> fsl_configure_pcie(), and PCI LAWs are set via set_next_law() in
> board-specific code?  I'm not seeing the call to set_next_law() in X-ES
> board specific code after this change though.
> 
> Best,
> Peter

Yep, that was missing, will fix ;)

- k

[U-Boot] [PATCH 08/15] powerpc/8xxx: Rework XES boards pci_init_board to use common FSL PCIe code

[Peter Tyser]

> > Any direction on how these should be applied for testing?
> > 
> > <snip>
> 
> I've pushed a 'dev' branch on u-boot-85xx.git on denx.de with the current set of patches applied.

Thanks.  Things are much tidier now.  I had a few comments.  Let me know
if you'd like me to submit patches to address any of them.

* There's a large chunk of defines that are no longer needed in the X-ES
board code:

--- a/board/xes/common/fsl_8xxx_pci.c
+++ b/board/xes/common/fsl_8xxx_pci.c
@@ -35,29 +35,6 @@
 static struct pci_controller pci1_hose;
 #endif
 
-/*
- * 85xx and 86xx share naming conventions, but different layout.
- * Correlate names to CPU-specific values to share common
- * PCI code.
- */
-#if defined(CONFIG_MPC85xx)
-#define MPC8xxx_DEVDISR_PCIE1          MPC85xx_DEVDISR_PCIE
-#define MPC8xxx_DEVDISR_PCIE2          MPC85xx_DEVDISR_PCIE2
-#define MPC8xxx_DEVDISR_PCIE3          MPC85xx_DEVDISR_PCIE3
-#define MPC8xxx_PORDEVSR_IO_SEL                MPC85xx_PORDEVSR_IO_SEL
-#define MPC8xxx_PORDEVSR_IO_SEL_SHIFT  MPC85xx_PORDEVSR_IO_SEL_SHIFT
-#define MPC8xxx_PORBMSR_HA             MPC85xx_PORBMSR_HA
-#define MPC8xxx_PORBMSR_HA_SHIFT       MPC85xx_PORBMSR_HA_SHIFT
-#elif defined(CONFIG_MPC86xx)
-#define MPC8xxx_DEVDISR_PCIE1          MPC86xx_DEVDISR_PCIEX1
-#define MPC8xxx_DEVDISR_PCIE2          MPC86xx_DEVDISR_PCIEX2
-#define MPC8xxx_DEVDISR_PCIE3          0       /* 8641 doesn't have PCIe3 */
-#define MPC8xxx_PORDEVSR_IO_SEL                MPC8641_PORDEVSR_IO_SEL
-#define MPC8xxx_PORDEVSR_IO_SEL_SHIFT  MPC8641_PORDEVSR_IO_SEL_SHIFT
-#define MPC8xxx_PORBMSR_HA             MPC8641_PORBMSR_HA
-#define MPC8xxx_PORBMSR_HA_SHIFT       MPC8641_PORBMSR_HA_SHIFT
-#endif
-
 void pci_init_board(void)
 {
        int first_free_busno = 0;



* It'd be nice if boards didn't have to define board_serdes_name(), or
at least a sane print statement was used if it wasn't.  When I booted an
X-ES board the first time I got:
PCIE1: connected to <NULL> as Endpoint (base addr ef008000)
PCIE1: Bus 00 - 00
PCIE2: connected to <NULL> as Endpoint (base addr ef009000)
PCIE2: Bus 01 - 01

Other boards will have the same issue.  Something like the following?:
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -526,8 +526,8 @@ int fsl_configure_pcie(struct fsl_pci_info *info,
        set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
        set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
        is_endpoint = fsl_setup_hose(hose, info->regs);
-       printf("PCIE%u: connected to %s as %s (base addr %lx)\n",
-              info->pci_num, connected,
+       printf("PCIE%u: connected%s%s as %s (base addr %lx)\n",
+              info->pci_num, connected ? " to " : "", connected ? connected : "",
               is_endpoint ? "Endpoint" : "Root Complex", info->regs);
        return fsl_pci_init_port(info, hose, busno);
 }


* Lastly, what about using a new define to specify the PCIe port's name
instead of making each board add a board_serdes_name() function?  This
reduces each board directory's clutter and makes it so all PCIe-related
configuration and naming occurs in the board's config.h file.  As an
example that uses the xpedite517x and mpc8572ds:
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -149,17 +149,6 @@ phys_size_t fixed_sdram (void)
 #endif
 
 #ifdef CONFIG_PCI
-static const char *slot_names[] = {
-       [PCIE1] = "Slot 2",
-       [PCIE2] = "Slot 1",
-       [PCIE3] = "ULI",
-};
-
-const char *board_serdes_name(enum srds_prtcl device)
-{
-       return slot_names[device];
-}
-
 void pci_init_board(void)
 {
        struct pci_controller *hose;
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -558,7 +558,26 @@ int fsl_configure_pcie(struct fsl_pci_info *info,
 /* Implement a dummy function for those platforms w/o SERDES */
 static const char *__board_serdes_name(enum srds_prtcl device)
 {
-       return NULL;
+       switch (device) {
+#ifdef CONFIG_SYS_PCIE1_NAME
+       case PCIE1:
+               return CONFIG_SYS_PCIE1_NAME;
+#endif
+#ifdef CONFIG_SYS_PCIE2_NAME
+       case PCIE2:
+               return CONFIG_SYS_PCIE2_NAME;
+#endif
+#ifdef CONFIG_SYS_PCIE3_NAME
+       case PCIE3:
+               return CONFIG_SYS_PCIE3_NAME;
+#endif
+#ifdef CONFIG_SYS_PCIE4_NAME
+       case PCIE4:
+               return CONFIG_SYS_PCIE4_NAME;
+#endif
+       default:
+               return NULL;
+       }
 }
 
 __attribute__((weak, alias("__board_serdes_name"))) const char *
--- a/include/configs/xpedite517x.h
+++ b/include/configs/xpedite517x.h
@@ -347,6 +347,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xe8000000
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00800000      /* 8M */
+#define CONFIG_SYS_PCIE1_NAME          "PEX8518 Switch"
 
 /* PCIE2 - VPX P1 */
 #define CONFIG_SYS_PCIE2_MEM_BUS       0xc0000000
@@ -355,6 +356,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS       0xe8800000
 #define CONFIG_SYS_PCIE2_IO_SIZE       0x00800000      /* 8M */
+#define CONFIG_SYS_PCIE2_NAME          "VPX Fabric A"
 
 /*
  * Networking options
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -485,6 +485,7 @@
 #define CONFIG_SYS_PCIE3_IO_PHYS       0xffc00000
 #endif
 #define CONFIG_SYS_PCIE3_IO_SIZE       0x00010000      /* 64k */
+#define CONFIG_SYS_PCIE3_NAME          "ULI"
 
 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 #define CONFIG_SYS_PCIE2_MEM_VIRT      0xa0000000
@@ -504,6 +505,7 @@
 #define CONFIG_SYS_PCIE2_IO_PHYS       0xffc10000
 #endif
 #define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
+#define CONFIG_SYS_PCIE2_NAME          "Slot 1"
 
 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT      0xc0000000
@@ -523,6 +525,7 @@
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xffc20000
 #endif
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
+#define CONFIG_SYS_PCIE1_NAME          "Slot 2"
 
 #if defined(CONFIG_PCI)
 


Best,
Peter

[U-Boot] [PATCH 15/15] powerpc/85xx: Rework SBC8548 pci_init_board to use common FSL PCIe code

[Paul Gortmaker]

[[PATCH 15/15] powerpc/85xx: Rework SBC8548 pci_init_board to use common FSL PCIe code] On 17/12/2010 (Fri 17:50) Kumar Gala wrote:

> Remove duplicated code in SBC8548 board and utliize the common
> fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
> controllers based on which PCIe controllers are enabled.
>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> CC: Paul Gortmaker <paul.gortmaker@windriver.com>

Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>

Tested with Peter's anti-NULL patch on top of the mpc85xx dev branch.
Board has both PCI-X and PCI-e slots, with e1000 and skge respectively.

P.

-----------------------

U-Boot 2010.12-00426-ged7ea8f (Jan 06 2011 - 15:43:08)

CPU:   8548E, Version: 2.0, (0x80390020)
Core:  E500, Version: 2.0, (0x80210020)
Clock Configuration:
       CPU0:990  MHz,
       CCB:396  MHz,
       DDR:198  MHz (396 MT/s data rate), LBC:99   MHz
L1:    D-cache 32 kB enabled
       I-cache 32 kB enabled
Board: Wind River SBC8548 Rev. 0x2
I2C:   ready
DRAM:      SDRAM: 128 MiB
DDR: 256 MiB (DDR2, 64-bit, CL=4, ECC off)
       DDR Chip-Select Interleaving Mode: CS0+CS1
FLASH: 72 MiB
L2:    512 KB already enabled
*** Warning - bad CRC, using default environment

PCI: Host, 64 bit, 66 MHz, sync, arbiter
  00:01.0     - 8086:1026 - Network controller
PCI1: Bus 00 - 00

PCIe1: Root Complex, x1, regs @ 0xe000a000
  02:00.0     - 1148:9e00 - Network controller
PCIe1: Bus 01 - 02
In:    serial
Out:   serial
Err:   serial
Net:   eTSEC0, eTSEC1
Hit any key to stop autoboot:  0
=> pci 0
Scanning PCI devices on bus 0
BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
_____________________________________________________________
00.00.00   0x1057     0x0012     Processor               0x20
00.01.00   0x8086     0x1026     Network controller      0x00
=> pci 1
Scanning PCI devices on bus 1
BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
_____________________________________________________________
01.00.00   0x1957     0x0012     Processor               0x20
=> pci 2
Scanning PCI devices on bus 2
BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
_____________________________________________________________
02.00.00   0x1148     0x9e00     Network controller      0x00
=>

[U-Boot] [PATCH 01/15] powerpc/fsl-pci: Add generic code to setup PCIe controllers

[Kumar Gala]

On Dec 17, 2010, at 5:50 PM, Kumar Gala wrote:

> Since all the PCIe controllers are connected over SERDES on the SoCs we
> can utilize is_serdes_configured() to determine if a controller is
> enabled.  After which we can setup the ATMUs and LAWs for the controller
> in a common fashion and allow board code to specify what the controller
> is connected to for reporting reasons.
> 
> We also provide a per controller (rather than all) for some systems that
> may have special requirements.
> 
> Finally, we refactor the code used by the P1022DS to utilize the new
> generic code.
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/include/asm/fsl_pci.h |   10 +++
> board/freescale/p1022ds/p1022ds.c  |   67 +------------------
> drivers/pci/fsl_pci_init.c         |  127 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 139 insertions(+), 65 deletions(-)

applied to 85xx

- k

[U-Boot] [PATCH 02/15] powerpc/85xx: Rework MPC8572DS pci_init_board to use common FSL PCIe code

[Kumar Gala]

On Dec 17, 2010, at 5:50 PM, Kumar Gala wrote:

> Remove duplicated code in MPC8572DS board and utliize the common
> fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
> controllers based on which PCIe controllers are enabled.
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> board/freescale/mpc8572ds/law.c       |    8 +--
> board/freescale/mpc8572ds/mpc8572ds.c |  100 ++++++--------------------------
> 2 files changed, 20 insertions(+), 88 deletions(-)

applied to 85xx, fixed commit typo s/utliize/utilize/

* added signed off by Chenhui Zhao <b26998@freescale.com>

- k

[U-Boot] [PATCH 03/15] powerpc/85xx: Rework P2020DS pci_init_board to use common FSL PCIe code

[Kumar Gala]

On Dec 17, 2010, at 5:50 PM, Kumar Gala wrote:

> Remove duplicated code in P2020DS board and utliize the common
> fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
> controllers based on which PCIe controllers are enabled.
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> board/freescale/p2020ds/law.c     |    8 +--
> board/freescale/p2020ds/p2020ds.c |  114 ++++---------------------------------
> 2 files changed, 12 insertions(+), 110 deletions(-)

applied to 85xx, fixed commit typo s/utliize/utilize/

Added attribution to Leo Li's original P2020 DS serdes clean up patches.

- k

[U-Boot] [PATCH 04/15] powerpc/85xx: Rework MPC8544DS pci_init_board to use common FSL PCIe code

[Kumar Gala]

On Dec 17, 2010, at 5:50 PM, Kumar Gala wrote:

> Remove duplicated code in MPC8544DS board and utliize the common
> fsl_pcie_init_ctrl().  We also now dynamically setup the LAWs for PCI
> controllers based on which PCIe controllers are enabled.
> 
> We don't use the full fsl_pcie_init_ctrl() since we have to handle PCIE3
> specially to setup the additional memory map region and we utilize a
> single LAW to cover the controller.
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> board/freescale/mpc8544ds/law.c       |   10 +---
> board/freescale/mpc8544ds/mpc8544ds.c |  110 +++++++++++----------------------
> 2 files changed, 37 insertions(+), 83 deletions(-)

applied to 85xx, fixed commit typo s/utliize/utilize/

- k

[U-Boot] [PATCH 05/15] powerpc/85xx: Rework MPC8536DS pci_init_board to use common FSL PCIe code

[Kumar Gala]

On Dec 17, 2010, at 5:50 PM, Kumar Gala wrote:

> Remove duplicated code in MPC8536DS board and utliize the common
> fsl_pcie_init_board().
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> board/freescale/mpc8536ds/mpc8536ds.c |  125 ++++++--------------------------
> 1 files changed, 24 insertions(+), 101 deletions(-)

applied to 85xx, fixed commit typo s/utliize/utilize/

- k

[U-Boot] [PATCH 06/15] powerpc/86xx: Rework MPC8641HPCN pci_init_board to use common FSL PCIe code

[Kumar Gala]

On Dec 17, 2010, at 5:50 PM, Kumar Gala wrote:

> Remove duplicated code in MPC8641HPCN board and utliize the common
> fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
> controllers based on which PCIe controllers are enabled.
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> board/freescale/mpc8641hpcn/law.c         |    7 +---
> board/freescale/mpc8641hpcn/mpc8641hpcn.c |   56 +++++-----------------------
> 2 files changed, 11 insertions(+), 52 deletions(-)

applied to 85xx, fixed commit typo s/utliize/utilize/

- k

[U-Boot] [PATCH 07/15] powerpc/85xx: Rework MPC8548CDS pci_init_board to use common FSL PCIe code

[Kumar Gala]

On Dec 17, 2010, at 5:50 PM, Kumar Gala wrote:

> Remove duplicated code in MPC8548CDS board and utliize the common
> fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
> controllers based on which PCIe controllers are enabled.
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> board/freescale/mpc8548cds/law.c        |   10 +------
> board/freescale/mpc8548cds/mpc8548cds.c |   46 ++++++++++---------------------
> 2 files changed, 16 insertions(+), 40 deletions(-)

applied to 85xx, fixed commit typo s/utliize/utilize/

- k

[U-Boot] [PATCH 09/15] powerpc/85xx: Rework TQM boards pci_init_board to use common FSL PCIe code

[Kumar Gala]

On Dec 17, 2010, at 5:50 PM, Kumar Gala wrote:

> Remove duplicated code in TQM 85xx boards and utliize the common
> fsl_pcie_init_board().
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> CC: wd at denx.de
> ---
> board/tqc/tqm85xx/law.c     |    9 +--------
> board/tqc/tqm85xx/tqm85xx.c |   41 ++++++++++++-----------------------------
> 2 files changed, 13 insertions(+), 37 deletions(-)

applied to 85xx, fixed commit typo s/utliize/utilize/

- k

[U-Boot] [PATCH 10/15] powerpc/85xx: Rework MPC8568MDS pci_init_board to use common FSL PCIe code

[Kumar Gala]

On Dec 17, 2010, at 5:50 PM, Kumar Gala wrote:

> Remove duplicated code in MPC8568MDS board and utliize the common
> fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
> controllers based on which PCIe controllers are enabled.
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> board/freescale/mpc8568mds/law.c        |    6 +---
> board/freescale/mpc8568mds/mpc8568mds.c |   52 +++++++++++--------------------
> 2 files changed, 19 insertions(+), 39 deletions(-)

applied to 85xx, fixed commit typo s/utliize/utilize/

- k

[U-Boot] [PATCH 11/15] powerpc/85xx: Rework MPC8569MDS pci_init_board to use common FSL PCIe code

[Kumar Gala]

On Dec 17, 2010, at 5:50 PM, Kumar Gala wrote:

> Remove duplicated code in MPC8569MDS board and utliize the common
> fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
> controllers based on which PCIe controllers are enabled.
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> board/freescale/mpc8569mds/law.c        |    4 +--
> board/freescale/mpc8569mds/mpc8569mds.c |   44 ++++--------------------------
> 2 files changed, 7 insertions(+), 41 deletions(-)

applied to 85xx, fixed commit typo s/utliize/utilize/

- k

[U-Boot] [PATCH 12/15] powerpc/85xx: Rework P1_P2_RDB pci_init_board to use common FSL PCIe code

[Kumar Gala]

On Dec 17, 2010, at 5:50 PM, Kumar Gala wrote:

> Remove duplicated code in P1_P2_RDB boards and utliize the common
> fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
> controllers based on which PCIe controllers are enabled.
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> board/freescale/p1_p2_rdb/law.c |    6 +---
> board/freescale/p1_p2_rdb/pci.c |   64 +++++---------------------------------
> 2 files changed, 10 insertions(+), 60 deletions(-)

applied to 85xx, fixed commit typo s/utliize/utilize/

- k

[U-Boot] [PATCH 13/15] powerpc/86xx: Rework MPC8610HPCD pci_init_board to use common FSL PCIe code

[Kumar Gala]

On Dec 17, 2010, at 5:50 PM, Kumar Gala wrote:

> Remove duplicated code in MPC8610HPCD board and utliize the common
> fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
> controllers based on which PCIe controllers are enabled.
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> board/freescale/mpc8610hpcd/law.c         |    8 +---
> board/freescale/mpc8610hpcd/mpc8610hpcd.c |   80 +++++++++--------------------
> 2 files changed, 25 insertions(+), 63 deletions(-)

applied to 85xx, fixed commit typo s/utliize/utilize/

- k

[U-Boot] [PATCH 14/15] powerpc/86xx: Rework SBC8641 pci_init_board to use common FSL PCIe code

[Kumar Gala]

On Dec 17, 2010, at 5:50 PM, Kumar Gala wrote:

> Remove duplicated code in SBC8641 board and utliize the common
> fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
> controllers based on which PCIe controllers are enabled.
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> CC: Paul Gortmaker <paul.gortmaker@windriver.com>
> ---
> board/sbc8641d/law.c      |    4 ---
> board/sbc8641d/sbc8641d.c |   63 +-------------------------------------------
> 2 files changed, 2 insertions(+), 65 deletions(-)

applied to 85xx, fixed commit typo s/utliize/utilize/

- k

[U-Boot] [PATCH 15/15] powerpc/85xx: Rework SBC8548 pci_init_board to use common FSL PCIe code

[Kumar Gala]

On Dec 17, 2010, at 5:50 PM, Kumar Gala wrote:

> Remove duplicated code in SBC8548 board and utliize the common
> fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
> controllers based on which PCIe controllers are enabled.
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> CC: Paul Gortmaker <paul.gortmaker@windriver.com>
> ---
> board/sbc8548/law.c     |    8 -------
> board/sbc8548/sbc8548.c |   50 ++++++++++++----------------------------------
> 2 files changed, 13 insertions(+), 45 deletions(-)

applied to 85xx, fixed commit typo s/utliize/utilize/

- k

[U-Boot] [PATCH v2 08/15] powerpc/8xxx: Rework XES boards pci_init_board to use common FSL PCIe code

[Kumar Gala]

Remove duplicated code in MPC8xxx XES boards and utilize the common
fsl_pcie_init_board().

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
CC: Peter Tyser <ptyser@xes-inc.com>
---
* Fix commit message copy/paste issue per Peter T.
* Fixed utilize typo per Peter T.
* removed PCI2 on xpedite520x per Peter T.
* Removed duplicate/now unused MPC8xxx defines per Peter T.

 board/xes/common/fsl_8xxx_pci.c |  110 +++++----------------------------------
 board/xes/xpedite517x/law.c     |    8 ---
 board/xes/xpedite520x/law.c     |    8 ---
 board/xes/xpedite537x/law.c     |   12 ----
 board/xes/xpedite550x/law.c     |   12 ----
 5 files changed, 13 insertions(+), 137 deletions(-)

diff --git a/board/xes/common/fsl_8xxx_pci.c b/board/xes/common/fsl_8xxx_pci.c
index 4135849..28c83c7 100644
--- a/board/xes/common/fsl_8xxx_pci.c
+++ b/board/xes/common/fsl_8xxx_pci.c
@@ -34,57 +34,16 @@
 #ifdef CONFIG_PCI1
 static struct pci_controller pci1_hose;
 #endif
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif
-#ifdef CONFIG_PCIE2
-static struct pci_controller pcie2_hose;
-#endif
-#ifdef CONFIG_PCIE3
-static struct pci_controller pcie3_hose;
-#endif
-
-/*
- * 85xx and 86xx share naming conventions, but different layout.
- * Correlate names to CPU-specific values to share common
- * PCI code.
- */
-#if defined(CONFIG_MPC85xx)
-#define MPC8xxx_DEVDISR_PCIE1		MPC85xx_DEVDISR_PCIE
-#define MPC8xxx_DEVDISR_PCIE2		MPC85xx_DEVDISR_PCIE2
-#define MPC8xxx_DEVDISR_PCIE3		MPC85xx_DEVDISR_PCIE3
-#define MPC8xxx_PORDEVSR_IO_SEL		MPC85xx_PORDEVSR_IO_SEL
-#define MPC8xxx_PORDEVSR_IO_SEL_SHIFT	MPC85xx_PORDEVSR_IO_SEL_SHIFT
-#define MPC8xxx_PORBMSR_HA		MPC85xx_PORBMSR_HA
-#define MPC8xxx_PORBMSR_HA_SHIFT	MPC85xx_PORBMSR_HA_SHIFT
-#elif defined(CONFIG_MPC86xx)
-#define MPC8xxx_DEVDISR_PCIE1		MPC86xx_DEVDISR_PCIEX1
-#define MPC8xxx_DEVDISR_PCIE2		MPC86xx_DEVDISR_PCIEX2
-#define MPC8xxx_DEVDISR_PCIE3	 	0	/* 8641 doesn't have PCIe3 */
-#define MPC8xxx_PORDEVSR_IO_SEL		MPC8641_PORDEVSR_IO_SEL
-#define MPC8xxx_PORDEVSR_IO_SEL_SHIFT	MPC8641_PORDEVSR_IO_SEL_SHIFT
-#define MPC8xxx_PORBMSR_HA		MPC8641_PORBMSR_HA
-#define MPC8xxx_PORBMSR_HA_SHIFT	MPC8641_PORBMSR_HA_SHIFT
-#endif
 
 void pci_init_board(void)
 {
-	struct fsl_pci_info pci_info[3];
 	int first_free_busno = 0;
-	int num = 0;
-	int pcie_ep;
-	__maybe_unused int pcie_configured;
 
-#if defined(CONFIG_MPC85xx)
+#ifdef CONFIG_PCI1
+	int pcie_ep;
+	struct fsl_pci_info pci_info;
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#elif defined(CONFIG_MPC86xx)
-	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-#endif
 	u32 devdisr = in_be32(&gur->devdisr);
-
-#ifdef CONFIG_PCI1
-	u32 pordevsr = in_be32(&gur->pordevsr);
 	uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD;
 	uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32;
 	uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB;
@@ -92,8 +51,13 @@ void pci_init_board(void)
 	uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
 
 	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
-		SET_STD_PCI_INFO(pci_info[num], 1);
-		pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
+		SET_STD_PCI_INFO(pci_info, 1);
+		set_next_law(pci_info.mem_phys,
+			law_size_bits(pci_info.mem_size), pci_info.law);
+		set_next_law(pci_info.io_phys,
+			law_size_bits(pci_info.io_size), pci_info.law);
+
+		pcie_ep = fsl_setup_hose(&pci1_hose, pci_info.regs);
 		printf("PCI1: %d bit %s, %s %d MHz, %s, %s\n",
 			pci_32 ? 32 : 64,
 			pcix ? "PCIX" : "PCI",
@@ -102,66 +66,18 @@ void pci_init_board(void)
 			pcie_ep ? "agent" : "host",
 			pci_arb ? "arbiter" : "external-arbiter");
 
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+		first_free_busno = fsl_pci_init_port(&pci_info,
 					&pci1_hose, first_free_busno);
 	} else {
 		printf("PCI1: disabled\n");
 	}
 #elif defined CONFIG_MPC8548
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	/* PCI1 not present on MPC8572 */
 	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
 #endif
 
-#ifdef CONFIG_PCIE1
-	pcie_configured = is_serdes_configured(PCIE1);
-
-	if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) {
-		SET_STD_PCIE_INFO(pci_info[num], 1);
-		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-		printf("PCIE1: connected as %s\n",
-			pcie_ep ? "Endpoint" : "Root Complex");
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie1_hose, first_free_busno);
-	} else {
-		printf("PCIE1: disabled\n");
-	}
-#else
-	setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE1);
-#endif /* CONFIG_PCIE1 */
-
-#ifdef CONFIG_PCIE2
-	pcie_configured = is_serdes_configured(PCIE2);
-
-	if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) {
-		SET_STD_PCIE_INFO(pci_info[num], 2);
-		pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
-		printf("PCIE2: connected as %s\n",
-			pcie_ep ? "Endpoint" : "Root Complex");
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie2_hose, first_free_busno);
-	} else {
-		printf("PCIE2: disabled\n");
-	}
-#else
-	setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE2);
-#endif /* CONFIG_PCIE2 */
-
-#ifdef CONFIG_PCIE3
-	pcie_configured = is_serdes_configured(PCIE3);
-
-	if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) {
-		SET_STD_PCIE_INFO(pci_info[num], 3);
-		pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
-		printf("PCIE3: connected as %s\n",
-			pcie_ep ? "Endpoint" : "Root Complex");
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie3_hose, first_free_busno);
-	} else {
-		printf("PCIE3: disabled\n");
-	}
-#else
-	setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE3);
-#endif /* CONFIG_PCIE3 */
+	fsl_pcie_init_board(first_free_busno);
 }
 
 #if defined(CONFIG_OF_BOARD_SETUP)
diff --git a/board/xes/xpedite517x/law.c b/board/xes/xpedite517x/law.c
index 0b7d9ef..df23df1 100644
--- a/board/xes/xpedite517x/law.c
+++ b/board/xes/xpedite517x/law.c
@@ -39,14 +39,6 @@ struct law_entry law_table[] = {
 	/* NAND LAW covers 2 NAND flashes */
 	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_512K, LAW_TRGT_IF_LBC),
 #endif
-#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
-#endif
-#ifdef CONFIG_SYS_PCIE2_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2),
-#endif
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/xes/xpedite520x/law.c b/board/xes/xpedite520x/law.c
index bbfcb9d..5c1fcd2 100644
--- a/board/xes/xpedite520x/law.c
+++ b/board/xes/xpedite520x/law.c
@@ -38,14 +38,6 @@ struct law_entry law_table[] = {
 	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
 	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-#if CONFIG_SYS_PCI1_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_1),
-#endif
-#if CONFIG_SYS_PCI2_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2),
-	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_2),
-#endif
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/xes/xpedite537x/law.c b/board/xes/xpedite537x/law.c
index daee676..54c28da 100644
--- a/board/xes/xpedite537x/law.c
+++ b/board/xes/xpedite537x/law.c
@@ -37,18 +37,6 @@
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
-#endif
-#ifdef CONFIG_SYS_PCIE2_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2),
-#endif
-#ifdef CONFIG_SYS_PCIE3_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_3),
-	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_3),
-#endif
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/xes/xpedite550x/law.c b/board/xes/xpedite550x/law.c
index 4d4445d..66f1cf9 100644
--- a/board/xes/xpedite550x/law.c
+++ b/board/xes/xpedite550x/law.c
@@ -37,18 +37,6 @@
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
-#endif
-#ifdef CONFIG_SYS_PCIE2_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2),
-#endif
-#ifdef CONFIG_SYS_PCIE3_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_3),
-	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_3),
-#endif
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
-- 
1.6.0.6

[U-Boot] [PATCH v2 08/15] powerpc/8xxx: Rework XES boards pci_init_board to use common FSL PCIe code

[Kumar Gala]

On Jan 9, 2011, at 2:54 PM, Kumar Gala wrote:

> Remove duplicated code in MPC8xxx XES boards and utilize the common
> fsl_pcie_init_board().
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> CC: Peter Tyser <ptyser@xes-inc.com>
> ---
> * Fix commit message copy/paste issue per Peter T.
> * Fixed utilize typo per Peter T.
> * removed PCI2 on xpedite520x per Peter T.
> * Removed duplicate/now unused MPC8xxx defines per Peter T.
> 
> board/xes/common/fsl_8xxx_pci.c |  110 +++++----------------------------------
> board/xes/xpedite517x/law.c     |    8 ---
> board/xes/xpedite520x/law.c     |    8 ---
> board/xes/xpedite537x/law.c     |   12 ----
> board/xes/xpedite550x/law.c     |   12 ----
> 5 files changed, 13 insertions(+), 137 deletions(-)

applied to 85xx

- k