From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paul Gortmaker Date: Thu, 6 Jan 2011 16:12:09 -0500 Subject: [U-Boot] [PATCH 15/15] powerpc/85xx: Rework SBC8548 pci_init_board to use common FSL PCIe code In-Reply-To: <1292629858-10233-15-git-send-email-galak@kernel.crashing.org> References: <1292629858-10233-6-git-send-email-galak@kernel.crashing.org> <1292629858-10233-7-git-send-email-galak@kernel.crashing.org> <1292629858-10233-8-git-send-email-galak@kernel.crashing.org> <1292629858-10233-9-git-send-email-galak@kernel.crashing.org> <1292629858-10233-10-git-send-email-galak@kernel.crashing.org> <1292629858-10233-11-git-send-email-galak@kernel.crashing.org> <1292629858-10233-12-git-send-email-galak@kernel.crashing.org> <1292629858-10233-13-git-send-email-galak@kernel.crashing.org> <1292629858-10233-14-git-send-email-galak@kernel.crashing.org> <1292629858-10233-15-git-send-email-galak@kernel.crashing.org> Message-ID: <20110106211208.GD20843@windriver.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de [[PATCH 15/15] powerpc/85xx: Rework SBC8548 pci_init_board to use common FSL PCIe code] On 17/12/2010 (Fri 17:50) Kumar Gala wrote: > Remove duplicated code in SBC8548 board and utliize the common > fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI > controllers based on which PCIe controllers are enabled. > > Signed-off-by: Kumar Gala > CC: Paul Gortmaker Tested-by: Paul Gortmaker Tested with Peter's anti-NULL patch on top of the mpc85xx dev branch. Board has both PCI-X and PCI-e slots, with e1000 and skge respectively. P. ----------------------- U-Boot 2010.12-00426-ged7ea8f (Jan 06 2011 - 15:43:08) CPU: 8548E, Version: 2.0, (0x80390020) Core: E500, Version: 2.0, (0x80210020) Clock Configuration: CPU0:990 MHz, CCB:396 MHz, DDR:198 MHz (396 MT/s data rate), LBC:99 MHz L1: D-cache 32 kB enabled I-cache 32 kB enabled Board: Wind River SBC8548 Rev. 0x2 I2C: ready DRAM: SDRAM: 128 MiB DDR: 256 MiB (DDR2, 64-bit, CL=4, ECC off) DDR Chip-Select Interleaving Mode: CS0+CS1 FLASH: 72 MiB L2: 512 KB already enabled *** Warning - bad CRC, using default environment PCI: Host, 64 bit, 66 MHz, sync, arbiter 00:01.0 - 8086:1026 - Network controller PCI1: Bus 00 - 00 PCIe1: Root Complex, x1, regs @ 0xe000a000 02:00.0 - 1148:9e00 - Network controller PCIe1: Bus 01 - 02 In: serial Out: serial Err: serial Net: eTSEC0, eTSEC1 Hit any key to stop autoboot: 0 => pci 0 Scanning PCI devices on bus 0 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 00.00.00 0x1057 0x0012 Processor 0x20 00.01.00 0x8086 0x1026 Network controller 0x00 => pci 1 Scanning PCI devices on bus 1 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 01.00.00 0x1957 0x0012 Processor 0x20 => pci 2 Scanning PCI devices on bus 2 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 02.00.00 0x1148 0x9e00 Network controller 0x00 =>