From mboxrd@z Thu Jan  1 00:00:00 1970
From: Scott Wood <scottwood@freescale.com>
Date: Tue, 15 Mar 2011 11:11:32 -0500
Subject: [U-Boot] p4080ds starts OS with MSR[EE]=1 and DEC armed?
In-Reply-To: <977C59AE-9AB2-4B92-B508-C057CB172F0C@kernel.crashing.org>
References: <E6A7C97E-09F9-4466-A0BF-8BA364787C78@watson.ibm.com>
	<6EC57A52-1C75-4F1A-8A43-90A06BB6D11B@kernel.crashing.org>
	<20110314130917.718704bf@schlenkerla>
	<67FE1774-18F0-4EC6-B4C0-51A0A7A7FAE2@kernel.crashing.org>
	<20110314163735.165fd1d5@schlenkerla>
	<977C59AE-9AB2-4B92-B508-C057CB172F0C@kernel.crashing.org>
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On Tue, 15 Mar 2011 00:39:17 -0500
Kumar Gala <galak@kernel.crashing.org> wrote:

> diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
> index 48a82ed..a6d1e99 100644
> --- a/cpu/mpc85xx/cpu_init.c
> +++ b/cpu/mpc85xx/cpu_init.c
> @@ -364,5 +364,16 @@ extern void setup_ivors(void);
>  
>  void arch_preboot_os(void)
>  {
> +       u32 msr;
> +
> +       /*
> +        * We are changing interrupt offsets and are about to boot the OS so
> +        * we need to make sure we disable all async interrupts. EE is already
> +        * disabled by the time we get called.
> +        */
> +       msr = mfmsr();
> +       msr &= ~(MSR_ME|MSR_CE|MSR_DE);
> +       mtmsr(msr);
> +
>         setup_ivors();
>  }
> 
> -----
> 
> :)

Ah, thanks.  Not sure why my previous grep found the other one but not
this. :-)

-Scott