From mboxrd@z Thu Jan 1 00:00:00 1970 From: Wolfgang Denk Date: Sat, 23 Apr 2011 20:45:34 +0200 Subject: [U-Boot] [PATCH] powerpc/85xx: Change timebase divisor to be defined per processor In-Reply-To: <54CE1181-5449-4FBF-9402-DF5D4E99E4CE@kernel.crashing.org> References: <1303412373-11991-1-git-send-email-galak@kernel.crashing.org> <54CE1181-5449-4FBF-9402-DF5D4E99E4CE@kernel.crashing.org> Message-ID: <20110423184534.8DAFCD5269D@gemini.denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Dear Kumar Gala, In message <54CE1181-5449-4FBF-9402-DF5D4E99E4CE@kernel.crashing.org> you wrote: > > On Apr 22, 2011, at 6:50 AM, Tabi Timur-B04825 wrote: > > > On Thu, Apr 21, 2011 at 1:59 PM, Kumar Gala wrote: > >> Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms because > >> different SoCs have different divisor amounts. All the PQ3 parts are > >> /8, the P4080/P4080 is /16, and P2040/P3041/P5020 are /32. > > > > Shouldn't there also be a README update to document this option? > > I think its self evident what it is. Please fix it. > >> + unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV; > >> + > >> + return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div; > > > > Why not just: > > > > return (gd->bus_clk + (CONFIG_SYS_FSL_TBCLK_DIV / 2)) / > > CONFIG_SYS_FSL_TBCLK_DIV; > > It was done this way to deal w/line wrapping. Now this is really a _very_ strange argument. Please fix as well. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de "The best index to a person's character is a) how he treats people who can't do him any good and b) how he treats people who can't fight back." - Abigail Van Buren