[U-Boot] [PATCH] ARM: i.MX51: Config option to disable PLL1

[U-Boot] [PATCH] ARM: i.MX51: Config option to disable PLL1

[David Jander]

i.MX51 PLL1 seems to have stability problems. It is advised to not use it,
although it is unclear whether all boards and/or chip revisions have this
problem. Using PLL2 for the core and DDR2 seems to fix the problem.
No official errata yet.

Signed-off-by: David Jander <david@protonic.nl>
---
 arch/arm/cpu/armv7/mx5/lowlevel_init.S |   16 ++++++++++++++++
 1 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index 96ebfe2..e1d6c35 100644
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -153,7 +153,11 @@
 	mov r1, #0x4
 	str r1, [r0, #CLKCTL_CCSR]
 
+#if defined(CONFIG_MX51_AVOID_PLL1)
+	setup_pll PLL1_BASE_ADDR, 216
+#else
 	setup_pll PLL1_BASE_ADDR, 800
+#endif
 
 #if defined(CONFIG_MX51)
 	setup_pll PLL3_BASE_ADDR, 665
@@ -165,7 +169,11 @@
 	str r1, [r0, #CLKCTL_CBCMR]
 	ldr r1, =0x13239145
 	str r1, [r0, #CLKCTL_CBCDR]
+#if defined(CONFIG_MX51_AVOID_PLL1)
+	setup_pll PLL2_BASE_ADDR, 800
+#else
 	setup_pll PLL2_BASE_ADDR, 665
+#endif
 
 	/* Switch peripheral to PLL2 */
 	ldr r0, =CCM_BASE_ADDR
@@ -197,7 +205,11 @@
 #endif
 	str r1, [r0, #CLKCTL_CACRR]
 	/* Switch ARM back to PLL 1 */
+#if defined(CONFIG_MX51_AVOID_PLL1)
+	mov r1, #0x00000104 /* Set ARM/DDR to PLL2 */
+#else
 	mov r1, #0
+#endif
 	str r1, [r0, #CLKCTL_CCSR]
 
 #if defined(CONFIG_MX51)
@@ -228,7 +240,11 @@
 	/* Use PLL 2 for UART's, get 66.5MHz from it */
 	ldr r1, =0xA5A2A020
 	str r1, [r0, #CLKCTL_CSCMR1]
+#if defined(CONFIG_MX51_AVOID_PLL1)
+	ldr r1, =0x0104041a /* Adjust dividers for 800MHz on PLL2 */
+#else
 	ldr r1, =0x00C30321
+#endif
 	str r1, [r0, #CLKCTL_CSCDR1]
 #elif defined(CONFIG_MX53)
 	ldr r1, [r0, #CLKCTL_CSCDR1]
-- 
1.7.4.1

[U-Boot] [PATCH] ARM: i.MX51: Config option to disable PLL1

[David Jander]

On Thu, 26 May 2011 19:00:14 +0200
David Jander <david@protonic.nl> wrote:

> i.MX51 PLL1 seems to have stability problems. It is advised to not use it,
> although it is unclear whether all boards and/or chip revisions have this
> problem. Using PLL2 for the core and DDR2 seems to fix the problem.
> No official errata yet.

Forgot to mention this in the commit message:

All boards that need this fix (all of them?) should change their board config
header file to include this:

#define CONFIG_MX51_AVOID_PLL1

...

#ifdef CONFIG_MX51_AVOID_PLL1
#define CONFIG_SYS_CLKTL_CBCDR  0x59EC7580
#else
#define CONFIG_SYS_CLKTL_CBCDR	0x59E35100
#endif

This is the case for mx51evk.h, and the exact value of CONFIG_SYS_CLKTL_CBCDR
may vary depending on crystal frequency, type of RAM, NFC clocks, etc...

I would like to have some feedback before resubmitting the patch with the
amended commit message. I would also like to know whether I should include
another patch fixing all affected board-config headers? I guess this should be
decided by the respective maintainers, since this requires fixing the linux
kernel clock driver also...

Beste regards,

-- 
David Jander
Protonic Holland.

[U-Boot] [PATCH] ARM: i.MX51: Config option to disable PLL1

[Stefano Babic]

On 05/26/2011 07:00 PM, David Jander wrote:
> i.MX51 PLL1 seems to have stability problems. It is advised to not use it,
> although it is unclear whether all boards and/or chip revisions have this
> problem. Using PLL2 for the core and DDR2 seems to fix the problem.
> No official errata yet.
> 

Hi David,

do you get some info from Freescale's FAE ? Is this issue strictly
related to the processor or can be board related ?

I hope someone from Freescale can help us to understand this issue.

> Signed-off-by: David Jander <david@protonic.nl>
> ---
>  arch/arm/cpu/armv7/mx5/lowlevel_init.S |   16 ++++++++++++++++
>  1 files changed, 16 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
> index 96ebfe2..e1d6c35 100644
> --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
> +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
> @@ -153,7 +153,11 @@
>  	mov r1, #0x4
>  	str r1, [r0, #CLKCTL_CCSR]
>  
> +#if defined(CONFIG_MX51_AVOID_PLL1)

If you add a new CONFIG_, you must document it in the README file.

Rather I cannot get a better feedback, I do not know this issue on the
i.MX51. As you reported, it seems still unclear what happens.

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH] ARM: i.MX51: Config option to disable PLL1

[Stefano Babic]

On 05/26/2011 07:45 PM, David Jander wrote:
> On Thu, 26 May 2011 19:00:14 +0200
> David Jander <david@protonic.nl> wrote:
> 

Hi David,

> I would like to have some feedback before resubmitting the patch with the
> amended commit message. I would also like to know whether I should include
> another patch fixing all affected board-config headers?

No, I do not think so. Responsibility for some changes is put on the
board maintainer.

> I guess this should be
> decided by the respective maintainers, since this requires fixing the linux
> kernel clock driver also...

Agree.

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH] ARM: i.MX51: Config option to disable PLL1

[David Jander]

On Fri, 27 May 2011 12:13:32 +0200
Stefano Babic <sbabic@denx.de> wrote:

> On 05/26/2011 07:00 PM, David Jander wrote:
> > i.MX51 PLL1 seems to have stability problems. It is advised to not use it,
> > although it is unclear whether all boards and/or chip revisions have this
> > problem. Using PLL2 for the core and DDR2 seems to fix the problem.
> > No official errata yet.
> > 
> 
> Hi David,
> 
> do you get some info from Freescale's FAE ?

Yes.

> Is this issue strictly
> related to the processor or can be board related ?

AFAIK, this issue could also be board-related. In other words, if one designs
a board that powers vpll* from a higher voltage than nominal mentioned
in the datasheet, chances could be lower.

> I hope someone from Freescale can help us to understand this issue.

I think I already know quite a lot about it (feel free to ask me off-list).

> > Signed-off-by: David Jander <david@protonic.nl>
> > ---
> >  arch/arm/cpu/armv7/mx5/lowlevel_init.S |   16 ++++++++++++++++
> >  1 files changed, 16 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
> > b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 96ebfe2..e1d6c35 100644
> > --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
> > +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
> > @@ -153,7 +153,11 @@
> >  	mov r1, #0x4
> >  	str r1, [r0, #CLKCTL_CCSR]
> >  
> > +#if defined(CONFIG_MX51_AVOID_PLL1)
> 
> If you add a new CONFIG_, you must document it in the README file.

Ah, ok, thanks for pointing out.

> Rather I cannot get a better feedback, I do not know this issue on the
> i.MX51. As you reported, it seems still unclear what happens.

Symptoms are sudden complete freeze of the ARM core, and either stable or
unstable image corruption on the LCD.

Best regards,

-- 
David Jander
Protonic Holland.