[U-Boot] [PATCH v2 1/2] gpio: Add GPIO driver framework for Marvell SoCs

[Simon Guinot <simon@sequanux.org>]

Hi Ajay,

On Fri, Jul 22, 2011 at 12:46:33PM +0530, Ajay Bhargav wrote:
> This patch adds generic GPIO driver framework support for Marvell SoCs.
> 
> To enable GPIO driver define CONFIG_MARVELL_GPIO and for GPIO commands
> define CONFIG_CMD_GPIO in your board configuration file.
> 
> Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
> ---
>  drivers/gpio/Makefile |    1 +
>  drivers/gpio/mvgpio.c |  114 +++++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 115 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/gpio/mvgpio.c

... snip ...

> +int gpio_direction_input(int gp)
> +{
> +	struct gpio_reg *gpio_reg_bank;
> +
> +	if (gp >= MV_MAX_GPIO) {
> +		printf("%s: Invalid GPIO %d\n", __func__, gp);
> +		return -EINVAL;
> +	}
> +
> +	gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp));
> +	writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gcdr);

AFAIK, Orion and Kirkwood SoCs don't provide bitwise set/clear for
GPIO output/direction registers. Instead, a register must be read
first to leave other bits unchanged (see __set_direction in kw_gpio.c).

Is it possible to handle Armada SoCs GPIOs in a same way ? maybe using
the pin registers (gpxx in the Armada struct gpio_reg array) ?

If not, this code is not Marvell generic but rather specific for Armada
SoCs and then maybe armada_gpio is a better name...

Regards,

Simon
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