From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marek.vasut@gmail.com>
Date: Thu, 11 Aug 2011 09:30:46 +0200
Subject: [U-Boot] [PATCH v4] ARM926ejs: Add routines to invalidate
	D-Cache
In-Reply-To: <4E437E7C.8030203@ti.com>
References: <1312944565-3279-1-git-send-email-hong.xu@atmel.com>
	<4E4226FE.4010805@aribaud.net> <4E437E7C.8030203@ti.com>
Message-ID: <201108110930.46500.marek.vasut@gmail.com>
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On Thursday, August 11, 2011 09:02:20 AM Aneesh V wrote:
> Hi Albert, Hong,
> 
> On Wednesday 10 August 2011 12:06 PM, Albert ARIBAUD wrote:
> > Hi Hong Xu,
> > 
> > Le 10/08/2011 08:17, Hong Xu a ?crit :
> >> There are some ARM926 specific code in arch/arm/lib/cache.c; So I also
> >> put the stuff there. ;-) I think Albert Aribaud or the original
> >> contributor of cache part shall have clearer view.So, I'll keep neutral
> >> to hear more ideas.
> > 
> > Basically, cache operations are CP15 commands which are defined for each
> > ARM architecture, not for each ISA, so Marek is right about the best
> 
> I am not sure if this is the case. I just quickly had a look at the
> ARMv5 and ARMv6 manuals. They are defining the CP15 instructions for
> cache operations(section 5.6.2 in ARMv5 manual and section B6.6.5 in
> the ARMv6 manual. And on first look, the CP15 operations look very
> similar
> 
> So, I feel that we can benefit many boards if Hong's operations are
> kept armv5/armv6 generic(you may have to carefully look at all
> operations and make sure they are valid for both armv5/v6).
> 
> My suggestion would be to create a new file in arch/arm
> /lib/cache_v5_v6.c and include this file in the build conditionally
> based on a config flag like CONFIG_SYS_ARM_CACHE_V5_V6_SUPPORT or
> something like that.  Any platform that wants to use these operations
> can then just enable this flag.
> 
> BTW, ARMv7 is not really backward compatible in the way the operations
> are done, because it provides the capability to find the levels of
> caches and repeat the operations at all levels where as up to armv6 the
> CP15 operations were only for Level 1.

That's actually not a bad idea, but we need to be definitelly 100% sure it'll 
work for all these different v5 and v6 cores !

> 
> I have not looked at the compatibility of ARMv4 operations.
> 
> best regards,
> Aneesh